JPS6214726U - - Google Patents
Info
- Publication number
- JPS6214726U JPS6214726U JP10586285U JP10586285U JPS6214726U JP S6214726 U JPS6214726 U JP S6214726U JP 10586285 U JP10586285 U JP 10586285U JP 10586285 U JP10586285 U JP 10586285U JP S6214726 U JPS6214726 U JP S6214726U
- Authority
- JP
- Japan
- Prior art keywords
- notch
- lead
- semiconductor device
- land portion
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000008188 pellet Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
第１図は本考案をモノリシツクＩＣに適用した
第１の実施例を示す半導体装置要部平面図、第２
図は第１図の要部拡大斜視図、第３図は本考案を
ハイブリツドＩＣに適用した第２の実施例を示す
半導体装置平面図、第４図は第３図の要部拡大斜
視図である。第５図はモノリシツクＩＣの具体例
を示す平面図、第６図は第５図の断面図、第７図
はハイブリツドＩＣの具体例を示す平面図、第８
図は第７図の断面図である。 １８……リードフレーム、１９……ランド部、
２０……切欠き部、２１，２１’……リード、２
１ａ，２１ａ’……先端部、２２……半導体ペレ
ツト。
第１の実施例を示す半導体装置要部平面図、第２
図は第１図の要部拡大斜視図、第３図は本考案を
ハイブリツドＩＣに適用した第２の実施例を示す
半導体装置平面図、第４図は第３図の要部拡大斜
視図である。第５図はモノリシツクＩＣの具体例
を示す平面図、第６図は第５図の断面図、第７図
はハイブリツドＩＣの具体例を示す平面図、第８
図は第７図の断面図である。 １８……リードフレーム、１９……ランド部、
２０……切欠き部、２１，２１’……リード、２
１ａ，２１ａ’……先端部、２２……半導体ペレ
ツト。
Claims (1)
- 【実用新案登録請求の範囲】 金属製のリードフレームのランド部上に、半導
体ペレツトを固着マウントし、上記ランド部の近
傍まで延びてくる複数のリードの先端部と半導体
ペレツトとを、金属細線で電気的に接続してなる
半導体装置において、 上記ランド部周縁の所望の箇所に切欠き部を形
成し、切欠き部に対応させて、所望のリードを延
設してそのリードの先端部を上記切欠き部に配置
したことを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10586285U JPS6214726U (ja) | 1985-07-11 | 1985-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10586285U JPS6214726U (ja) | 1985-07-11 | 1985-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6214726U true JPS6214726U (ja) | 1987-01-29 |
Family
ID=30980689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10586285U Pending JPS6214726U (ja) | 1985-07-11 | 1985-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214726U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006253681A (ja) * | 2005-03-07 | 2006-09-21 | Agere Systems Inc | 集積回路パッケージ |
-
1985
- 1985-07-11 JP JP10586285U patent/JPS6214726U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006253681A (ja) * | 2005-03-07 | 2006-09-21 | Agere Systems Inc | 集積回路パッケージ |