JPS61127635U - - Google Patents
Info
- Publication number
- JPS61127635U JPS61127635U JP936585U JP936585U JPS61127635U JP S61127635 U JPS61127635 U JP S61127635U JP 936585 U JP936585 U JP 936585U JP 936585 U JP936585 U JP 936585U JP S61127635 U JPS61127635 U JP S61127635U
- Authority
- JP
- Japan
- Prior art keywords
- land portion
- leads
- lead
- wire
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000008188 pellet Substances 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図乃至第４図は本考案に係る半導体装置の
実施例を説明するためのもので、第１図は本考案
をモノリシツクＩＣに適用した一実施例を示す平
面図、第２図は第１図のＡ―Ａ線に沿う拡大断面
図、第３図は本考案をハイブリツドＩＣに適用し
た実施例を示す平面図、第４図は第３図のＢ―Ｂ
線に沿う断面図である。第５図は従来のモノリシ
ツクＩＣの一例を示す平面図、第６図は第５図の
Ｃ―Ｃ線に沿う断面図である。 ６……半導体ペレツト、８……ボドデイングパ
ツド、１１……リードフレーム、１２……ランド
部、１４……リード、１４ａ……リード先端部、
１６……ワイヤ。
実施例を説明するためのもので、第１図は本考案
をモノリシツクＩＣに適用した一実施例を示す平
面図、第２図は第１図のＡ―Ａ線に沿う拡大断面
図、第３図は本考案をハイブリツドＩＣに適用し
た実施例を示す平面図、第４図は第３図のＢ―Ｂ
線に沿う断面図である。第５図は従来のモノリシ
ツクＩＣの一例を示す平面図、第６図は第５図の
Ｃ―Ｃ線に沿う断面図である。 ６……半導体ペレツト、８……ボドデイングパ
ツド、１１……リードフレーム、１２……ランド
部、１４……リード、１４ａ……リード先端部、
１６……ワイヤ。
Claims (1)
- 【実用新案登録請求の範囲】 リードフレームのランド部上に固着した半導体
ペレツトのボンデイングパツドと、ランド部の近
傍まで延びてくる複数のリードの先端部とを、ワ
イヤで電気的に接続してなる半導体装置において
、 前記リードのうち、所望のリードの先端部を略
Ｌ字状に屈曲形成したことを特徴とする半導体装
置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP936585U JPS61127635U (ja) | 1985-01-26 | 1985-01-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP936585U JPS61127635U (ja) | 1985-01-26 | 1985-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61127635U true JPS61127635U (ja) | 1986-08-11 |
Family
ID=30489515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP936585U Pending JPS61127635U (ja) | 1985-01-26 | 1985-01-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61127635U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007059884A (ja) * | 2005-07-22 | 2007-03-08 | Marvell World Trade Ltd | 高速集積回路用のパッケージング |
-
1985
- 1985-01-26 JP JP936585U patent/JPS61127635U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007059884A (ja) * | 2005-07-22 | 2007-03-08 | Marvell World Trade Ltd | 高速集積回路用のパッケージング |