JPS62146246U - - Google Patents

Info

Publication number
JPS62146246U
JPS62146246U JP2924486U JP2924486U JPS62146246U JP S62146246 U JPS62146246 U JP S62146246U JP 2924486 U JP2924486 U JP 2924486U JP 2924486 U JP2924486 U JP 2924486U JP S62146246 U JPS62146246 U JP S62146246U
Authority
JP
Japan
Prior art keywords
intermediate language
line number
program
execution
interrupt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2924486U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2924486U priority Critical patent/JPS62146246U/ja
Publication of JPS62146246U publication Critical patent/JPS62146246U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Devices For Executing Special Programs (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案によるプログラムデバツクの支
援機構の実施例を示すブロツク図、第2図は行番
号変換テーブルメモリに記録された原始プログラ
ム行番号と中間語プログラムの行番号との対応表
の一例を示す説明図、第3図は中間語インタプリ
タ方式の言語システムにおける本考案によるプロ
グラムデバツクの支援機構の動作を示す説明図、
第4図は従来の中間語インタプリタ方式の言語シ
ステムにおけるプログラムデバツグ作業を示す説
明図である。 1……原始プログラム、2……中間語コンパイ
ラ、3……中間語プログラム、4……中間語イン
タプリタ、5……キーボード、6……行番号変換
テーブルメモリ、6′……対応表、7……中断ロ
ケーシヨンレジスタ、8……比較器、S……一
致信号。
Fig. 1 is a block diagram showing an embodiment of the program debugging support mechanism according to the present invention, and Fig. 2 shows a correspondence table between source program line numbers and intermediate language program line numbers recorded in the line number conversion table memory. An explanatory diagram showing an example; FIG. 3 is an explanatory diagram showing the operation of the program debugging support mechanism according to the present invention in an intermediate language interpreter type language system;
FIG. 4 is an explanatory diagram showing program debugging work in a conventional intermediate language interpreter type language system. 1... Source program, 2... Intermediate language compiler, 3... Intermediate language program, 4... Intermediate language interpreter, 5... Keyboard, 6... Line number conversion table memory, 6'... Correspondence table, 7... ... Interrupt location register, 8... Comparator, S3 ... Match signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 原始プログラムを中間語コンパイラで中間語に
翻訳し、この中間語プログラムを中間語インタプ
リタで実行する言語システムの誤りを検出し修正
するプログラムデバツクの支援機構において、上
記原始プログラムの行番号と該原始プログラムを
中間語に翻訳した中間語プログラムの行番号との
対応表を記録する行番号変換テーブルメモリを設
けると共に、この行番号変換テーブルメモリに原
始プログラム上の実行中断の行番号を支持するキ
ーボードを設け、かつ上記行番号変換テーブルメ
モリから出力される行番号により中間語プログラ
ム上の実行中断の位置を記憶する中断ロケーシヨ
ンレジスタを設け、さらにこの中断ロケーシヨン
レジスタに記憶された行番号と中間語プログラム
の実行中の行番号とを一命令解釈実行サイクル毎
に比較する比較器を設け、この比較器が一致信号
を出力することにより中間語インタプリタの実行
を任意の位置で中断するようにしたことを特徴と
するプログラムデバツクの支援機構。
In a program debugging support mechanism that detects and corrects errors in a language system in which a source program is translated into intermediate language by an intermediate language compiler and this intermediate language program is executed by an intermediate language interpreter, the line number of the source program and the source A line number conversion table memory is provided to record a correspondence table between the line numbers of the intermediate language program translated into intermediate language, and a keyboard is provided in this line number conversion table memory to support the line number of the execution interruption in the source program. An interrupt location register is provided for storing the execution interrupt position in the intermediate language program based on the line number output from the line number conversion table memory, and the line number and intermediate language stored in the interrupt location register are also provided. A comparator is provided to compare the line number of the program being executed every instruction interpretation execution cycle, and this comparator outputs a match signal to interrupt the execution of the intermediate language interpreter at an arbitrary position. A program debugging support mechanism featuring:
JP2924486U 1986-03-03 1986-03-03 Pending JPS62146246U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2924486U JPS62146246U (en) 1986-03-03 1986-03-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2924486U JPS62146246U (en) 1986-03-03 1986-03-03

Publications (1)

Publication Number Publication Date
JPS62146246U true JPS62146246U (en) 1987-09-16

Family

ID=30832961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2924486U Pending JPS62146246U (en) 1986-03-03 1986-03-03

Country Status (1)

Country Link
JP (1) JPS62146246U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57100544A (en) * 1980-12-15 1982-06-22 Mitsubishi Electric Corp Debug device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57100544A (en) * 1980-12-15 1982-06-22 Mitsubishi Electric Corp Debug device

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