JPS6214472A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6214472A JPS6214472A JP15367985A JP15367985A JPS6214472A JP S6214472 A JPS6214472 A JP S6214472A JP 15367985 A JP15367985 A JP 15367985A JP 15367985 A JP15367985 A JP 15367985A JP S6214472 A JPS6214472 A JP S6214472A
- Authority
- JP
- Japan
- Prior art keywords
- film
- impurity
- pox
- source
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- 125000004429 atom Chemical group 0.000 claims abstract description 8
- 125000004430 oxygen atom Chemical group O* 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 8
- 239000011521 glass Substances 0.000 abstract description 8
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 60
- 238000005406 washing Methods 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 229910001750 ruby Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関するものであって、
薄膜トランジスタ（Ｔ Ｐ Ｔ）の製造に適用して最適
なものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device,
This method is most suitable for manufacturing thin film transistors (TPTs).
本発明は、半導体装置の製造方法において、不純物原子
と酸素原子との化合物層を低温プロセスにより半導体基
体上に形成し、熱処理を行うことにより、この化合物層
を不純物拡散源として半導体基体に不純物原子を拡散さ
せるようにすることにより、半導体基体に容易にしかも
低温で不純物拡散を行うことを可能にし、これによって
特性の良好な半導体装置を簡単な工程で製造可能とした
ものである。The present invention provides a method for manufacturing a semiconductor device, in which a compound layer of impurity atoms and oxygen atoms is formed on a semiconductor substrate by a low-temperature process, and heat treatment is performed to inject impurity atoms into the semiconductor substrate using this compound layer as an impurity diffusion source. By diffusing the impurity into the semiconductor substrate, it is possible to easily diffuse the impurity at a low temperature, thereby making it possible to manufacture a semiconductor device with good characteristics through a simple process.
従来、アモルファス５ｉＴＦＴまたは多結晶５ｉＴＦＴ
のソース領域及びドレイン領域は、ｎ゛層（またはｐＩ
層）により構成されている。これらのソース領域及びド
レイン領域は、いわゆるスタッガード（ｓ ｔａｇｇｅ
ｒｅｄ）型ＴＦＴの場合には気相成長により形成され、
またセルフアラインメント型ＴＰＴの場合にはイオン注
入またはＰＳＧ膜（またはＢＳＧ膜）を用いた不純物ド
ーピングにより形成されている。Conventionally, amorphous 5iTFT or polycrystalline 5iTFT
The source and drain regions of the n layer (or pI
layer). These source and drain regions are so-called staggered.
In the case of red) type TFT, it is formed by vapor phase growth,
In the case of a self-alignment type TPT, it is formed by ion implantation or impurity doping using a PSG film (or BSG film).
しかしながら、スタッガード型ＴＰＴにおいて気相成長
によりソース領域及びドレイン領域を形成する方法では
、これらのソース領域及びドレイン領域とゲート電極と
の重なりの面積を小さくすることが困難であるため、ソ
ース・ゲート間及びドレイン・ゲート間の容量が大きく
、このためスイッチング速度が小さい。のみならず、Ｔ
ＰＴのオン時に反転層とｎ層層（またはｐ層層）との間
に寄生抵抗（反転層となっていない真性半導体層）が存
在するためトランジスタ特性が悪い。However, in the method of forming source and drain regions by vapor phase growth in staggered TPT, it is difficult to reduce the area of overlap between these source and drain regions and the gate electrode. The capacitance between the capacitor and the drain and the gate is large, so the switching speed is low. Not only T.
When the PT is turned on, parasitic resistance (intrinsic semiconductor layer that is not an inversion layer) exists between the inversion layer and the n-layer (or p-layer), resulting in poor transistor characteristics.
またセルフアラインメント型ＴＦＴにおいてイオン注入
によりソース領域及びドレイン領域を形成する方法では
、イオン注入工程のコストが高いのみならず、注入不純
物イオンの活性化のために６００℃以上での熱処理を行
う必要があるという欠点がある。さらにｐｓｃ膜（ＢＳ
Ｇ膜）を不純物拡散源として用いてソース領域及びドレ
イン領域を形成する方法は、Ｐ （Ｂ）の拡散のために
高温の熱処理が必要であるのみならず、ソース領域及び
ドレイン領域を構成するｎ層層（またはｐ層層）とソー
ス電極及びドレイン電極とのコンタクトをとるためにＰ
ＳＧ膜（ＢＳＧ膜）のエツチング工程が必要であり、製
造工程数が多いという欠点がある。Furthermore, in the method of forming source and drain regions by ion implantation in self-alignment TFTs, not only is the cost of the ion implantation process high, but also heat treatment at 600°C or higher is required to activate the implanted impurity ions. There is a drawback. In addition, the psc film (BS
The method of forming source and drain regions using a G film) as an impurity diffusion source not only requires high-temperature heat treatment for diffusion of P (B), but also requires P to make contact between the layer (or p layer) and the source and drain electrodes.
This method requires an etching step for the SG film (BSG film), and has the drawback of requiring a large number of manufacturing steps.
本発明は、従来技術が有する上述のような欠点を是正し
た半導体装置の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that corrects the above-mentioned drawbacks of the prior art.
本発明者等は、上述のような従来技術の欠点を是正すべ
く鋭意研究を行った結果、次のような現象を見いだし、
本発明を案出するに至った。すなわち、まず例えばガラ
ス基板上に例えばａ −Ｓｉ膜を形成した後、ＰＩ（３
とＮｔＯ（またはＯｘ）との混合ガス（例えばＰＨｉ／
ＮｚＯ≧０．００１ ＞を反応ガスとして用いたプラズ
マＣＶＤ法により低温で気相成長を行う、これによって
上述のａ−５ｉ膜上にＰＯＸ膜が形成される。次にＳｉ
に強く吸収される波長の光、例えばエキシマ−レーザー
によるレーザービームによりＰ ＯＸ ／ ａ −Ｓｔ
界面近傍を局部加熱して、ａ−３ｉ膜を溶融させる。こ
の結果、ＰＯＸ膜中のＰがａ−Ｓｉ膜中に拡散してｎ層
が形成され、活性化も同時に行われる。The inventors of the present invention have conducted extensive research to correct the shortcomings of the prior art as described above, and have discovered the following phenomenon.
The present invention has been devised. That is, first, for example, an a-Si film is formed on, for example, a glass substrate, and then PI (3
and NtO (or Ox) (e.g. PHi/
Vapor phase growth is performed at low temperature by plasma CVD using NzO≧0.001 as a reaction gas, thereby forming a POX film on the a-5i film described above. Next, Si
POX/a-St is generated by a laser beam of a wavelength that is strongly absorbed by, for example, an excimer laser.
The a-3i film is melted by locally heating near the interface. As a result, P in the POX film is diffused into the a-Si film to form an n-layer, and activation is also performed at the same time.
上述のａ−３ｉ膜の代わりに多結晶Ｓｉ膜、単結晶Ｓｉ
膜等を用いた場合も同様にしてｎ層を形成することがで
きる。また上述のプラズマＣＶＤにおいてＢＪｂとＮＺ
Ｏ（またはＯＸ）との混合ガスを反応ガスとして用いれ
ば、ａ−５ｉ膜上にＢＯＸ膜が形成されるので、このＢ
ＯＸ膜中のＢをＳｉ中に拡散させることによってｐ層を
形成することができる。Polycrystalline Si film, single-crystalline Si film is used instead of the above-mentioned a-3i film.
Even when a film or the like is used, the n-layer can be formed in the same manner. In addition, in the plasma CVD described above, BJb and NZ
If a mixed gas with O (or OX) is used as a reaction gas, a BOX film will be formed on the a-5i film.
The p layer can be formed by diffusing B in the OX film into Si.
しかも上述のＰＯＸ膜及びＢＯＸ膜はいずれも水洗によ
って容易に除去することが可能であるので好都合である
。Moreover, both the above-mentioned POX film and BOX film can be easily removed by washing with water, which is advantageous.
本発明は上述のような実験結果に基づいて案出されたも
のである。The present invention was devised based on the above-mentioned experimental results.
すなわち本発明に係る半導体装置の製造方法は、不純物
原子と酸素原子との化合物層（例えばｐｏ。That is, the method for manufacturing a semiconductor device according to the present invention includes a compound layer of impurity atoms and oxygen atoms (for example, po.
膜５）を低温プロセスにより半導体基体（例えばａ−５
ｔ膜２）上に形成する工程と、熱処理（例えばレーザー
ビーム６によるビームアニール）を行うことにより、上
記化合物層を不純物拡散源として上記半導体基体に上記
不純物原子を拡散させる工程と、上記化合物層を除去す
る工程とをそれぞれ具備している。film 5) to a semiconductor substrate (e.g. a-5) by a low-temperature process.
t film 2), a step of diffusing the impurity atoms into the semiconductor substrate using the compound layer as an impurity diffusion source by performing heat treatment (for example, beam annealing with a laser beam 6), and a step of diffusing the impurity atoms into the semiconductor substrate using the compound layer as an impurity diffusion source. and a step of removing.
以下本発明の実施例につき図面を参照しながら説明する
。Embodiments of the present invention will be described below with reference to the drawings.
まず本発明をプレーナ型ＴＰＴの製造に適用した第１実
施例につき図面を参照しながら説明する。First, a first embodiment in which the present invention is applied to manufacturing a planar TPT will be described with reference to the drawings.
第１Ａ図に示すように、まず例えばガラス基板１上に従
来公知の方法と同様にしてａ−３ｉ膜２、ＳｉＯ□から
成るゲート絶縁膜３及び多結晶Ｓｉから成るゲート電極
４を形成した後、既述と同様な方法、すなわち例えばＰ
Ｈ３とＮ２０（または０□）との混合ガスを反応ガスと
して用いたプラズマＣＶＤ法により全面にＰＯ１Ｉ膜５
を形成する。As shown in FIG. 1A, first, an a-3i film 2, a gate insulating film 3 made of SiO□, and a gate electrode 4 made of polycrystalline Si are formed on, for example, a glass substrate 1 using a conventionally known method. , in the same way as described above, i.e. for example P
A PO1I film 5 is formed on the entire surface by plasma CVD using a mixed gas of H3 and N20 (or 0□) as a reaction gas.
form.
次に第１Ｂ図に示すように、室温において例えばエキシ
マ−レーザーによるレーザービーム６を上方より照射す
る。この際、ゲート電極４がａ−Ｓｉｌ［２へのエネル
ギー供給のマスクとして働く結果、ＰＯ，膜５がａ−Ｓ
ｉ膜２と直接接している部分においてＰＯｘＯｘ中のＰ
がａ−Ｓｉ膜膜中中拡散されて、ゲート電極４とセルフ
ァラインにｎ゛型のソース領域７及びドレイン領域８が
形成される。Next, as shown in FIG. 1B, a laser beam 6 of, for example, an excimer laser is irradiated from above at room temperature. At this time, as a result of the gate electrode 4 acting as a mask for energy supply to a-Sil[2, PO and film 5
In the part directly in contact with the i-film 2, P in POxOx
is diffused into the a-Si film to form an n'-type source region 7 and drain region 8 at the gate electrode 4 and self-alignment line.
次に上述のｐｏ、膜５を水洗により除去した後、第１Ｃ
図に示すように、ソース領域７及びドレイン領域８にそ
れぞれ電極９．１０を形成し、さらにＰＳＧ膜、Ｓｉｎ
、膜、Ｓｉ３Ｎ、膜等から成るパッシベーション膜１１
を全面に形成して、目的とするｎチャネルのブレーナ型
ＴＰＴを完成させる。Next, after removing the above-mentioned po and membrane 5 by washing with water,
As shown in the figure, electrodes 9 and 10 are formed in the source region 7 and drain region 8, respectively, and a PSG film and a Sin
, film, Si3N, film, etc., passivation film 11
is formed over the entire surface to complete the desired n-channel Brehner type TPT.
上述の第１実施例によれば、ａ −Ｓｉ膜膜上上ゲート
絶縁膜３及びゲート電極４を形成し、次いで全面にＰＯ
Ｘ膜５を形成した後、レーザービーム６を照射してＰＯ
，膜５からａ−Ｓｔ膜膜中中Ｐを拡散させることにより
ｎ゛型のソース領域７及びドレイン領域８を形成してい
るので、室温でソース領域７及びドレイン領域８を容易
に形成することができ、従って低温プロセスにより、低
融点のガラス基板１を用いてＴＰＴを製造することがで
きる。しかもゲート電極４に対してセルファラインにこ
れらのソース領域７及びドレイン領域８を形成すること
ができるので、ソース領域７及びドレイン領域８とゲー
ト電極４との重なりを小さくすることができる。従って
、ソース・ゲート間及びドレイン・ゲート間の容量を小
さくすることができるので、スイッチング速度の大きい
ＴＰＴを得ることができる。According to the first embodiment described above, the upper gate insulating film 3 and the gate electrode 4 are formed on the a-Si film, and then PO is formed on the entire surface.
After forming the X film 5, a laser beam 6 is irradiated to form the PO
Since the n-type source region 7 and drain region 8 are formed by diffusing P in the a-St film from the film 5, the source region 7 and drain region 8 can be easily formed at room temperature. Therefore, TPT can be manufactured using a low melting point glass substrate 1 by a low temperature process. Furthermore, since the source region 7 and drain region 8 can be formed in a self-aligned manner with respect to the gate electrode 4, the overlap between the source region 7 and the drain region 8 and the gate electrode 4 can be reduced. Therefore, the capacitance between the source and the gate and between the drain and the gate can be reduced, so that a TPT with a high switching speed can be obtained.
また従来のようにイオン注入や高温の熱処理を行う必要
がなく、さらにはＰＳＧ膜を不純物拡散源として用いた
場合に必要であったエツチング工程も不要となる。この
ため、製造工程の簡略化及び製造コストの低減を図るこ
とができる。のみならず、上述のＰＯｘ膜５は既述のよ
うに水洗により容易に除去することができるので、製造
上極めて有利である。Further, there is no need to perform ion implantation or high-temperature heat treatment as in the prior art, and furthermore, there is no need for an etching process that is necessary when a PSG film is used as an impurity diffusion source. Therefore, it is possible to simplify the manufacturing process and reduce manufacturing costs. In addition, the above-mentioned POx film 5 can be easily removed by washing with water as described above, which is extremely advantageous in manufacturing.
次に本発明をスタフガード型ＴＰＴの製造に適用した第
２実施例につき説明する。Next, a second embodiment in which the present invention is applied to manufacturing a stuffed guard type TPT will be described.
第２Ａ図に示すように、まずガラス基板１上に多結晶Ｓ
ｉから成るゲート電極４．５ｉＯｚから成るゲート絶縁
膜３及びａ−Ｓｉ膜２を形成した後、第１実施例と同様
にして全面にＰＯＸ膜５を形成する。As shown in FIG. 2A, first, polycrystalline S is placed on the glass substrate 1.
After forming the gate electrode 4.5 iOz and the a-Si film 2, a POX film 5 is formed on the entire surface in the same manner as in the first embodiment.
次に第２Ｂ図に示すように、ガラス基板１の下方から例
えばエキシマ−レーザーによるレーザービーム６を照射
する。この際、第１実施例におけると同様にゲート電極
４がａ−３ｉ膜２へのエネルギー供給のマスクとして働
く結果、ＰＯ，膜５中のＰがａ−５ｉ膜２中に拡散され
て、ゲート電極４に対してセルファラインにｎゝ型のソ
ース領域７及びドレイン領域８が形成される。Next, as shown in FIG. 2B, a laser beam 6 such as an excimer laser is irradiated from below the glass substrate 1. At this time, as in the first embodiment, as the gate electrode 4 acts as a mask for supplying energy to the a-3i film 2, PO and P in the film 5 are diffused into the a-5i film 2, and the gate electrode 4 acts as a mask for supplying energy to the a-3i film 2. An n-type source region 7 and drain region 8 are formed in self-alignment with respect to the electrode 4.
次に水洗によりＰＯＸ膜５を除去した後、第２Ｃ図に示
すように、ソース領域７及びドレイン領域８にそれぞれ
電極９．ｌＯを形成し、さらに全面にパッシベーション
膜１１を形成して、目的とするｎチャネルのスタフガー
ド型ＴＰＴを完成させる。Next, after removing the POX film 5 by washing with water, as shown in FIG. 2C, electrodes 9. 1O is formed, and a passivation film 11 is further formed on the entire surface to complete the intended n-channel stuffed guard type TPT.
この第２実施例によれば、第１実施例と同様に室温でソ
ース領域７及びドレイン領域８を容易に形成することが
できるので、低温プロセスにより、低融点のガラス基板
ｌを用いてスタフガード型ＴＰＴを製造することができ
る。しかも第１実施例と同様にソース領域７及びドレイ
ン領域８をゲート電極４に対してセルファラインに形成
することができるので１、ソース・ゲート間及びドレイ
ン・ゲート間の容量を小さくすることができ、従ってス
イッチング速度の大きいスタフガード型ＴＰＴを得るこ
とができる。のみならず、ａ−５ｉ膜２を薄くすること
により、ゲート電極４と多少の重なりが生ずるようにソ
ース領域７及びドレイン領域８を形成することができる
ので、ＴＰＴのオン時にこれらのソース領域７及びドレ
イン領域８とチャネルとの間に寄生抵抗、すなわち反転
層となっていない真性半導体層が存在せず、従ってＴＰ
Ｔの特性が良好である。According to the second embodiment, the source region 7 and the drain region 8 can be easily formed at room temperature as in the first embodiment, so a stuff guard type TPT can be manufactured. Moreover, as in the first embodiment, the source region 7 and the drain region 8 can be formed in a self-aligned manner with respect to the gate electrode 4, so that the capacitance between the source and the gate and between the drain and the gate can be reduced. Therefore, it is possible to obtain a stuffed guard type TPT with a high switching speed. In addition, by making the a-5i film 2 thinner, the source region 7 and drain region 8 can be formed so as to overlap with the gate electrode 4 to some extent. There is no parasitic resistance, that is, an intrinsic semiconductor layer that is not an inversion layer, between the drain region 8 and the channel, and therefore the TP
T characteristics are good.
以上本発明の実施例につき説明したが、本発明は上述の
２つの実施例に限定されるものではなく、本発明の技術
的思想に基づく種々の変形が可能である。例えば、上述
の２つの実施例において、Ｐ０８膜５の代わりに必要に
応じてｓｂｏ、膜やＡＳＯＩＩ膜を用いてもよい。さら
にＢＯＸ膜を用いることにより、ソース領域７及びドレ
イン領域８がｐ゛型であるｐチャネルのＴＰＴを製造す
ることができる。また上述の２つの実施例において用い
たａ−５ｉ膜２０代わりに多結晶Ｓｉ膜、単結晶Ｓｉ膜
、さらには必要に応じてＳｉ以外の半導体膜を用いるこ
とも可能である。同様に、必要に応じてガラス基板１の
他に石英基板等を用いることも可能である。Although the embodiments of the present invention have been described above, the present invention is not limited to the above two embodiments, and various modifications can be made based on the technical idea of the present invention. For example, in the two embodiments described above, instead of the P08 film 5, an sbo film or an ASOII film may be used as necessary. Further, by using the BOX film, it is possible to manufacture a p-channel TPT in which the source region 7 and drain region 8 are p' type. Further, instead of the a-5i film 20 used in the above two embodiments, it is also possible to use a polycrystalline Si film, a single crystal Si film, or even a semiconductor film other than Si if necessary. Similarly, it is also possible to use a quartz substrate or the like in addition to the glass substrate 1, if necessary.
さらに、上述の２つの実施例においては、不純物拡散を
行わせるための加熱源としてエキシマ−レーザーによる
レーザービームを用いたが、必要に応じてＹＡＧレーザ
−、ルビーレーザー等によるレーザービーム照射、電子
ビーム照射、ＩＲ照射等を用いてもよい。Furthermore, in the above two embodiments, a laser beam by an excimer laser was used as a heating source for impurity diffusion, but if necessary, laser beam irradiation by a YAG laser, ruby laser, etc., or electron beam irradiation could be used. Irradiation, IR irradiation, etc. may also be used.
さらにまた、ＰＯＸ膜５（またはＢＯ，膜）の除去は水
洗以外の方法、例えば所定のエツチング液を用いたウェ
ットエツチングやドライエツチングによっても行うこと
が可能である。Furthermore, the POX film 5 (or BO, film) can be removed by a method other than washing with water, such as wet etching or dry etching using a predetermined etching solution.
なお上述の２つの実施例においては、本発明をＴＰＴの
製造に適用した場合につき説明したが、その他の半導体
装置にも本発明を通用することが可能である。In the above two embodiments, the present invention is applied to the manufacture of TPT, but the present invention can also be applied to other semiconductor devices.
本発明に係る半導体装置の製造方法によれば、半導体装
置の特性に悪影響を与えないように半導体基体に容易に
しかも低温で不純物拡散を行うことが可能であるので、
特性の良好な半導体装置を低温プロセスにより製造する
ことが可能である。According to the method for manufacturing a semiconductor device according to the present invention, it is possible to easily diffuse impurities into a semiconductor substrate at a low temperature so as not to adversely affect the characteristics of the semiconductor device.
It is possible to manufacture a semiconductor device with good characteristics by a low-temperature process.
しかも製造工程の簡略化及び製造コストの低減を図るこ
とができる。Furthermore, it is possible to simplify the manufacturing process and reduce manufacturing costs.
第１Ａ図〜第１Ｃ図は本発明をプレーナ型ＴＰＴの製造
に適用した第１実施例を工程順に示す断面図、第２Ａ図
〜第２Ｃ図は本発明をスタッガード型ＴＰＴの製造に適
用した第２実施例を工程順に示す断面図である。
なお図面に用いた符号において、
ｌ・・・−・・・−・−・・−・・ガラス基板２−・・
・−・−一一−−−−・・−ａ−Ｓｔ膜４・−−−−一
−・−・・・−−−一一−−ゲート電極５−・・・・・
・・・・−・・−・ＰＯ，膜６−・−・−・・〜・−・
・−・−・・レーザービーム７−・−・−・−・−・−
・・・ソース領域８・・−−−一−・・−・・−・・・
−・・ドレイン領域である。Figures 1A to 1C are cross-sectional views showing the first embodiment in which the present invention is applied to the manufacture of a planar TPT, and Figures 2A to 2C are sectional views in which the present invention is applied to the manufacture of a staggered TPT. FIG. 7 is a cross-sectional view showing the second embodiment in the order of steps. In addition, in the symbols used in the drawings, l...-------...Glass substrate 2-...
・-・-11-------a-St film 4------1-----11--Gate electrode 5--
・・−・・−・PO, Membrane 6−・−・−・・〜・−・
・−・−・・Laser beam 7−・−・−・−・−・−
...Source area 8...---1-...
-...Drain region.
Claims (1)
り半導体基体上に形成する工程と、熱処理を行うことに
より、上記化合物層を不純物拡散源として上記半導体基
体に上記不純物原子を拡散させる工程と、 上記化合物層を除去する工程とをそれぞれ具備すること
を特徴とする半導体装置の製造方法。[Claims] By forming a compound layer of impurity atoms and oxygen atoms on the semiconductor substrate by a low-temperature process and performing heat treatment, the impurity atoms can be introduced into the semiconductor substrate using the compound layer as an impurity diffusion source. A method for manufacturing a semiconductor device, comprising the steps of diffusing the compound layer and removing the compound layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60153679A JPH0797565B2 (en) | 1985-07-12 | 1985-07-12 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60153679A JPH0797565B2 (en) | 1985-07-12 | 1985-07-12 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6214472A true JPS6214472A (en) | 1987-01-23 |
| JPH0797565B2 JPH0797565B2 (en) | 1995-10-18 |
Family
ID=15567792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60153679A Expired - Lifetime JPH0797565B2 (en) | 1985-07-12 | 1985-07-12 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0797565B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0215669A (en) * | 1988-07-01 | 1990-01-19 | Ricoh Co Ltd | Semiconductor device |
| US5656511A (en) * | 1989-09-04 | 1997-08-12 | Canon Kabushiki Kaisha | Manufacturing method for semiconductor device |
| US5933205A (en) * | 1991-03-26 | 1999-08-03 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for driving the same |
| US5956105A (en) * | 1991-06-14 | 1999-09-21 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
| US6713783B1 (en) | 1991-03-15 | 2004-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Compensating electro-optical device including thin film transistors |
| US6778231B1 (en) | 1991-06-14 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical display device |
| US6975296B1 (en) | 1991-06-14 | 2005-12-13 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5642336A (en) * | 1979-09-14 | 1981-04-20 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPS59218775A (en) * | 1983-01-19 | 1984-12-10 | Seiko Epson Corp | Manufacture of semiconductor device |
-
1985
- 1985-07-12 JP JP60153679A patent/JPH0797565B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5642336A (en) * | 1979-09-14 | 1981-04-20 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPS59218775A (en) * | 1983-01-19 | 1984-12-10 | Seiko Epson Corp | Manufacture of semiconductor device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0215669A (en) * | 1988-07-01 | 1990-01-19 | Ricoh Co Ltd | Semiconductor device |
| US5656511A (en) * | 1989-09-04 | 1997-08-12 | Canon Kabushiki Kaisha | Manufacturing method for semiconductor device |
| US6713783B1 (en) | 1991-03-15 | 2004-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Compensating electro-optical device including thin film transistors |
| US5933205A (en) * | 1991-03-26 | 1999-08-03 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for driving the same |
| US5963278A (en) * | 1991-03-26 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for driving the same |
| US5956105A (en) * | 1991-06-14 | 1999-09-21 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
| US6778231B1 (en) | 1991-06-14 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical display device |
| US6975296B1 (en) | 1991-06-14 | 2005-12-13 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
| US7928946B2 (en) | 1991-06-14 | 2011-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0797565B2 (en) | 1995-10-18 |
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| EXPY | Cancellation because of completion of term |