JPS62143445A - Method for forming multilayer interconnection - Google Patents
Method for forming multilayer interconnectionInfo
- Publication number
- JPS62143445A JPS62143445A JP28301485A JP28301485A JPS62143445A JP S62143445 A JPS62143445 A JP S62143445A JP 28301485 A JP28301485 A JP 28301485A JP 28301485 A JP28301485 A JP 28301485A JP S62143445 A JPS62143445 A JP S62143445A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring layer
- opening
- forming
- lower wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、半導体集積回路装置における多層配線の形
成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming multilayer wiring in a semiconductor integrated circuit device.
(従来の技術)
半導体集積回路装置(IC)において、多層配線は、従
来、第2図に示すようにして形成されている。すなわち
、まず、IC基板1上に絶縁膜2(例えば5iotまた
はPSG)を形成した後、該絶縁膜2上に第1配線層の
kl−8i系合金膜3を形成する。その後、該合金膜3
上に層間絶縁膜4(例えばPSG)を形成した後、この
層間絶縁膜4にホトリソ・エツチングによって開孔部5
を選択的に形成する。その後、前記開孔部5を通して前
記A/−8t系合金膜3(第1配線層)に接続される第
2配線層としてのAj−8i系合金膜6を前記層間絶縁
膜4上に形成する。(Prior Art) In a semiconductor integrated circuit device (IC), multilayer wiring is conventionally formed as shown in FIG. That is, first, an insulating film 2 (for example, 5iot or PSG) is formed on an IC substrate 1, and then a kl-8i alloy film 3 as a first wiring layer is formed on the insulating film 2. After that, the alloy film 3
After forming an interlayer insulating film 4 (for example, PSG) on top, openings 5 are formed in this interlayer insulating film 4 by photolithography and etching.
selectively formed. Thereafter, an Aj-8i alloy film 6 is formed on the interlayer insulating film 4 as a second wiring layer to be connected to the A/-8t alloy film 3 (first wiring layer) through the opening 5. .
しかしながら、このような方法では、開孔部5のアスペ
クト比が大きくなるに従って開孔部5の段差において第
2配線層(At−8i系合金膜6)のステップカバレー
ジが悪くなり、くびれ7を生じ、断線を起し?すくなり
、それを防止するのは困難でめった。However, in such a method, as the aspect ratio of the opening 5 increases, the step coverage of the second wiring layer (At-8i alloy film 6) deteriorates at the step of the opening 5, resulting in constriction 7. , caused a disconnection? It is difficult and rare to prevent this.
これに対して、従来の第2の方法として、特開昭54−
11.1795号公報に示される方法がある。この方法
は、第3図に示すように、IC基板ll上にStO,膜
12を設け、その上に第1配線層のAJ膜13を形成し
、更にその上に5i02膜14をCVD法により形成し
、そしてこのSin、膜14を選択エツチングして開孔
部15を作った後、無電解めっき法により、開孔部15
のAI!膜1膜上3上ッケルめっき層16を形成し、そ
の後、そのニッケルめっき層16と前記Sin、膜14
上に、前記ニッケルめっき層16を介してAI!膜13
(第1配線層)に接続される第2配線層としてのAI!
膜17全形成するという方法である。On the other hand, as the second conventional method,
There is a method disclosed in Japanese Patent No. 11.1795. In this method, as shown in FIG. 3, a StO film 12 is provided on an IC substrate 11, an AJ film 13 as a first wiring layer is formed thereon, and a 5i02 film 14 is further formed on it by CVD. After selectively etching the Sin film 14 to form the openings 15, the openings 15 are formed by electroless plating.
AI! A nickel plating layer 16 is formed on the film 1 film 3, and then the nickel plating layer 16 and the above-mentioned Sin, film 14 are formed.
On top, through the nickel plating layer 16, AI! Membrane 13
(AI as the second wiring layer connected to the first wiring layer)!
This is a method in which the entire film 17 is formed.
この方法において、ニッケルめっき層16は開孔部15
を埋め、表面は5102膜14の表面と同一平面となる
ように形成される。したがって、この方法によれば、開
孔部15における段差を解消でき、該部分での第2配線
層(A/膜17)の段切れを防止でき、かつニッケルめ
っき層16’r介して良好な層間接続を得ることができ
る。In this method, the nickel plating layer 16 is
The surface is formed to be flush with the surface of the 5102 film 14. Therefore, according to this method, it is possible to eliminate the level difference in the opening 15, prevent the second wiring layer (A/film 17) from being broken in this area, and provide a good Interlayer connections can be obtained.
(発明が解決しようとする問題点)
しかし、本発明者が上記第3図の方法を、上述した内容
で実験したとζろ、StO,膜14(層間絶縁膜)の開
孔部15にニッケルめっき層16は形成されなかった。(Problem to be Solved by the Invention) However, when the present inventor conducted an experiment using the method shown in FIG. Plating layer 16 was not formed.
したがって、上記方法では、実際のところは上述した効
果も得られていない。Therefore, the above method does not actually achieve the above effects.
この発明は上記の点に鑑みなされたもので、その目的は
、層間絶縁膜の開孔部を金属層で埋めるという多層配線
の形成方法において、前記開孔部を無電解めつき法によ
シ金属層で完全に埋めることができるようにした多層配
線の形成方法を提供することにある。The present invention has been made in view of the above points, and its object is to provide a method for forming a multilayer wiring in which the openings in an interlayer insulating film are filled with a metal layer, in which the openings are filled by electroless plating. It is an object of the present invention to provide a method for forming multilayer wiring that can be completely filled with a metal layer.
(問題点を解決するための手段)
この発明では、IC基板上の下層配線層の表面にPd層
を形成し、その後、下層配線層上に層間絶縁膜を形成し
、開孔部を開け、該開孔部に無電解めっき法で金属層を
形成する。(Means for Solving the Problems) In the present invention, a Pd layer is formed on the surface of a lower wiring layer on an IC substrate, and then an interlayer insulating film is formed on the lower wiring layer, and an opening is formed. A metal layer is formed in the opening by electroless plating.
(作用)
上記のように下層配線層の表面にPd層を形成すると、
その後、層間絶縁膜に開けた開孔部(該開孔部の下層配
線層上)に無電解めっき法で金属層を形成する際、開孔
部の底面にはPd層が活性層として露出することになる
。したがって、単にめっき浴に浸すだけで、開孔部に金
属層を形成できることになる。(Function) When a Pd layer is formed on the surface of the lower wiring layer as described above,
After that, when a metal layer is formed by electroless plating in the opening made in the interlayer insulating film (on the lower wiring layer of the opening), the Pd layer is exposed as an active layer on the bottom of the opening. It turns out. Therefore, a metal layer can be formed in the opening simply by immersing it in a plating bath.
(実施例) 第1図はこの発明の一実施例を示す工程断面図である。(Example) FIG. 1 is a process sectional view showing an embodiment of the present invention.
以下この一実施例について説明する。This embodiment will be described below.
まず、第1図(a)に示すように、IC基板21上にC
VD工程により絶縁膜22(例えば5i01またはP
S G )’t 6000λ厚に形成した後、その絶縁
膜22上に第1配線層金属膜としてAl−3i系合金膜
23を6000^厚に真空蒸着形成する。First, as shown in FIG. 1(a), C is placed on the IC board 21.
The insulating film 22 (for example, 5i01 or P
After forming the insulating film 22 to a thickness of 6000λ, an Al-3i alloy film 23 is vacuum-deposited to a thickness of 6000λ as a first wiring layer metal film.
そして、続けて、第1図(b)に示すように、AI!−
8i系合金膜23の表面に1o−too^厚iCPd
(ハラジウム)層24を活性層として真空蒸着形成する
。Then, as shown in FIG. 1(b), AI! −
10-too^ thick iCPd on the surface of the 8i alloy film 23
A (haladium) layer 24 is formed by vacuum evaporation as an active layer.
その後、Pd層24トAI!−8i系合金M23eM1
配線層ノ9ターンにノぐターニングした後、Pd/i*
24を表面に有するAl−8i系合金膜23(第1配線
層)上に第1図(C)に示すように層間絶縁膜25(例
えばPSG)を6000^厚にCVD法で形成する。After that, the Pd layer 24 and AI! -8i alloy M23eM1
After turning the wiring layer into 9 turns, Pd/i*
As shown in FIG. 1(C), an interlayer insulating film 25 (for example, PSG) is formed to a thickness of 6000^ on the Al-8i alloy film 23 (first wiring layer) having 24 on the surface by the CVD method.
その後、同図に示すように、層間絶縁膜25にホトリソ
・エツチングによって開孔部26を選択的に形成する。Thereafter, as shown in the figure, openings 26 are selectively formed in the interlayer insulating film 25 by photolithography and etching.
その上で、無電解ニッケル系めっき浴、例えばPH7〜
’l)約80℃0Ni−Pめっき浴に全体を浸す。する
と、前記比1図(c)に示すように、開孔部26内の、
表面にPl!24’に活性層として有するAt−8i系
合金換23上にニッケル系めっき層27が無電解めっき
法により選択的に形成される。ここで、ニッケル系めっ
き層27は、開孔部26を完全に埋め、表面が層間絶縁
腺25の表面と平担となるように形成する。Then, use an electroless nickel plating bath, for example, pH7~
'l) Immerse the entire body in a Ni-P plating bath of approximately 80°C. Then, as shown in FIG. 1(c), inside the opening 26,
Pl on the surface! A nickel-based plating layer 27 is selectively formed on the At-8i-based alloy 23 provided as an active layer at 24' by electroless plating. Here, the nickel-based plating layer 27 is formed so that the opening 26 is completely filled and its surface is flush with the surface of the interlayer insulation gland 25 .
その後、全体を水洗いして乾燥させた上で、第1図(d
)に示すように、前記ニッケル系めっき層27および層
間絶縁膜25上に、第2配線層金属膜としてのAl−8
i系合金膜28を真空蒸着形成する。After that, after washing the whole thing with water and drying it,
), on the nickel-based plating layer 27 and the interlayer insulating film 25, an Al-8 layer is formed as a second wiring layer metal film.
An i-based alloy film 28 is formed by vacuum evaporation.
その後、このAI!−8i系合金膜28を第2配線層・
ぐターンに/4?ターニングして第2配M層とする。こ
の第2配線層は前記ニッケル系めっき層27を介して第
1配線層(AI!−8i系合金膜23)に接続される。After that, this AI! -8i alloy film 28 as second wiring layer
Turn/4? Turning is performed to form a second M layer. This second wiring layer is connected to the first wiring layer (AI!-8i alloy film 23) via the nickel-based plating layer 27.
なお、このよりな一実施例は、2層配線にこの発明を応
用した場合であるが、この発明は、上記のような工程を
くり返して3層以上の多層配線を形成することもできる
。Although this more specific embodiment is a case in which the present invention is applied to a two-layer wiring, the present invention can also form a multilayer wiring of three or more layers by repeating the above steps.
また、上記一実施例では、第1配線層金属膜としてのA
l−8i系合金膜23を真空蒸着形成した後、続いてP
d層24を真空蒸着形成し、その後に両層を第1配線層
・ぞターンに・ンターニングしたが(換言すれば、Pd
層24をAI!−8i系合金膜230ツクターニングの
前に形成したが)、Pd層24をAI!−3i系合金膜
23の・ぐターニング後に真空蒸着形成してもよい。そ
の場合は、Pd層24のみの/にターニング(第1配線
層・ンターンと同一・ぐターン)が必要になる。Further, in the above embodiment, A as the first wiring layer metal film
After forming the l-8i alloy film 23 by vacuum evaporation, P
The d layer 24 was formed by vacuum evaporation, and then both layers were turned into the first wiring layer (in other words, the Pd
AI for layer 24! -8i alloy film 230 (formed before turning), Pd layer 24 is formed using AI! It may be formed by vacuum evaporation after the -3i alloy film 23 is turned. In that case, it is necessary to turn only the Pd layer 24 (same turn as the first wiring layer turn).
(発明の効果)
以上詳述したように、この発明の方法によれば、下層配
線層の表面にPd層を形成することにより、層間絶縁膜
の開孔部に無電解めっき法で金属層を形成する際は、前
記開孔部の底面にPd層が活性層として露出することに
なり、したがって単にめっき浴に浸すだけで開孔部を金
属層で完全に埋めることができる。また、Pd層は無電
解めっきの際の酸に対するバリアとして働くので、前記
酸による下層配線層の浸食も防止できる。(Effects of the Invention) As detailed above, according to the method of the present invention, by forming a Pd layer on the surface of the lower wiring layer, a metal layer is formed in the opening of the interlayer insulating film by electroless plating. During formation, the Pd layer is exposed as an active layer at the bottom of the opening, so that the opening can be completely filled with the metal layer simply by immersing it in a plating bath. Furthermore, since the Pd layer acts as a barrier against acid during electroless plating, it is possible to prevent the underlying wiring layer from being eroded by the acid.
そして、この発明によれば、上述のように開孔部に金属
層を完全に埋め込むことができたことにより、開孔部に
おける段差を解消でき、該部分での上層配線層の段切れ
を防止でき、かつ金属層を介して良好な層間接続金得る
ことができる。しかも、表面が平担な多層配線構造ひい
ては半導体集積回路装置が得られる。According to the present invention, since the metal layer can be completely buried in the opening as described above, it is possible to eliminate the level difference in the opening, and prevent the upper wiring layer from breaking at that part. It is possible to obtain a good interlayer connection through the metal layer. Moreover, a multilayer wiring structure and a semiconductor integrated circuit device with a flat surface can be obtained.
また、上記一実施例のように下層配線層金属膜を真空蒸
着形成した後、そのまま続けてPd層を真空蒸着形成す
れば、汚染のないクリーンな配線層を得ることができる
。Moreover, if the lower wiring layer metal film is formed by vacuum evaporation and then the Pd layer is formed by vacuum evaporation as in the above embodiment, a clean wiring layer without contamination can be obtained.
(図面)
第1図はこの発明の多層配線の形成方法の一実施例を示
す工程断面図、4@2図および第3図はそれぞれ従来の
多層配線の形成方法を説明するための断面図である。
21・・・IC基板、23・・・Al−8i系合金ノ換
、24・・・Pd層、25・・・層間絶縁膜、26・・
・開孔部、27・・・ニッケル系めっき層、28・・・
kl−8i系合金膜。
51図
第1図(Drawings) Fig. 1 is a process sectional view showing an embodiment of the method for forming multilayer wiring according to the present invention, and Fig. 4@2 and Fig. 3 are sectional views for explaining the conventional method for forming multilayer wiring, respectively. be. 21... IC substrate, 23... Al-8i alloy replacement, 24... Pd layer, 25... Interlayer insulating film, 26...
・Opening part, 27... Nickel-based plating layer, 28...
kl-8i alloy film. Figure 51 Figure 1
Claims (2)
)前記下層配線層の表面に活性層としてPd層を真空蒸
着で形成する工程と、 (c)これらの工程の後、前記下層配線層上に層間絶縁
膜を形成する工程と、 (d)その層間絶縁膜に選択的に開孔部を開ける工程と
、 (e)その開孔部の前記活性層を有する下層配線層上に
、開孔部を埋めるように金属層を無電解めつき法により
形成する工程と、 (f)その金属層と前記層間絶縁膜上に、前記金属層を
介して前記下層配線層に接続される上層配線層を形成す
る工程とを具備することを特徴とする多層配線の形成方
法。(1) A method for forming multilayer wiring on an IC substrate, comprising: (a) forming a lower wiring layer on the substrate; (b) forming a lower wiring layer on the substrate;
) forming a Pd layer as an active layer on the surface of the lower wiring layer by vacuum evaporation; (c) after these steps, forming an interlayer insulating film on the lower wiring layer; (d) (e) forming a metal layer on the lower wiring layer having the active layer in the opening by electroless plating so as to fill the opening; and (f) forming an upper wiring layer connected to the lower wiring layer via the metal layer on the metal layer and the interlayer insulating film. How to form wiring.
蒸着形成する工程は、下層配線層金属膜の真空蒸着形成
後、該金属膜の配線パターンへのパターニングの前にて
行うことを特徴とする特許請求の範囲第1項記載の多層
配線の形成方法。(2) The step of forming a Pd layer as an active layer by vacuum evaporation on the surface of the lower wiring layer is carried out after forming the lower wiring layer metal film by vacuum evaporation and before patterning the metal film into a wiring pattern. A method for forming a multilayer wiring according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28301485A JPS62143445A (en) | 1985-12-18 | 1985-12-18 | Method for forming multilayer interconnection |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28301485A JPS62143445A (en) | 1985-12-18 | 1985-12-18 | Method for forming multilayer interconnection |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62143445A true JPS62143445A (en) | 1987-06-26 |
Family
ID=17660107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28301485A Pending JPS62143445A (en) | 1985-12-18 | 1985-12-18 | Method for forming multilayer interconnection |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62143445A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5288664A (en) * | 1990-07-11 | 1994-02-22 | Fujitsu Ltd. | Method of forming wiring of semiconductor device |
-
1985
- 1985-12-18 JP JP28301485A patent/JPS62143445A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5288664A (en) * | 1990-07-11 | 1994-02-22 | Fujitsu Ltd. | Method of forming wiring of semiconductor device |
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