JPS62143445A - Method for forming multilayer interconnection - Google Patents

Abstract

PURPOSE:To completely fill an opening, provided in an interlayer insulating film, with a metal layer by only placing a substrate in a plating bath by a method wherein a Pd layer is formed on the surface of a lower wiring layer and, in a process of forming a metal layer by electroless plating in the opening, the Pd layer is caused to be exposed as an activation layer on the bottom of the opening. CONSTITUTION:A lower wiring layer 23 is formed on an interlayer insulating film 22 positioned on a substrate 21. On the surface of the lower wiring layer 23, a Pd layer 24 is formed by evaporation to serve as an activation layer. An interlayer insulating film 25 is formed on the lower wiring layer 23. An opening 26 is selectively provided in the interlayer insulating film 25. In the opening 26, on the lower wiring layer 23 provided with the activation layer, a metal layer 27 is formed by electroless plating to fill up the opening 26. An upper wiring layer 28 is then formed on the metal layer 27 and interlayer insulating film 25, to be connected to the lower wiring layer 23 with the intermediary of the metal layer 27. In this way, the opening 26 is completely filled by the metal layer 27 by only putting the entirety in a plating bath.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming multilayer wiring in a semiconductor integrated circuit device.

(Prior Art) In a semiconductor integrated circuit device (IC), multilayer wiring is conventionally formed as shown in FIG. That is, first, an insulating film 2 (for example, 5iot or PSG) is formed on an IC substrate 1, and then a kl-8i alloy film 3 as a first wiring layer is formed on the insulating film 2. After that, the alloy film 3
After forming an interlayer insulating film 4 (for example, PSG) on top, openings 5 are formed in this interlayer insulating film 4 by photolithography and etching.
selectively formed. Thereafter, an Aj-8i alloy film 6 is formed on the interlayer insulating film 4 as a second wiring layer to be connected to the A/-8t alloy film 3 (first wiring layer) through the opening 5. .

However, in such a method, as the aspect ratio of the opening 5 increases, the step coverage of the second wiring layer (At-8i alloy film 6) deteriorates at the step of the opening 5, resulting in constriction 7. , caused a disconnection? It is difficult and rare to prevent this.

On the other hand, as the second conventional method,
There is a method disclosed in Japanese Patent No. 11.1795. In this method, as shown in FIG. 3, a StO film 12 is provided on an IC substrate 11, an AJ film 13 as a first wiring layer is formed thereon, and a 5i02 film 14 is further formed on it by CVD. After selectively etching the Sin film 14 to form the openings 15, the openings 15 are formed by electroless plating.
AI! A nickel plating layer 16 is formed on the film 1 film 3, and then the nickel plating layer 16 and the above-mentioned Sin, film 14 are formed.
On top, through the nickel plating layer 16, AI! Membrane 13
(AI as the second wiring layer connected to the first wiring layer)!
This is a method in which the entire film 17 is formed.

In this method, the nickel plating layer 16 is
The surface is formed to be flush with the surface of the 5102 film 14. Therefore, according to this method, it is possible to eliminate the level difference in the opening 15, prevent the second wiring layer (A/film 17) from being broken in this area, and provide a good Interlayer connections can be obtained.

(Problem to be Solved by the Invention) However, when the present inventor conducted an experiment using the method shown in FIG. Plating layer 16 was not formed.

Therefore, the above method does not actually achieve the above effects.

The present invention has been made in view of the above points, and its object is to provide a method for forming a multilayer wiring in which the openings in an interlayer insulating film are filled with a metal layer, in which the openings are filled by electroless plating. It is an object of the present invention to provide a method for forming multilayer wiring that can be completely filled with a metal layer.

(Means for Solving the Problems) In the present invention, a Pd layer is formed on the surface of a lower wiring layer on an IC substrate, and then an interlayer insulating film is formed on the lower wiring layer, and an opening is formed. A metal layer is formed in the opening by electroless plating.

(Function) When a Pd layer is formed on the surface of the lower wiring layer as described above,
After that, when a metal layer is formed by electroless plating in the opening made in the interlayer insulating film (on the lower wiring layer of the opening), the Pd layer is exposed as an active layer on the bottom of the opening. It turns out. Therefore, a metal layer can be formed in the opening simply by immersing it in a plating bath.

(Example) FIG. 1 is a process sectional view showing an embodiment of the present invention.

This embodiment will be described below.

First, as shown in FIG. 1(a), C is placed on the IC board 21.
The insulating film 22 (for example, 5i01 or P
After forming the insulating film 22 to a thickness of 6000λ, an Al-3i alloy film 23 is vacuum-deposited to a thickness of 6000λ as a first wiring layer metal film.

Then, as shown in FIG. 1(b), AI! −
10-too^ thick iCPd on the surface of the 8i alloy film 23
A (haladium) layer 24 is formed by vacuum evaporation as an active layer.

After that, the Pd layer 24 and AI! -8i alloy M23eM1
After turning the wiring layer into 9 turns, Pd/i*
As shown in FIG. 1(C), an interlayer insulating film 25 (for example, PSG) is formed to a thickness of 6000^ on the Al-8i alloy film 23 (first wiring layer) having 24 on the surface by the CVD method.

Thereafter, as shown in the figure, openings 26 are selectively formed in the interlayer insulating film 25 by photolithography and etching.

Then, use an electroless nickel plating bath, for example, pH7~
'l) Immerse the entire body in a Ni-P plating bath of approximately 80°C. Then, as shown in FIG. 1(c), inside the opening 26,
Pl on the surface! A nickel-based plating layer 27 is selectively formed on the At-8i-based alloy 23 provided as an active layer at 24' by electroless plating. Here, the nickel-based plating layer 27 is formed so that the opening 26 is completely filled and its surface is flush with the surface of the interlayer insulation gland 25 .

After that, after washing the whole thing with water and drying it,
), on the nickel-based plating layer 27 and the interlayer insulating film 25, an Al-8 layer is formed as a second wiring layer metal film.
An i-based alloy film 28 is formed by vacuum evaporation.

After that, this AI! -8i alloy film 28 as second wiring layer
Turn/4? Turning is performed to form a second M layer. This second wiring layer is connected to the first wiring layer (AI!-8i alloy film 23) via the nickel-based plating layer 27.

Although this more specific embodiment is a case in which the present invention is applied to a two-layer wiring, the present invention can also form a multilayer wiring of three or more layers by repeating the above steps.

Further, in the above embodiment, A as the first wiring layer metal film
After forming the l-8i alloy film 23 by vacuum evaporation, P
The d layer 24 was formed by vacuum evaporation, and then both layers were turned into the first wiring layer (in other words, the Pd
AI for layer 24! -8i alloy film 230 (formed before turning), Pd layer 24 is formed using AI! It may be formed by vacuum evaporation after the -3i alloy film 23 is turned. In that case, it is necessary to turn only the Pd layer 24 (same turn as the first wiring layer turn).

(Effects of the Invention) As detailed above, according to the method of the present invention, by forming a Pd layer on the surface of the lower wiring layer, a metal layer is formed in the opening of the interlayer insulating film by electroless plating. During formation, the Pd layer is exposed as an active layer at the bottom of the opening, so that the opening can be completely filled with the metal layer simply by immersing it in a plating bath. Furthermore, since the Pd layer acts as a barrier against acid during electroless plating, it is possible to prevent the underlying wiring layer from being eroded by the acid.

According to the present invention, since the metal layer can be completely buried in the opening as described above, it is possible to eliminate the level difference in the opening, and prevent the upper wiring layer from breaking at that part. It is possible to obtain a good interlayer connection through the metal layer. Moreover, a multilayer wiring structure and a semiconductor integrated circuit device with a flat surface can be obtained.

Moreover, if the lower wiring layer metal film is formed by vacuum evaporation and then the Pd layer is formed by vacuum evaporation as in the above embodiment, a clean wiring layer without contamination can be obtained.

[Brief explanation of drawings]

(Drawings) Fig. 1 is a process sectional view showing an embodiment of the method for forming multilayer wiring according to the present invention, and Fig. 4@2 and Fig. 3 are sectional views for explaining the conventional method for forming multilayer wiring, respectively. be. 21... IC substrate, 23... Al-8i alloy replacement, 24... Pd layer, 25... Interlayer insulating film, 26...
・Opening part, 27... Nickel-based plating layer, 28...
kl-8i alloy film. Figure 51 Figure 1

Claims (2)

[Claims] (1) A method for forming multilayer wiring on an IC substrate, comprising: (a) forming a lower wiring layer on the substrate; (b) forming a lower wiring layer on the substrate;
) forming a Pd layer as an active layer on the surface of the lower wiring layer by vacuum evaporation; (c) after these steps, forming an interlayer insulating film on the lower wiring layer; (d) (e) forming a metal layer on the lower wiring layer having the active layer in the opening by electroless plating so as to fill the opening; and (f) forming an upper wiring layer connected to the lower wiring layer via the metal layer on the metal layer and the interlayer insulating film. How to form wiring. (2) The step of forming a Pd layer as an active layer by vacuum evaporation on the surface of the lower wiring layer is carried out after forming the lower wiring layer metal film by vacuum evaporation and before patterning the metal film into a wiring pattern. A method for forming a multilayer wiring according to claim 1.