JPS62143177A - Vector processor - Google Patents

Abstract

PURPOSE:To easily execute program debugging by interrupting the decoding processing of a vector instruction during the setting period of the 1st bit, and in the setting period of the 2nd bit, serially executing scalar processing and vector processing. CONSTITUTION:When an incorrect result is generated in a vector processor, a position generating the cause of the incorrect result in a program can be checked by interrupting the vector processing on an optional position in a DO loop and outputting the data to a main storage device 1 even when a variable referred in the DO loop or a value of an array does not exist in the main storage device 1 but exists in a register 6. Even when a variable or an array referred in the DO loop exists only in the register 6 of the processor, a value for debugging is substituted for the variable or array to retry the vector processing. In addition, parallel processing between the vector processing inherent in the vector processor and the scalar processing is suppressed and the defect of ordering for the reference of the main storage due to the parallel processing and a defect due to the rewriting of a vector instruction string can be easily extracted. Consequently, program debugging can be easily attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a vector processing bag (ξ), and more particularly to a vector processing device suitable for investigating the cause when an incorrect result is obtained by vector processing.

(Background of the Invention) In a processing device that is oriented toward vector calculation, especially in a vector processing device, it is necessary to prepare a depacking means that is more powerful than the depacking means in a general-purpose computer. When the program of process B is executed on a vector processing device, process A is Do
Since it has a block structure, it is executed by a vector arithmetic unit or a vector data transfer circuit. Hereinafter, the arithmetic units or data transfer circuits in the processing device will be collectively referred to as resources.

Vector calculations generally involve a very large amount of operations, and therefore consume a considerable amount of time even with high-speed vector resources. For this reason, it is common to perform control to start processing B (scalar processing) without waiting for the completion of processing A (vector processing). The program logic is processing A and B.
Parallel processing occurs only if the two can be executed independently.

If the program logic is correct and reflects the intentions of the program creator, it is possible to obtain valid results even if the above-mentioned 4ρ process is performed. However, if the program logic contains an error contrary to the intention of the program creator, it becomes difficult to detect the error if parallel processing as described above is performed. For example, if the program is correct, the array C read in process A and the area written in process B will not overlap in main memory, but because the Do control variable value happened to be incorrect,
This is a case where the pointer of array C has grown so large that it points to part of the area. In such a case, if the store processing in Process B overlaps in time with the readout of array C in Process A, which is vector processing, the time required for main memory reference in vector processing varies greatly depending on the processing situation.

The order of store processing and vector readout changes, and the reproducibility of the results is lost. Here, the processing status refers to the busy status of the main memory boat, etc. Therefore, the vector processing array C
The temporal ordering of reads and stores of scalar processing is no longer as specified in the program, and sometimes a correct result is obtained, and sometimes an incorrect result.

In addition, if a vector instruction is modified by the previous scalar processing, the vector processing device reads ahead of the instruction, so there is a possibility that the vector instruction before the modification is loaded into the instruction buffer and processed. If this instruction prefetch is related to data transfer between main memory and buffer storage, instruction rewriting may be enabled or disabled due to competition with other data transfer circuits of the processing device.

Achieving parallel processing in this way means breaking the order of processing defined in the program.

On the other hand, when we analyze the process of depacking a program, we find that the depacking process can be performed in an orderly manner, meaning that the logic written in the program is performed in order, and after the result of one statement is determined, the next statement is Requires a precondition to start processing.

This precondition is exclusive of parallel processing or vector processing. Therefore, some interface is required between the program and the hardware of the processing device to serialize the logical operations of the processing device or provide instructions that ensure the ordering of some logical operations.

In the past, in order to solve the difficulty of program debugging in parallel processing, there is an example of adding a maintenance architecture to a data flow machine (Hiraki, Nishiguchi, Sekiguchi, Shimada ``Science and Technology 11F Computing Data Drive''). ``Maintenance Architecture of J Computer S IGMA-1'', Information Processing Society of Japan 31st Conference Proceedings 6D-3)
. A data flow machine is a type of computer that performs parallel processing, but each instruction's arithmetic processing is executed independently. Therefore, the processing of the computer is interrupted at a certain specified point, and the information in the computer's internal registers, memory, etc.
By reading it using the maintenance architecture, it is possible to know the calculation status at a specified time.

On the other hand, vector calculations are executed by expanding DO loop processing into a set of Baku1Hel instructions, which have a different calculation method than scalar processing, so it is extremely difficult to stop vector calculations at any point. .

Even if this could be done, there is also the issue of how much information the transformed data during pipeline processing in the vector arithmetic unit can provide for program debugging. Therefore, it is considered appropriate to specify an appropriate interruption point for vector processing between vector instructions and to stop vector processing when the vector processing reaches this interruption point. Now let's consider what stopping vector calculations means for the vector processing device.

Back 1 to 1 processing begins with the decoding of a vector instruction and ends with the processing of all vector elements, but generally the time between the start and end of vector processing is limited to scalar instructions since multiple data are processed with one vector instruction. l−
~2 orders of magnitude longer. Therefore, even if the start of execution of a vector instruction is interrupted using a concept similar to scalar processing, vector instructions that have already been started will continue to operate without stopping for more than a few dozen machine cycles. However, depacking the source code of a program requires that the internal operations of the computer be completed and the processing results written to storage means such as main memory. It is necessary to wait for the resource to stop. Therefore, in order to depack vector processing, it is necessary to interrupt the start of a vector instruction at the target program position, wait for the completion of the vector instructions that have been executed before this interruption point, and then
Various depacking processes need to be initiated.

Depacking means converting the bit pattern on the storage means in the processing device into a character and
It is to output to. As this data conversion method, a method used in general-purpose machines and the like can be used. Therefore,
If the registers in the vector processor can be written to the main memory, software assets of conventional methods can be used. To facilitate discussion, storage means within the vector processor will be limited to vector registers.

In order to write the contents of the vector register to main memory, it is necessary to issue a vector store instruction.

However, the problem is how to issue this vector store instruction. This cannot be solved by embedding a vector store instruction in the vector instruction sequence in advance by specifying the depack mode of the compiler. In this store instruction embedding method, vector processing itself is performed without stopping, and only a trace of the vector calculation is obtained after a series of calculations is completed. Therefore, the important processes for program debugging are: 1. Stop the program processing, set an arbitrary data pattern in the storage means in the processing device at that point, and restart the processing device. 2. At the above-mentioned stop point. , outputting data at an arbitrary location in the storage means within the processing device, and restarting the processing device cannot be performed. Furthermore, due to the depack mode specification of the compiler, the vector instruction sequence changes by inserting an extra store instruction, and the processing status of the vector processor, especially the data processing status regarding main memory, is different from that in cases other than depack mode. It is.

Although the above discussion has been about vector registers, the same applies even if the storage means in the vector processor is replaced by vector mask registers or other registers. Due to these circumstances, the current situation is that a debugging method for vector processing devices has not yet been established.

[Purpose of the invention]

An object of the present invention is to provide a vector processing device that facilitates program debugging.

[Summary of the invention]

In order to debug a program in a vector processing device, the present invention provides an instruction (TVP instruction) for testing the processing status of a vector processor, an instruction (QVD instruction) for instructing interruption of vector instruction decoding processing, and an instruction (RDR instruction) that instructs to cancel the interruption of decoding processing;
An instruction (SBON instruction) that instructs to suppress the parallel execution of vector processing and scalar processing, and an instruction (SBOFF instruction) that instructs to cancel the suppression by this instruction are provided as an instruction series. On the other hand, in the control register used to exchange control between the scalar processor and the vector processor, there is a bit (
A bit (S bit) indicating serialization of scalar and vector processing is provided. Then, the D bit in the control register is set and reset by the QVD instruction and RDR instruction, and the S bit is set and reset by the 5BON instruction and S BOF.
Set and reset with F command. These allow program debugging of the vector processing device to be accomplished without any problems.

[Embodiments of the invention]

First, the basic concept of the present invention will be explained. In order to realize program debugging of a vector processing device, it is necessary to cooperate with four processing systems: hardware, architecture, compiler, and operation system (O8).

In terms of hardware, there are two types of storage means (
This storage means is provided with a control register (hereinafter referred to as S bit). The D bit indicates the instruction decoding interruption of the vector processor, and the S p! - instructs to serialize vector processing. When the D bit is turned on, the Squashi processor transfers control to the resident space of O8.

As a result, the user program clearing process is interrupted and the process of O8 is started. At this point, the vector processor is still processing the user program.

Therefore, while the search process is switched from the user space to the O8 space, the vector processing continues in the user space. This dual nature is different from the conventional concept of task switching. O8 performs processing to transfer control to an address stored at a specific address in the main memory.

Section 2 discusses the configuration of user space. Generally, user space is considered to be a single structure, and most programs configure their logic within this single structure. However, when an unpredictable event such as an address exception occurs in a user program, instead of abnormally terminating in user space, control is passed to O8 at the time the exception occurs, and ○S is There is a processing system that can set a user program execution environment for O8 so that control can be transferred to a second user space and processing can be continued in this new user space. This processing system is not necessarily a vector processing device. In such a processing system, a user program is executed not in a single user space but in two different user spaces. Hereinafter, these two types of user spaces will be referred to as type 1 user space and type 2 user space.
This is called the seed user space. The second type user space is a space to which control cannot be transferred unless an unpredictable event occurs in the first type user space, and a space to which program control cannot be transferred unless the O8 intervenes due to the above event. The operation of O8 in the present invention is similar to the control communication between the two types of user spaces described above, but differs in the following points.

Conventionally, switching between two types of user spaces is always performed at one point, and only after the operation of the processing device is completed. Here, we will define one point of action as follows. A two-dimensional space with time as the axis and the address of the main memory IT as the horizontal axis (this space belongs to a different classification from the user/O8 space.Hereinafter, this space will be referred to as π space). A general-purpose computer, ie, a computer, can be represented by a single line. Therefore, the words "one point of action" have meaning for a certain time.

In the switching operation of two types of user spaces, the processing device does not access both spaces at the same time. However, the vector processing device of the present invention draws a plurality of processing trajectories in the π space. Therefore, it is not ``one point of operation'' but ``multiple points of operation'' for a certain time, and two types of user spaces can be accessed by both scalar and vector processors at the same time. Therefore, two types of user spaces may both be processed at the same time.

Therefore, the following instruction set is prepared as an architecture.

The following processing instructions include: 1. An instruction to test the processing status of a vector processor (hereinafter referred to as T est Vector Processor)
It is called an or command. (abbreviation: TVP), 2. Reset D bit], vector instruction M, instruction to resume reading (Rest D bit and Re5)
This is called a tart instruction. (abbreviation: RDR), 3. Instruction to turn on and off the S bit (S bit on
or off, abbreviations are 5BON, 5BOFF), 4,
Command to return from the second type of user space to the first type of user space (this command is 5supervisor Ca1l (SV
C) instruction), as a vector processing instruction: 5. Instruction to interrupt vector instruction decoding and turn on the D bit (Quit vector decode instruction, abbreviated as 0VD) Next, compiler processing Let's talk about. The compiler needs to determine the boundaries between type 1 and type 2 user spaces. The compiler compiles both the user program and the depacking program loaded into the second type space. It is possible to predict the size of space of the second kind,
Therefore, the boundaries of both spaces can be determined.

The depack program loaded into type 2 user space must have a function that can output the contents of registers in any processing device to main memory and set values in any register when vector processing is interrupted. There is. For this reason, it is necessary to wait for the completion of processing by the vector processor at the beginning of the depack program (using the TVP instruction).

For users who perform depacking, the information they want to know is not the register values in the processing device or the data at absolute addresses in the main memory, but the values of variables or arrays used in the program at a specific time. Therefore, variables in the first type user space,
It is necessary to transfer the correspondence between the array, the register number in the processing device, and the location address on the main memory to the second type of user space.

In particular, vector processors store intermediate results of vector calculations in buffer registers called vector registers that are managed by the user program. and this vector register number. Therefore, this correspondence table of array variables and vector register numbers is passed between the first and second type user spaces, and this correspondence table is used to find the vector register number of the array or variable pointed out by the user, and their contents are must be written to the specified address in main memory. Regarding the exchange of this correspondence table, since both the first and second type of user space are one user space from the concept of multiple virtual space (MVS), it is necessary to allocate a specific address in the main memory to the correspondence table, or Just like a subroutine call, the address of this correspondence table may be stored in a specific general-purpose register to switch between type 1 and type 2 user spaces. However, the latter method is difficult to implement unless the vector processor has an architecture that does not directly write values to general-purpose registers. This is because when switching type 1/2 user space with a scalar processor, the vector processor has not yet completed instruction processing, and if the architecture is such that the contents of general-purpose registers can be changed during vector processing, the contents of general-purpose registers may be changed. This is because the value of can no longer be guaranteed.

When it becomes possible to exchange the correspondence table between variables, arrays, vector registers, or main memory addresses between type 1 and type 2 user spaces, load/store instructions for this correspondence table and vector instructions are activated (at this time, the RDR instruction ), the value of any register within the vector processor can be read or written.

Note that the QVD instruction is required again after the load/store instruction.

Such a method makes it possible to interrupt vector processing, read data in the internal registers and main memory of the vector processing device, and write specific data for depacking into these storage means. This is because a vector instruction decoding interrupt instruction embedded in a vector instruction string interrupts the instruction execution process of the scalar processor and starts the depack program. Therefore, some kind of artificial manipulation, that is, QVD instructions are inserted into the vector instruction sequence. However, this artifact has only a small effect on the processing of the vector processor. In other words, compared to scalar instructions, vector instructions have the following characteristics:
The point is that the instruction execution time is longer than the instruction decoding process. Therefore, within the vector processor, there is a high probability that the vector instruction has been completely decoded and is waiting for the resources necessary to execute the instruction to become available.

Therefore, the instruction decoding interrupt instruction (QVD) is included in the vector instruction sequence.
Even if an instruction is inserted, the effect is only on the instruction decoding circuit of the vector processing device, but not on the operational status of the resources. This point is different from the method of inserting load/store instructions into a vector instruction sequence for depacking. Therefore, inserting a vector instruction decoding interrupt instruction into a vector instruction is a modification to the program, but the degree of modification is local, and it is not necessary to make a major change to the program for depacking. It won't be.

Although the depacking method described above is sufficient for use as a swatch processing device, it is still insufficient for use as a vector processing device. The vector processing device can perform parallel operations of vector processing and other search processing. For this reason,
If this program unsuitable for parallel operation is coded by a user's mistake and the compiler cannot detect this unsuitability for parallel operation, malfunction with poor reproducibility may occur. In such a case, the depacking operation is
It is necessary to specify that a certain process in the program should be executed after a certain process. It is possible to implement this depacking operation by introducing a special statement. For example, in a supervisor macro, a task's boss/
There are wait commands, etc. However, in this method, if it becomes necessary to explicitly indicate the order relationship between multiple processes, the program becomes very complicated and difficult to write.

It also becomes difficult to decipher the program context. This is due to the fact that conventional programming language does not specify "when to perform processing." Therefore, this method cannot be adopted for determining whether or not it is appropriate to perform column ()p operations in a vector processing device.

In the present invention, the suitability of parallel operation of the vector processing device is realized as follows.

1. The user points out the range that the program wants to investigate.

2. The compiler inserts necessary scan instructions into the object code within the above range so that the S bit of the control register of the processing unit is turned on (SBON, 5BOF).
(using the F command).

3. As a result, the instruction decoding circuit of the scanning processor controls so that serialization of vector processing and other scanning processing is performed within a certain range of the program to be verified.

4. Compare the results when the program is executed using the serialization operation as described above and when the program is executed in parallel processing operation, and find out that the incorrect result is due to incorrect use of the parallel processing function of the vector processing device. Determine whether or not it has occurred.

By doing this, the program will run out of control and you will receive 5BO.
When the FF instruction is rewritten, the processing device performs serialization operation until the user program ends. However, this does not mean that the program devanok will be seriously hindered.

An embodiment of the present invention will be described below with reference to the drawings. In the instruction decoding process of a vector processing device, two types of instruction systems, scan and vector, are decoded by two instruction solution J parts, and instruction execution is controlled. shall be adopted. In this method, the decoding units for the scan and vector instructions are separated, so two types of instruction sequences can be executed independently, and parallel processing can be easily realized. In addition.

In addition to the instruction decoding process of the vector processing device, a single instruction decoding unit decodes a mixed instruction sequence of scat and vector instructions.
There is a method for controlling instruction execution, and since it uses a mixture of scan instructions and vector instructions, it is easy to control the two-top instructions, including guaranteeing the order of scan processing and vector processing. There is t,'iR. Of course, the present invention may adopt this method.

FIG. 1 is a block diagram of an embodiment of the present invention's vector processing device. In FIG. 1, 1 is a main memory device, and 8 is a main memory control circuit. Reference numeral 2 designates data transfer circuits (hereinafter referred to as requesters), and since there are five in this embodiment, they are distinguished by adding subscripts a, b, . . . , e. 3 is an instruction decoding circuit, and since there are two of these, subscripts a and b are added to distinguish them.

4 is a scalar arithmetic unit (general purpose, including floating point registers)
, 5 is an instruction activation circuit, 6 is a vector register, and 7 is a vector arithmetic unit. Since each resource of the vector processing device is controlled by two instruction decoding circuits 3a and 3b, they can be classified into a scalar processor section SP and a vector processor section vP, as indicated by dotted lines in FIG.

When the vector processing unit is activated, requester 2
a sends an instruction read request to the main memory control circuit 8 through a path 10;
Send to. The main memory control circuit 8 determines the bank to be accessed in the main memory device 1 from the main memory reference address of the instruction read request, and issues a read request to the bank. When there are multiple reference requests to the same bank of the main memory device, the main memory control circuit 8 determines the priority order among the reference requests.

Instructions read from the banks of main memory 1 pass through main memory control circuit 8 and pass through path 11 . Requester 2a.

It is sent to the instruction decoding circuit 3a via path 12.

The instruction decoding circuit 3a decodes the scalar instruction and passes instructions necessary for executing the instruction to the scalar arithmetic unit 4 and the requester 2b via a path 13.
．． Send via 14. A vector processing start instruction (hereinafter referred to as Execute V ec
It is called a tor processing instruction and is abbreviated as E.
(written as XVP), the instruction decoding circuit 3a passes path 15.
The requester 2c is instructed to read the vector instruction via the requester 2c. At the same time, the vector instruction decoding circuit 3b is activated by path 16. The requester 2c issues a read request to the main memory control circuit 8 using the path 17 in the same manner as when reading a scalar instruction.

A vector instruction read from main memory 1 is sent to instruction decoding circuit 3b through main memory control circuit 8, path 18, requester 2c, and path 19. The instruction decoding circuit 3b sends the decoded vector instruction to the instruction activation circuit 5. The instruction activation circuit 5 constantly manages the resource status of the vector processor section VP via paths 20 and 21. pass 20
．． 21 is the east line. When the resources necessary to execute the vector instruction are not available, the instruction activation circuit 5 selects the path 22.
The requester 2c requests to stop reading the vector instruction through
Notify. If the resource is vacant, the instruction activation circuit 5 performs activation processing on the resource necessary for executing the instruction via the path 23 (east line).

If the activated resource is Questa 2d or 2e,
The requester sends the request address to the main memory control circuit 8 using the path 24 or 25.

In the case of a load process, data is received via path 26 or 27 and written to the vector register 6 via path 28 or 29. In the case of store processing, the data on the vector register 6 is read out via the path 28 or 29.The actual operation is as follows:1.A vector register control circuit (not shown) reads data from the vector register side via the path 28.
29) and is sent to the main memory control circuit 8 via a path 26 or 27. If the activated resource is the vector arithmetic unit 7, the vector register 6 to be operated on is read out from the vector register 6, the operation is performed, and the result of the operation is written to the vector register 6 through the path 30.

Note that control regarding writing to and reading from the vector register 6 is not directly related to the present invention, and therefore the necessary configuration is omitted in FIG.

Next, the operation of the instructions required by the present invention will be explained using FIG.

FIG. 2 shows details of the instruction decoding circuits 3a and 3b of FIG. 1 and their peripheral circuits, and the same parts as in FIG. 1 are given the same numbers. The boundary between the scalar processor section SP and the vector processor section VP is indicated by a dotted line 57.

In FIG. 2, the counter 50 belongs to the address generation section of the NoriQuesta 2a in FIG. This counter 50
is counted up every cycle according to the instruction word length stored in the register 51, and sends the instruction successive address to the main memory control circuit via the register 91 and path 10.

The main memory control circuit 8 reads an instruction from a designated address in the main memory and sends it onto the path 11. The instruction on "Path 1" is passed through the register 65 and is processed by the comparator circuit 52.
TVP, 5BON, 5BOFF, EXVP, R in parallel
It is determined whether or not it is a DR command. The register 53 stores data for checking these five instructions. The instructions in register 65 are TVP, 5BON, 5BOFF, and E.
Pass 80-8 when either XVP or RDR (7)
"1" is sent on each of the four channels.

Register 54 is a control register, and flip-flop 55
．． 56 corresponds to the S and D bits of the control register.

When the 5BON instruction is detected by comparison circuit 52, flip-flop 55 is set to LL I II.

The instruction activation circuit 5, which manages resources within the vector processor, sends information on the path 31 as to whether the vector processor is busy or not (in this example, busy is set to 11).
1 II). The busy information of the vector processor section and the output of the flip-flop 55 are logically ANDed by an AND circuit 58 and sent onto a path 85. The signal on this path 85 causes counter 50 to stop operating. At the same time, the write enable of the register 65 is turned off. Therefore, the vector processor section is busy and the S bit of the control register 54 is L.
At the time of L I II, the reading of the swash instruction is interrupted, and the parallel processing of both the swash and vector processor sections is serialized.

When comparison circuit 52 detects the 5BOFF instruction, flip-flop 55 is reset by a signal on path 82.

When the comparison circuit 52 detects the EXVP instruction, the path 83
The upper signal activates counter 59. The counter 59 reads out the vector instruction shown in FIG. 1 and constitutes a part of the address generation section of the Questa 2c. When counter 59 is activated, it is counted up every cycle according to the vector instruction word length stored in register 6o, and sends an address onto path 17. Main memory control circuit 8 is path 1
A vector instruction is read from main memory according to the address sent out on path 18, and the vector instruction read out is stored in register 63. This vector instruction is checked by the comparison circuit 61 to see if it is a QVD instruction. The register 62 stores data for detecting a QVD instruction. QVD by comparison circuit 61
When an instruction is detected, a signal II 1 # is sent on path 86. This signal sets flip-flop 56 of control register 54 to II II II. The setting of the flip-flop 56 causes the counter 59 to stop operating through a path 87. At the same time, the write enable of register 63 is turned off. This interrupts the vector instruction decoding process.

Vector instructions other than QVD instructions pass through path 88 and are decoded by decoder 64, and decoded information is sent to instruction activation circuit 5.

When the comparison circuit 52 detects the RDR command, the signal becomes “1”.
is sent out on path 84. This signal resets flip-flop 56.

This enables the write enable of register 63 to be written via path 87, and at the same time restarts the operation of counter 59.

When the comparison circuit 52 detects the TVP command, the signal 111
++-H,? It is sent out on bus 80. The signal on path 80 is ANDed with the signal on path 31 by AND circuit 66, and the result is set in register 67. register 6
7 indicates a condition code, and when the TvP instruction is executed, the busy information of the vector processor section at that time becomes T.
It can be referenced by instructions after VP.

FIG. 3 is a detailed diagram of the instruction activation circuit 5 of FIG. 1. Third
In the figure, when a vector instruction is sent via path 150, it is stored in register 100. register 100
A resource determination circuit 10 determines what resources are required to execute the instruction.
given to 1.

A number of resources is determined. The resource determination circuit 101 can be configured by a storage means (for example, ROM) that reads a resource number using an operation code as an address. The output of the resource determination circuit 101 is decoded by a decoder 104. To simplify the explanation below, assume that two resources are allocated to execute the vector instruction on register 100. This allocation information is path 151, 152
are input to selectors 102 and 103 via. Register 105 holds the state of resources.

The state of a resource is managed by determining whether it is busy ("l") or not. Register 10 showing the status of multiple resources
5 are selected by selectors 102 and 103, and the results are set in registers 106 and 107. Therefore, the values in registers 106 and 107 indicate the busy state of the resource that executes the vector instruction in register 100.

The values of registers 106 and 107 are logically summed by OR circuit 108 and the result is sent onto path 22. If the signal on path 22 is II I 11, the vector instruction in register 100 cannot be executed, so this information is used to
The operation of the vector instruction requester 2c shown in the figure is suppressed.

The inverted signal of the logical sum of OR circuit 108 is sent onto path 153. If the signal on path 153 is 111 II,
This indicates that the vector instruction in register 100 can be executed. The outputs of the registers 106 and 107 are sent to the inverting circuit 12.
1, 122, a resource selection circuit 10 that selects a resource for executing a vector instruction in the register 100;
9 is input. Resource selection circuit 109 selects resources according to predetermined priorities. The output of the resource selection circuit 109 corresponds to each resource, and when a certain signal on the path 154 becomes II III II, it is indicated that the corresponding resource has been selected. The signal on path 154 is AN
The logical AND is performed by the D circuit 110, and the result is passed to the path 15.
5 and becomes a set signal for register 105. Register 105 is reset by the resource vector instruction processing completion report signal on path 21.21.

The vector instruction stored in register 100 is transferred to register 111 when the signal on path 153 is 1''. The opcode of the vector instruction in register 111 is path 1.
56 and is input to the order generation circuit 112. The order generation circuit 112 generates order information necessary for executing a vector instruction by referring to a storage means such as a ROM using the operation code as an address. The output of the order generation circuit 112 passes through a path 156, is sorted according to resource by the switching circuit 113, and is sent out via a path 23 to the resource that executes the instruction. Similarly, the operand of the vector instruction on register 111 is path 157.
The signals are sorted according to resources by the switching circuit 114 and sent out onto the path 23.

Each resource busy information in the register 105 is sent to the OR circuit 11.
5, and the result is sent out over path 31.

The signal on path 31 is used as a signal indicating that the vector processor section is busy.

FIG. 4 is a detailed diagram of the resource selection circuit 109 in FIG. 3, and for convenience of explanation, shows a case where four resources are selected. In FIG. 4, information that any of the four resources is available is transmitted through paths 200a to 200a.
given by d. FIG. 4 shows an example in which path 200a has the highest priority, followed by paths 200b and 200c, and path 200d has the lowest priority. , and all higher-order signals are LL OII, the corresponding signal is selected. Therefore, even if multiple signals on paths 200a to 200d are "1", the output on path 154 will be the priority one. Only the signal on the path corresponding to the high 1 resource becomes "1".

〔Effect of the invention〕

According to the present invention, when a vector processing device obtains an incorrect result, an investigation is performed to find out in which part of the program the cause of the error has occurred, by interrupting vector processing at an arbitrary location within the D○ loop. ○ Even if the value of a variable or array referenced in a loop does not exist in the main memory but exists in a register in the vector processing unit, output that data to the main memory and examine it. I can do it. Further, even if a variable or array referenced in the Do loop exists only in a register within the processing device, it is possible to assign a value for depacking and retry vector processing.

Furthermore, by suppressing the parallel processing of vector processing and scalar processing specific to vector processing devices, it is possible to easily report defects caused by the order of main memory references caused by parallel processing and defects caused by vector instruction sequence rewriting. can.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the vector processing device of the present invention, FIG. 2 is a detailed diagram of a portion related to instruction reading and decoding in FIG. 1, and FIG. 3 is an instruction activation circuit in FIG. 1. FIG. 4 is a detailed diagram of the resource selection circuit in FIG. 3. 1... Main memory device, 8... Main memory control circuit, 2a~
2e...Requester (data transfer circuit), 3a, 3
b...Instruction decoding circuit, 4...Scalar arithmetic unit, 5...
...Instruction activation circuit, 6...Vector register, 7
...Vector arithmetic unit. Figure 4

Claims (1)

[Claims] a main memory device that stores programs and data; a scalar processor that reads scalar instructions from the main memory device and executes scalar processing; and a scalar processor that is activated by the scalar processor and reads vector instructions from the main memory device to perform vector processing. In a vector processing device equipped with a vector processor that executes a vector processor, in order to debug a program, a first instruction that tests the processing status of the vector processor, and a second instruction that instructs to interrupt the decoding process of the vector instruction are used. a third instruction that instructs to cancel the suspension of decoding processing caused by the second instruction, a fourth instruction that instructs to suppress parallel execution of vector processing and scalar processing, and a third instruction that instructs to suppress parallel execution of vector processing and scalar processing; and a fifth instruction that instructs release, and a control register used for transferring control between both processors, which is set by the second instruction and reset by the third instruction. and a second bit that is set by the fourth instruction and reset by the fifth instruction, and interrupts the decoding process of the vector instruction while the first bit in the control register is set. , A vector processing device characterized in that scalar processing and vector processing are executed serially during the setting period of the second bit.