JPH0744401A - Logic integrated circuit and its data processing system - Google Patents

Abstract

PURPOSE:To control efficiently a multi-processor comprising plural CPUs. CONSTITUTION:An area of a general-purpose register used by one process is limited so that data for the general-purpose register are not saved in an external memory at the changeover of the execution process in an RISC processor and plural processes are reserved by dividing the area of the general-purpose register. In the division of the general-purpose register, a management register is provided, which reserves information of the division of the general-purpose register and information for the process changeover and a register address when an instruction is read is converted into an address of the general-purpose register when the instruction is decoded, As the division information for the case, the address of the general-purpose register to each process is referenced by the management register. Furthermore, two program counters are provided in one CPU, the one program counter is used for the execution process and the other is used for an auxiliary use and set in the execution standby state and an optional process in the standby is allocated to the divided general-purpose register.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effectively applied to an arithmetic circuit in a logic integrated circuit, and more particularly to a technique effectively applied to a microprocessor having a large-capacity general-purpose register and a data processing system.

[0002]

2. Description of the Related Art In recent years, the performance of microprocessors has dramatically improved with the development of RISC processors. In general, this RISC processor is a microprocessor that is composed of only simple instructions so that each pipeline can be executed in one machine cycle in order to make full use of pipeline technology to speed up the operation. And
As shown in FIG. 2, in this RISC processor,
Since the operating frequency is high and one instruction is simple, a large capacity and a large number of instructions are required, and a primary cache memory and a secondary cache memory with a built-in CPU are provided. Then, the data of the general-purpose register that is less frequently executed is also saved in the main memory. Therefore, operations between the primary cache memory, the secondary cache memory, the main memory and the general-purpose registers in the CPU that disturb the flow of the pipeline and hinder the speedup, the secondary cache memory and the primary cache The operation between the cache memories is avoided, and only the operation between the general-purpose register and other general-purpose registers is performed. Further, for the same reason, in this RISC processor, a complicated one depending on the context of the pipeline, which is represented by the auto increment / decrement which determines the next address so that the next data can also be read, which is seen in the CISC processor, is complicated. Addressing mode is not adopted. FIG. 3 shows a conceptual diagram of pipeline processing of a general RISC processor. In this RISC processor, a series of operations such as instruction reading, instruction decoding, general-purpose register designation, ALU operation, and write back are performed in a pipeline to execute instructions. When the memory is accessed, one stage is added between the arithmetic unit ALU and the write back in order to shorten the memory access. However, in the CISC processor, in order to reduce the programming man-hours at the assembler level by the programmer, complicated instructions and addresses are taken in, and the reduction of the processing speed due to the disturbance of the pipeline is neglected. In addition, the CISC processor has a problem in that instruction execution is slowed because extra cycles are required due to the disturbance of the pipeline. On the other hand, the RIS
In the C processor, a general-purpose register is designated by performing an operation on a general-purpose register as a reference and an index.
Since the address modification can be performed in one cycle by using the index modification addressing mode only by the operation between general-purpose registers, the RISC processor can execute the instruction in one cycle. However, in the existing processor regardless of the RISC processor or the CISC processor, a method in which one execution process occupies the general-purpose register is adopted. Therefore, in order to reduce the data transfer of the data saved in the external memory from the external memory to the general-purpose register, a large number of general-purpose registers are provided. Then, the variables that are most frequently used are left in the general-purpose registers, and the variables optimized by the compiler are optimized by the compiler. As described above, in the conventional RISC processor, in addition to the improvement of the hardware technique, the improvement of the software technique is largely responsible. However, most computer systems, workstations, and the like support a multitasking system that switches processes in a time-sharing manner so that multiple pieces of software can be executed simultaneously, so it is necessary to switch between multiple execution processes within a certain period of time. . At this time, if a large number of general-purpose registers are occupied by one execution process, the data stored in the large number of general-purpose registers must be saved to an external memory on the operating system (hereinafter referred to as OS) when switching processes. Will not happen. As a result, data is saved by the addressing between the external memory and the general-purpose register, which causes an unnecessary delay time from the application software being executed. On the other hand, existing computer systems, workstations, etc., which are premised on a single-chip processor configuration, have a save time that does not sacrifice the throughput of the entire system due to saving the data when switching processes. This was done by limiting the number of general-purpose registers so that it could be done. However, in a computer system including a multi-chip processor, it becomes necessary to allocate each processor in units of execution processes, which complicates the process switching means and further increases the delay time at the time of process switching, which causes the same problem. Has occurred. For this reason, in the conventional OS, the RISC processor only decides the selection means of a plurality of processes.
In the OS for multiprocessor, it is necessary to select the processor in addition to that. Also, distributed OS
In the above, since software is configured by a subroutine-level finer process such as a thread, process switching must be frequently performed. Therefore, when the RISC processor architecture as described above is applied to a multiprocessor, it is necessary to distribute all programs to each processor. As a result, frequent process switching is performed, pipeline processing is hindered, and saving of data in the external memory of the general-purpose register imposes a heavy burden on the entire system.

[0003]

The present invention is intended for the next generation O
To provide a microprocessor having high-speed process management and register management functions capable of supporting S, and to provide a microprocessor having a management function for efficiently controlling a multiprocessor such as one LSI having a plurality of CPUs. With the goal.

[0004]

In the RISC processor, the area of the general-purpose register that can be used by one process is limited so that the data of the general-purpose register does not have to be saved to the external memory when the execution process is switched. This process can be secured by the division in the general-purpose register. Then, a management register that secures information on division and process switching in the general-purpose register is provided, and the register address in the register group at the time of reading the instruction is converted to the general-purpose register address at the time of decoding the instruction. As the division information at that time, the value of the program counter for each process of the general-purpose register is referenced from the management register. Furthermore, 1C
Two program counters are provided in the PU, one is used as a process for execution, and the other program counter is used as an auxiliary, and is assigned to any process waiting in the split register as an execution wait state.

[0005]

The microprocessor having the register dividing function can have a plurality of process information in one CPU, and can switch processes within one to several cycles. As a result, it is possible to minimize the amount of data saved in the external memory of the general-purpose register when switching the execution process, and to significantly reduce the switching time. Also, by performing parallel processing with other processes, when an instruction code that cannot be executed due to a delay slot is detected in the instruction code being executed, the program counter is switched to the waiting process, and the instruction code becomes executable. By replacing, the disturbance of the pipeline can be reduced.

[0006]

【Example】

(Embodiment 1) FIG. 1 shows a processor of the present invention which performs process switching by hardware. General-purpose register Rg0
˜Rg255, a general-purpose register file composed of 256 general-purpose registers is grouped by 16 general-purpose registers, and Grp0 to Grp1.
Divide up to 5 into 16 groups. Here, in the present invention, group division is performed without adding hardware for division to the general-purpose register file itself, but a grouping method will be described later. A management register is configured corresponding to each general-purpose register group in the general-purpose register, and a management register group is configured by the number of management registers corresponding to the number of groups of the general-purpose register. Further, in each of the management registers, a preset value of the program counter PC or a value PC * of the program counter PC at the time of process interruption is stored, and flag information is also stored. Here, the above-mentioned execution status flag needs at least a bit indicating execution and execution waiting. When reading and writing this execution status flag, there are a method of reading and writing a certain execution status flag for each register number of each management register, and a method of reading and writing an individual bit indicating the execution status in each of the above management registers. In the method of reading and writing the individual bit indicating the execution status in each management register, the position of the read status bit and the management register number match. A specific example of this is shown in FIG. In FIG. 4, the general-purpose register group Grp.
0 in the management register 0 corresponding to the flag of the general register group Grp. It is assumed that the flag of the management register 1 corresponding to 1 is in the execution waiting state. The management register has a flag having an in-execution bit and an execution-waiting state bit, and the general-purpose register group Gr.
p. Since 0 is in the execution state, the flag of the 0-bit management register is set, and the flag of the 0-bit executing bit is set. Here, the general-purpose register group Grp. In order to switch 1 to the running state, all bits of the running state bit are scanned and it is determined that the flag of the running bit of 0 bit is on. Then, the in-execution bit in the 0-bit flag of the management register is cleared to switch to the execution waiting state, and the in-execution bit flag of 1 bit is set. By this, the in-execution bit and the execution wait bit are switched. Further, connected to the general-purpose register, an arithmetic unit ALU for performing a logical operation between designated general-purpose registers is configured. There are provided a data cache memory and an instruction cache memory that always accumulate data in the main memory and read from the main memory when there is no data to be read. And these cache memories are 1
A secondary cache memory and / or a secondary cache memory, wherein the instruction cache memory reads a code instruction and the data cache memory reads / writes data to be referenced from a register. Further, the data cache memory inputs / outputs bidirectional data and reads the address of the program counter PC via an address line. On the other hand, the instruction cache memory is connected to a fetch circuit that fetches the input instruction, and the fetch circuit is connected to a decode circuit DCR. The instruction decoded by the decoding circuit DCR is connected as a control signal to a logic circuit such as a management register, a general-purpose register, and an arithmetic unit ALU,
One of them is taken into the process switching circuit. Here, this process switching circuit is connected to the decoding circuit DCR when a process switching instruction is generated, and is composed of a save processing block, a selection algorithm block, and a restoration block.
The save processing block, the restore block, and the selection algorithm block are connected to the switching control line connected to the register control line, and the value PC * of the program counter PC and the execution state flag information stored in the management register are stored in the management register. To control. Further, the register group signal Grp is selected by the selection algorithm block.
# Is generated and data is transferred to the management register and the general-purpose register group. The register group signal Grp # is for designating the allocated general-purpose register group. Further, the management register and the general-purpose register group are connected to the input data bus and the output data bus. Then, the data output from the management register and the general-purpose register group is transferred to the arithmetic unit ALU which is addressed and accessed by the decoding circuit DCR and also to the program counter PC. Further, the output data from the program counter PC is accessed to the management register and the general-purpose register group via the input data bus. Further, the management register is made to correspond to the general-purpose register group on the OS in a one-to-one manner. When Grp0 is designated, the management register a is designated, and the process stored in the management register a is assigned to the general-purpose register group Grp0. The data to be recorded in the management register is not particularly limited,
It shall include the execution data when the execution was interrupted. Therefore, in this embodiment, if the general-purpose register group Grp0 is designated when the execution is interrupted for one register group signal Grp #, the management register a corresponding to the general-purpose register group Grp is assigned. Stored value of the program counter PC PC *
That is, two pieces of data, that is, an execution state flag and the execution state flag are held. Here, the general-purpose register group Grp0
The flag of the management register a corresponding to is the execution state flag being executed, and the flag of the management register b corresponding to the general-purpose register group Grp1 is the execution state flag in the standby state.

Next, the initial setting operation and process switching operation of this processor will be described.

First, a method of grouping general-purpose registers will be described. Although not shown in particular, a reset signal is input to the processor to clear the flag data of the management register group, and only the management register for activation is set to the execution state. A PC value at the time of startup is stored in advance in the management register for startup, and this value is transferred to the program counter PC to permit reading from the memory to the CPU. As a result, the boot program is loaded into the CPU, and the OS is booted so that the OS can be booted.
Necessary data is secured in the management register and general-purpose register therein, allocation of data on the memory, setup of peripheral input / output devices, and the like are performed. Then, when the preparation is completed, the OS is started up, and processes other than the boot-up management registers are also allocated under the OS management. Here, the process assigned to the management register is O
Whether processing S itself or controlling the periphery of the I / O device,
The application launched by S is not particularly limited.

Next, the data transfer procedure of the processor of this embodiment when switching processes will be described. Here, the general-purpose register file is divided into 16 groups as described above, and the general-purpose register group G
It is assumed that rp0 is in the execution state and the process is switched to the general-purpose register group Grp1.
The process switching instruction is output from the data cache memory and the instruction cache memory. Then, the data cache memory addresses the register via the data bus, and the instruction cache memory fetches the process switching instruction into the processor via the fetch circuit. Then, the instruction fetched by the fetch circuit is transferred to the decode circuit DCR, the instruction is decoded, the operation content of the arithmetic unit ALU is selected, and the data of the operation content is transferred to the arithmetic unit ALU. Further, the data output from the decoding circuit DCR is input to the process switching circuit.

Next, a processing method in this process switching circuit will be described below. First, in the save block, the register control line is accessed through the switching control line to select the management register a being executed. Then, the value PC * of the program counter is held in the program counter PC, and the value PC * of the program counter is overwritten in the management register a via the input data bus. Then, the execution state flag stored in the management register a is read onto the switching control line via the register control line, and the execution state flag is switched to the standby state. Next, in the selection algorithm block, the process to be executed next is selected from the execution waiting flag, and the register group signal Grp # is generated to specify the general-purpose register group corresponding to the process. Then, in the latch circuit, the register group signal Grp # generated from the selection algorithm block is generated.
The general-purpose register group Grp1 is selected while holding, and the management register b is designated by this.
Further, in the restoration block, the management register b is designated by the register control line accessed through the switching control line, and the value PC * of the program counter stored in the management register b is set to the output data bus. The value PC * of this program counter is set in the above-mentioned program counter PC while being read out.
Then, the management register b is calculated from the register group number read by the bit number in the selection algorithm block, and the flag in the standby state stored in the management register b is set to the same bit as that during execution of the execution state flag. Switch. Then, the first instruction of the selected process is read from the instruction cache memory into the fetch circuit, whereby the process switching operation is completed and the next process is executed. Further, all processes need not be managed only by the process switching circuit and the management register, but can be managed by the main memory. In fact, the number of processes managed by the OS is enormous, and it is not possible to manage all the processes with the management registers in the processor CPU. Therefore,
When the present invention is used on the OS, the process in the execution waiting state that is most frequently used is stored in the management register, and the process whose execution has been terminated or suspended stores the management register data in the main memory. Here, the processing performed by the OS is the processing of saving from the management register to the main memory, the processing of copying the data of the process in the execution waiting state on the main memory to the management register, and the management register. It includes the process of selecting the process to be copied. By the way, when there is data in the memory, the data which is rarely used in the management register and general-purpose register groups Grp0 to 15 is transferred from the data cache memory to the management register group by program control or automatic control. To do. Until the switching work is completed, the processor CPU
Assumes that the next instruction is not executed. This switching method can be implemented by both software and hardware, but in the case of software, at least one management register is occupied by initiating the switching process. Further, in the related art, a general process occupies a general-purpose register file, so several tens of cycles are consumed for saving work. Therefore, in order to achieve high speed using this method, it is preferable to incorporate it in hardware. However, in this case, the general-purpose register file itself is not added with hardware for division, but the register address allocated in process units is converted into the address of the general-purpose register file. Here, although the ALU is described as the arithmetic unit in the present embodiment, the Floa is used instead.
toning Point Processing Un
By using it, the load on the software of the entire system can be further reduced.

(Embodiment 2) FIG. 5 shows a processor in which the management register has a function of arbitrarily selecting a general-purpose register group even when the number of management registers does not match the number of general-purpose register groups. In the present embodiment, each management register of the management register group of the first embodiment also stores data relating to the group number of the general-purpose register. In the present embodiment, the data grp * relating to the general-purpose register group numbers stored in the management registers a and b will be described below as data of the general-purpose register groups Grp0 and Grp2, respectively. First, similar to the first embodiment, general-purpose registers are grouped like Grp0 and Grp2, and the value PC of the program counter PC is set on the OS.
* Is set in each of the above management registers, and execution status flag data and group number data g
Store rp *. Then, the management register designation of the management register group is performed by inputting the start address, and the process corresponding to the general-purpose register group is transferred to the general-purpose register group corresponding to the management register and executed.

Next, the process switching method of the processor according to the present embodiment will be described. Here, the general-purpose register file is divided into an arbitrary number of groups as described above, and the management register a in which the data of the general-purpose register group Grp0 is stored as the group number data grp *.
In the execution state, the process is switched to the management register b in which the data of the general-purpose register group Grp2 is stored as the group number data grp *. A switching instruction is generated from the instruction cache memory,
The instruction cache memory fetches a switching instruction into the processor via the fetch circuit. Then, the instruction fetched by the fetch circuit is transferred to the decode circuit DCR, and the data is input to the process switching circuit. Next, the data transfer method in this process switching circuit will be described in detail below.
First, in the save processing block, the register control line is accessed via the switching control line to select the management register a being executed. Then, the value P of the program counter
C * is held in the program counter PC, and further the value PC * of the program counter is input via the input data bus.
Is overwritten on the management register a. Then, the execution state flag stored in the management register a is read onto the switching control line via the register control line, and the execution state flag is switched to the standby state. Next, the process to be executed next is selected in the selection algorithm block, and the data is transferred to the return block. Then, in this restoration block, the management register b is designated by accessing it through the register control line connected to the switching control line. Then, the data of the general-purpose register group Grp2 of the group number data grp * stored in the management register b is read out onto the switching control line via the register control line. The group number data grp read from the management register b
Grp as general-purpose register group data as *
Register group signal Gr for selecting 2 data
The general-purpose register group Grp2 is designated while generating p # and holding the signal in the latch circuit. At this time, the value PC * of the program counter stored in the management register b is read out through the output data bus, and the value PC * of the program counter is read.
* Is set in the program counter PC. Then, the management register b is calculated from the register group number read by the bit number in the selection algorithm block, and the flag in the standby state stored in the management register b is set to the same bit as that during execution of the execution state flag. Switch. Then, the first instruction of the selected process is read from the instruction cache memory into the fetch circuit, whereby the process switching operation is completed and the next process is executed. Here, as in the first embodiment, all processes need not be managed only by the process switching circuit and the management register.
It can also be managed in main memory. In fact, the number of processes managed by the OS is enormous, and it is not possible to manage all the processes with the management registers in the processor CPU. Therefore, when the present invention is used on the OS, the process in the execution waiting state that is most frequently used is stored in the management register, and the process whose execution has been completed or suspended saves the management register data in the main memory. Here, the processing performed by the OS is the processing of saving from the management register to the main memory, the processing of copying the data of the process in the execution waiting state on the main memory to the management register, and the management register. It includes the process of selecting the process to be copied. Moreover, conventionally, several tens of cycles are consumed by occupying the general-purpose register file in one process, so it is preferable to incorporate it in hardware in order to increase the speed using this method. However, in this case, the general-purpose register file itself is not added with hardware for division, but the process is switched. Further, although the ALU is described as the arithmetic unit in this embodiment, the FLU is used instead.
The use of PU can further reduce the load on the software. Furthermore, when the number of general-purpose register groups is larger than the number of management registers and the number of management registers corresponding to the above general-purpose register groups is insufficient, the corresponding management register groups are divided by software and newly created on the memory. This is dealt with by creating a proper management register. In this embodiment, since the process data on the general-purpose register can be referred to by software, the usability for the user becomes much better than in the first embodiment.

(Embodiment 3) By applying the present invention to FIG. 6, a plurality of fetch circuits, decode circuits, and arithmetic units are provided, and the same number of program counters as the arithmetic units are provided.
The multiprocessor formed in one LSI is shown.
In this embodiment, one management register group and a general-purpose register file are provided so as to be commonly accessible to all the processors, and the management register group and the general-purpose register file are divided to correspond to each processor to receive an instruction. 6 will be described as an example of a multiprocessor having two processor CPUs. In other words, in the present embodiment, a plurality of processor elements do not occupy one general-purpose register group,
The number is determined for each processor, and the number of the assigned processor is registered in the execution status flag of the management register. Therefore, here, the processor CPU1 includes the program counter PC1 and the arithmetic unit A.
Including a processor element PE1 constituted by LU1;
Similarly, the processor CPU2 includes the processor element PE2. Further, in this embodiment, as shown in FIG. 6, a data cache memory and an instruction cache memory are provided commonly to the processors CPU1 and CPU2. On the other hand, in the related art, as shown in FIG.
As described above, a dedicated built-in cache memory is provided for each processor CPU, and a shared bus for accessing the respective processor CPUs is provided to commonly access the secondary cache memory for each processor. Therefore, even if the processors CPUs are different chips, the data saved in the secondary cache memory is read from the same data area by different processes and the results saved in the secondary cache memory are the results of either process. , The results of other processes are erased. Further, since the wrong data may be read when another process that depends on the same data is started, access to such data is prohibited by the OS. However, in the present embodiment, as shown in FIG.
A data cache memory and an instruction cache memory corresponding to the PU1 and the processor CPU2 are provided in common, and by checking the processor number of the process to be executed in the management register, it is possible to avoid data collision between the processes, and the internal cache is provided. Since the data transfer is performed by the memory, the time required for checking the data area by the OS can be reduced, and high speed processing can be easily achieved. Here, although not particularly limited,
Since the data cache memory and the instruction cache memory of this embodiment generate instruction codes for the number of processors, a multiport memory is used. Also,
In this embodiment, a fetch circuit, a decode circuit, a data bus, an address bus, etc. are provided for each processor CPU, but the process switching circuit is the same as the data cache memory and the instruction cache memory, regardless of the number of processors. It is provided for common access.

The process switching method of the multiprocessor of this embodiment will be described below. First, similar to the first embodiment, general-purpose registers are grouped like Grp1a and Grp2a, and the respective values PC * of the program counters PC1 and PC2 are set in the respective management registers and the execution state The processor element data PE * stored together with the flag data is stored. Then, the management register designation of the management register group is performed by inputting the start address, and the process corresponding to the general-purpose register group is transferred to the general-purpose register group corresponding to the management register and executed.

Next, the data transfer procedure of the multiprocessor of the present embodiment at the time of process switching will be described. In this embodiment, as an example, a processing method in the case of performing process switching in a general-purpose register group corresponding to one processor CPU will be described below. Here, the processors CPU1 and CPU2 are respectively processor elements PE1 and PE.
In addition to corresponding to 2, the general-purpose register file is divided into the same number of groups as the management registers. Therefore, the general-purpose register group Grp1a is in the execution state in the processor CPU1, the general-purpose register group Grp2a is in the execution state in the processor CPU2, and the process is switched to the general-purpose register group Grp1b in the processor CPU1. A process switching instruction to the processor CPU1 is generated from the data cache memory and the instruction cache memory, and the processor CPU
In No. 2, the process switching instruction is not generated. Then, the instruction cache memory fetches a process switching instruction into the processor CPU1 via the fetch circuit 1. Then, the instructions respectively fetched by the fetch circuit 1 are transferred to the decode circuit DCR1, and the decode circuit D
The data output from CR1 is input to the process switching circuit. On the other hand, in the fetch circuit 2, the process switching instruction in the processor CPU2 is not generated from the instruction cache memory. Therefore, the instruction for executing the specified operation content in the arithmetic unit ALU2 corresponding to the processor element PE2 is held via the decode circuit DCR2, no data is input to the process switching circuit, and the processor executing the instruction is held. Element PE
2 and the processes in the management register 2a are held and executed. In this way, the decoding circuit DC
The instruction to the process switching circuit is fetched only from the decoding circuit in which the process switching instruction is decoded like R1.

Next, a processing method in this process switching circuit will be described below. First, in the save block, the register control line is accessed via the switching control line to select the management register 1a being executed. Then, the value PC * of the program counter is held in the program counter PC1 of the processor element PE1, and the value PC * of the program counter is overwritten in the management register 1a via the input data bus 1. Then, the execution state flag stored in the management register 1a is read onto the switching control line via the register control line, and the execution state flag and the data of the processor element PE1 held therein as the processor element data PE * are read. To the standby state.
Next, in the selection algorithm block, the next execution process is selected from the execution waiting state flag, and the register group signal Grp # is generated to specify the general-purpose register group corresponding to the selected process. Then, the latch circuit holds the register group signal Grp # generated from the selection algorithm block while selecting the general-purpose register group Grp1b, whereby the management register 1b is designated. Further, in the return block, the management register 1b is designated via the switching control line, and the value PC * of the program counter PC1 stored in the management register 1b is set in the program counter PC1. Then, the management register 1b is calculated from the register group number read by the bit number in the selection algorithm block, and the standby state flag stored in the management register 1b is used as the execution state flag, while the processor element PE1 is being executed. Switch to the same bit as that. Also, the management register 1b
The data read from the general-purpose register group Grp1b is calculated by the arithmetic unit ALU1.
Then, when the execution restart instruction is generated from the instruction cache memory, the process switching operation is completed and the process is executed. Here, when there is data on the OS, the less frequently used data in the management register and the general-purpose register group is saved in the data cache memory or the instruction cache memory by program control or automatic control, and the cache is saved. Transfers required data from memory to management registers. This switching method can be implemented by both software and hardware, but software requires a switching process. Further, conventionally, several cycles are consumed by occupying one process general-purpose register file, so that it is preferable to incorporate it in hardware in order to achieve high speed using this method.
However, in this case, the general-purpose register file itself is not added with hardware for division, but the process is switched. Here, although the ALU is described as the arithmetic unit in the present embodiment, the load on the software can be further reduced by using the graphic accelerator instead, or by using the ALU and the graphic accelerator in parallel, and in one cycle. Instructions can be executed and high-performance arithmetic processing becomes possible. In the case of a graphic accelerator, by considering each graphic instruction as a process, the normal CPU
High-speed processing is possible because there is no dependency for each process, unlike the process in. Further, in this embodiment, since the processor element data PE * is stored in each management register being executed, other processor elements can be shared.

(Embodiment 4) By applying the present invention to FIG.
A processor in which a plurality of program counters are provided for one processor so as to support high-speed process switching on a cycle-by-cycle basis is shown. Conventionally, RISC
For processors such as processors that perform pipeline processing on a cycle-by-cycle basis, evaluation delays due to conditional branch instructions and delays due to load / store of memory cause
There is a problem that an instruction that does not enter the pipeline is not executed as a delay slot and one cycle is consumed. The present embodiment is a method for reducing this, and like the program counters PC1 and PC2, a plurality of program counters are provided for one processor, and addresses indicating a process in execution and a process in non-execution are provided. It holds the data, switches the program counter in cycle units, and uses the instruction code properly. Then, a selector is provided for selecting one of the program counters PC1 and PC2 for switching the process being executed and the process not being executed, and
PC * for selecting the value PC * of the program counter in the management register corresponding to the general-purpose register group corresponding to each of the program counters PC1 and PC2
Provide a selector. Then, the program counter P
It sets the value PC * of the program counter in C1 and PC2, and controls the management register and the general-purpose register group. Furthermore, when a delay slot is input as an external instruction, a delay slot detection circuit for detecting the instruction is provided between the instruction cache memory and the fetch circuit. Since the delay slot detection circuit needs to operate the selector when the delay slot is detected, the delay slot detection circuit and the selector are connected. Further, the latch circuit for the pipeline stage in the above embodiment can be divided into the PC1 and PC2, respectively.

Here, FIG. 8A shows the content of the instruction stored in the instruction cache memory, and FIG.
Shows a diagram of instruction execution. This Figure 8
8A and 8B will be described below. Figure 8
In the data executed by the program counter PC1 in (a), DS1 and DS2 are delay slots and contain the same instruction code for executing nothing. Further, the program counter PC2 is a process selected from the processes waiting to be executed, and is a process in a running state that may be executed at any time.
After the process of C1 is completed, PC2 becomes the main execution process. Before fetching the instruction, the address indicated by the program counter PC1 is set to the delay slot DS1.
, The selector in the delay slot is detected, the selector is switched to the program counter PC2, and the instruction code that is not the delay slot is read as fetch data. Similarly, the delay slot DS2 also reads the instruction code executed by the program counter PC2 as fetch data. When executing the instruction code of the program counter PC1, the arithmetic unit A
The LU operates between general-purpose register groups, and when executing the instruction code of the program counter PC2, the LU operates between general-purpose register groups. In this way, by using the program counter PC1 as an auxiliary program for filling the pipeline with instructions, it becomes possible to execute one instruction per cycle for one processor. However, since the instruction code of the program counter PC2 has a delay slot without exception, the program counter PC2 also needs to detect the delay slot. This is because the delay slot cycle may be detected and consumed during the execution of the program counter PC1, so that the delay slot is rarely included in the fetch cycle.

Next, the data transfer procedure of the method of switching the program counter of the processor in this embodiment will be described with reference to FIGS. 7, 8A and 8B.
Further, since the process switching operation is similar to that of the first embodiment,
The description is omitted. The program counter PC1 shown in FIG.
In the following, description will be made assuming that the instruction is switched from the delay slot DS1 of the PC1 in FIG. First, N to do nothing
The OP instruction is output from the instruction cache memory. Then, the NOP instruction is read into the delay slot DS detection circuit via the instruction cache memory, and it is detected that the instruction from the instruction cache memory is the delay slot DS1. Then, the process switching is designated to the selector, the data for switching the program counter is transferred, and the program counter PC1 being executed is switched to PC2. The instructions fetched by the fetch circuits are transferred to the decode circuits DCR, the instructions are decoded, the operation content of the arithmetic unit ALU is selected, and the operation content data is transferred to the arithmetic unit ALU. Furthermore, the decoding circuit D
The data output from the CR is taken into the management register and the general-purpose register, OP22 is executed in the management register 2a, and the next instruction is generated from the instruction cache memory, whereby the program counter PC1 is switched to.

Here, in this embodiment, an ALU is used as an arithmetic unit.
However, by using the graphic accelerator instead, or by using the ALU and the graphic accelerator in parallel, the load on the software can be further reduced and high-performance processing can be performed. In the present embodiment, when the number of general-purpose register groups is small or when the general-purpose register group is treated as a special register, the management register is not necessarily required as long as the general-purpose register and the corresponding program counter are in correspondence. Two or more program counters can be set. Then, one program counter is always used for execution, and the other program counters are used for delay slot replacement.

(Embodiment 5) FIG. 9 shows a functional block diagram of a workstation to which the microprocessor of the present invention is applied. A plurality of processor CPUs and a memory management unit MM to which the present invention is applied by a system bus
U, main memory, graphic accelerator, input / output device I / O, and 2nd cache memory are connected. And the graphic accelerator and CRT
Is connected, and the input / output device I / O is connected to the network, keyboard, and hard disk. Here, the memory management unit MMU is for converting a hierarchical memory and a real memory, and the graphic accelerator is for reading and executing high-speed drawing of points, lines, fills, characters, etc. by an instruction. The calculation result by the graphic accelerator is written to the VRAM as dot data output, and C
It is output to RT and displayed. The input / output device I / O basically inputs / outputs data from / to the outside of the workstation according to an instruction from the processor CPU of the present invention. However, during DMA transfer, data between the memory and I / O is transferred. Transfer. Further, the input / output device I / O fetches an external command input from the keyboard and communicates with other workstations via the network. Then, the hard disk specifies to the hard disk driver of the hard disk (not shown) generated from the processor of the present invention the amount of extracting the content of the hard disk and the storage location in the main memory. Here, in the processor of the present invention, one primary cache memory can be shared by a plurality of processor elements PE1 to PEn, so that it is possible to switch a part of the multi-thread that was switched by software in the related art by hardware. Therefore, the number of times of memory access can be reduced and high-speed switching can be performed. Also, conventionally, another processor C until the contents are recognized.
Although it was impossible to operate the PU, it is possible to handle it by the internal bus, so that the calculation can be performed in the processor CPU, so that the scheduling can be performed at high speed. Further, storing the execution process at the time of the external interrupt in the management register can speed up the process switching after the interrupt request.

[0022]

In a logic integrated circuit having a large-capacity general-purpose register file, by dividing the general-purpose register file for each process, the process switching time is greatly shortened, and expansion to a multiprocessor is facilitated.
By optimizing the instruction code assigned to the pipeline processing, the processing speed can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a processor to which the present invention is applied.

FIG. 2 is a functional block diagram of a conventional RISC processor.

FIG. 3 is a conceptual diagram of pipeline processing of a general RISC processor.

FIG. 4 illustrates a method for reading and writing execution status flags in a processor of the present invention.

FIG. 5 is a functional block diagram of a processor in which data of a general-purpose register group is stored in a management register according to the second embodiment.

FIG. 6 is a functional block diagram of a multiprocessor including a plurality of arithmetic units and a plurality of program counters according to the third embodiment.

FIG. 7 is a functional block diagram of a processor in which a plurality of program counters are provided for one processor according to the fourth embodiment.

FIG. 8 is a diagram showing instruction contents and pipeline processing of an instruction cache memory of a processor in which a plurality of program counters are provided for one processor of the fourth embodiment.

FIG. 9 is a functional block diagram of a workstation system according to a fifth embodiment of the invention.

[Explanation of symbols]

PC: Program counter, Reg: General-purpose register,
DCR ... Decoding circuit, BLK ... Block, Grp ...
General-purpose register group, PC * ... program counter value, ALU ... arithmetic unit, Grp # ... register group signal, CPU ... processor, grp * ... general-purpose register group data, PE * ..Processor element data, PE ... Processor element, MMU ... Memory management unit, I / O ... Input / output device

Claims (6)

[Claims] 1. A general-purpose register file configured by a general-purpose register group including a plurality of general-purpose registers,
A management register group including a plurality of management registers for storing information on processes assigned to each of the general-purpose registers and information on switching of the processes, and a memory
A logic integrated circuit included in a chip, wherein the management register holds an instruction for performing a read operation and a write operation between the general-purpose register in the general-purpose register file and the memory, and the management register is It has a function of being divided for each process, and the general-purpose register is assigned by the management register for each execution process, and when the execution process is different and the same general-purpose register is designated at the time of instruction input, each execution is executed. The use range of the general-purpose register is limited for each process by being specified in the general-purpose register assigned to the process and referring to the data stored in the management register from the register specification at the time of inputting an instruction. Logic integrated circuit. 2. The logic integrated circuit according to claim 1, wherein information about the process in the execution state and the process in the execution wait state is stored in each of the general-purpose registers in the general-purpose register file. . 3. The logic integrated circuit according to claim 1, wherein the logic integrated circuit has a plurality of processors and a plurality of processes are simultaneously executed by the general-purpose register. 4. The logic integrated circuit comprises a program counter indicating an instruction code of an execution process, a program counter indicating an instruction code of a process other than the execution process in a waiting state, and a circuit for detecting the instruction code. In the normal processing, the program counter of the execution process is used, and the instruction code not executed in the pipeline is detected by the instruction code detection circuit before the instruction is read, and the instruction code of the process in the execution waiting state is detected. A program counter switching circuit for switching to a program counter indicating that the instruction code of another process is inserted instead, and is replaced with an instruction code that can be executed in a pipeline when an instruction is input. The logic integrated circuit according to item 1. 5. A function of switching the process, selecting a management register, holding the value in a program counter, overwriting the management register to switch the execution state flag to the execution waiting state flag, and from the execution waiting state flag. The function to transfer data according to a selection algorithm that selects the next execution process and specifies the general-purpose register group corresponding to that process, and specifies the management register to be executed next and reads the value of the program counter stored therein and the above program This is performed by a process switching circuit having a data restoring function for setting in a counter, and in the above selection algorithm, a management register having information of the next execution process is calculated from the general-purpose register group read by the bit number. Logic integrated circuits Claims paragraph 1, wherein the switching to the same bit during execution of the running state flag flags stored standby state. 6. A system bus allows a plurality of processors,
A memory management unit, a main memory, a graphic accelerator, an input / output device, and a cache memory are connected, and also the graphic accelerator and the CRT, the input / output device, a network, a keyboard, and a hard disk are connected, and the memory management unit is used. Converting the hierarchical memory and the real memory, reading and executing high-speed drawing by an instruction in the graphic accelerator, executing the calculation result in the VRAM as dot data output, and outputting and displaying in the CRT, The input / output device inputs / outputs data from / to the outside in accordance with an instruction from the processor and transfers data between the memory and the input / output device at the time of DMA transfer. Amount of extracting the contents of the hard disk to the hard disk driver generated from the processor in the hard disk, while receiving the command from the outside input from the keyboard and communicating with other system in the network. A data processing system for designating a storage location in the main memory, comprising a general-purpose register file configured by a general-purpose register group including a plurality of general-purpose registers, information on processes assigned to each of the general-purpose registers, and switching of the processes. A logical integrated circuit having a management register group composed of a plurality of management registers for storing information on a memory and a memory in one chip, wherein the management register is provided between the general-purpose register in the general-purpose register file and the memory. Read operation The management register holds information for performing a write operation, and the management register has a function of being divided for each process. The general-purpose register is assigned by the management register for each execution process, and the execution process is different. In the case where the instruction is input, the same general-purpose register is designated to specify the general-purpose register assigned to each execution process, and the data stored in the management register is referenced from the register designation when the instruction is input. A data processing system, wherein the use range of the general-purpose register is limited for each process.