JPS62142786U - - Google Patents
Info
- Publication number
- JPS62142786U JPS62142786U JP3071886U JP3071886U JPS62142786U JP S62142786 U JPS62142786 U JP S62142786U JP 3071886 U JP3071886 U JP 3071886U JP 3071886 U JP3071886 U JP 3071886U JP S62142786 U JPS62142786 U JP S62142786U
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- subcode
- data
- register group
- selector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000605 extraction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
Description
第１図は本考案に係るサブコード抽出回路の一
実施例を示す要部構成図、第２図はシフトレジス
タを説明するための図、第３図はタイムチヤート
、第４図および第５図はコンパクトデイスクのデ
ータパターンを説明するための図である。
１…第１のシフトレジスタ群、２…第２のシフ
トレジスタ群、１―６〜２―１…シフトレジスタ
、３…データバス、４…セレクタ、５…分周器、
６…カウンタ、７…ゲート、８…ＣＰＵ。
Fig. 1 is a main part configuration diagram showing an embodiment of a subcode extraction circuit according to the present invention, Fig. 2 is a diagram for explaining a shift register, Fig. 3 is a time chart, and Figs. 4 and 5. is a diagram for explaining a data pattern of a compact disc. DESCRIPTION OF SYMBOLS 1...First shift register group, 2...Second shift register group, 1-6 to 2-1...Shift register, 3...Data bus, 4...Selector, 5...Frequency divider,
6...Counter, 7...Gate, 8...CPU.
Claims (1)
報を取込み、外部信号によりパラレル出力が可能
に構成された９６ビツト長の第１のシフトレジス
タ群と第２のシフトレジスタ群と、 デイスクからのサブコードＱデータとサブコー
ドクロツクとを、前記第１のシフトレジスタ群か
第２のシフトレジスタ群のいずれか一方に供給す
るように切換えを行うセレクタと、 デイスクからサブコード同期信号が入力される
毎に、前記セレクタの選択を切換える制御および
サブコードクロツクの内サブコードＱデータを出
力する時に発生されるサブクロツクのみを抽出し
て前記セレクタに与える制御を行う制御手段とを
具備し、前記セレクタで２系統のシフトレジスタ
群を交互に選択してサブコードＱデータを取込み
、一方のシフトレジスタ群でサブコードＱデータ
を取込んでいる間に、他方のシフトレジスタ群か
らはデータの読み出しが行えるようにしたことを
特徴とするコンパクトデイスクサブコード抽出回
路。[Claims for Utility Model Registration] A first shift register group and a second shift register group each having a length of 96 bits and configured to take in 96 bits of information after the synchronization bit of the subcode and to enable parallel output using an external signal. and a selector that switches to supply the subcode Q data and subcode clock from the disk to either the first shift register group or the second shift register group; control means for controlling the selection of the selector each time a synchronization signal is input, and controlling for extracting only the sub-clock generated when outputting the sub-code Q data among the sub-code clocks and applying it to the selector; The selector alternately selects the two shift register groups to take in the subcode Q data, and while one shift register group is taking in the subcode Q data, the subcode Q data is taken in from the other shift register group. is a compact disk subcode extraction circuit characterized by being able to read data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3071886U JPS62142786U (en) | 1986-03-04 | 1986-03-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3071886U JPS62142786U (en) | 1986-03-04 | 1986-03-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62142786U true JPS62142786U (en) | 1987-09-09 |
Family
ID=30835785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3071886U Pending JPS62142786U (en) | 1986-03-04 | 1986-03-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62142786U (en) |
-
1986
- 1986-03-04 JP JP3071886U patent/JPS62142786U/ja active Pending
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