JPS62137647A - Memory interface circuit - Google Patents

Abstract

PURPOSE:To facilitate a synchronous processing by reading out the content of memory of write address when the mode setting value from a host processor is 1, subtracting it and writing it in a memory, and sending out an access completion signal when the result became 0. CONSTITUTION:A memory access supporting circuit 11 having a data register 11a, a mode setting circuit 12 and a modifying circuit 13 are provided in a memory interface circuit 10 connected to a host processor 20, data processors 21, 22 and a memory 23. When the mode setting value of the circuit 12 according to a command of the processor 20 is 1, the content of the memory 23 of write address is read out, and write data from the circuit 11 is subtracted. When the circuit 13 detects the result, as 0, it sends out an access completion signal to the circuit 11, and when the mode setting value is 0, the circuit 13 also sends out the access completion signal to the circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory interface circuit, and more particularly to a memory interface circuit that executes read/write operations from a data flow processor to a memory.

[Conventional technology]

Conventionally, there is μPD7281 manufactured by NEC Corporation as a data flow processor. μPD930 manufactured by NEC Corporation is used as a memory interface circuit in the arithmetic processing system using the data flow processor.
There are 5. First, the memory access operation of the μPD9305 will be explained.

The μPD 9305 transfers data and performs arithmetic processing using a data flow method, and input/output data is called a token.

l.-kun is set data consisting of a data section, an identifier indicating the meaning of this data section, and a destination tag indicating the destination of the token.

For example, in the case of a memory write, the data portion is the write data, the write data token has an identifier indicating that the data is to be written, and a destination tag whose destination is the memory interface circuit, and the data portion is the write address.

A write address token containing an identifier indicating that it is a write address and a destination tag indicating that the memory interface circuit is the destination is input to the memory interface circuit in this order.

The memory interface circuit has an internal data register, and when a write data token 7 is input, the write data of the data section is set and held in the data register. Then, when the write address token is entered,
The memory interface circuit outputs the write data read from the data register, the write address of the data portion of the write address token, and a memory write command signal to the memory to instruct a write operation.

The memory executes the write operation according to the above instructions, and when the write operation is completed, returns an access completion signal to the memory interface circuit. The memory interface circuit receives this access end signal and ends the memory write operation.

The μPD9305 further has a function called read modify write. This function changes the identifier of the write address 1--kun of the memory write operation to the identifier of the read modify line I, and instead of the memory write operation described above, reads the data in the memory of the corrupted address. Bitwise AND of the data in the data register.

After performing a logical OR or exclusive OR operation, the result is written into the memory at the write address. With this function, the process of reading the contents of memory, performing arithmetic processing, and then writing can be done in one memory access, making it extremely fast. Also, as an example of this function, if you use an exclusive OR operation to store data such that all the bits and pieces are 1 in the internal data register, you can easily change the memory contents for each bit and so. Be able to invert (0 to 1, 1 to 0).

[Problems to be Solved by the Present Invention] In the lead mochi 49, 41 to functions of the conventional memory interface circuit described above, the operations thereof are limited to logical operations. This is because these are independent calculations for each Bi/So 1 unit, and only simple calculations can be realized because the number of elements in the integrated circuit is limited.

The above-mentioned read-modify-write function performs an arithmetic operation of subtraction on the memory contents, and if there is also a zero detection function for the result of this subtraction, the following synchronization process becomes possible. For example, when performing picture processing with the data flow type arithmetic processing device, it is possible to divide the entire screen into a plurality of regions and execute the same processing in parallel for each region. By the way, when the amount of processing depends on the data value or when it is not divided evenly, the end time of processing for each area may not match, and in order to move on to the next processing, it is necessary to So-called synchronous processing to confirm the completion of processing must not be performed. There are roughly two methods for performing the above-mentioned synchronization processing using a conventional memory interface circuit.

The first method is to obtain a final token indicating the end of processing in all regions by performing a pseudo binary operation between end 1 and -kun, which indicate the end of processing in each region. FIG. 3 is a data flow diagram showing the principle of ill processing. In FIG. 3, e+, ez.

e3, e4 and e5 indicate the end I-kun for each area. Synchronization processing 30, 31, 32 and 33 are pseudo 2
In term operation processing, the final token e6 is generated by synchronizing every two ending tokens.

However, with this method, it is necessary to write the synchronization part in the program, and the disadvantage is that the synchronization process as shown in the example in Figure 3 must be written every time the division method or processing program changes. The second method is to have the host computer perform synchronization processing. The memory interface circuit has a vortex of ports that perform input and output to the host computer.
Therefore, to perform the example shown in FIG. 3 in a second way, the end tokens el, ez.

Each of e3, e4 and e5 is input to the host computer via the memory interface circuit, and the host l-
, the number of end tokens input by the computer is counted to determine that processing has ended in all areas. However, this second method places a heavy burden on the host computer. An object of the present invention is to realize a means for easily detecting the end of all processes by synchronizing the end of each process when processing the following processes in parallel.

[Means for solving problems]

The memory interface circuit of the present invention is connected to a host processor, a plurality of data flow processors connected in a ring, and a memory, and is configured to interface with the memory according to instructions from 1 to -k inputted from the data flow processor. A memory interface circuit that executes a read/write operation to the memory, outputs the write address and write data obtained by the instruction of the input token, instructs the write operation to the memory, and terminates the access in response to this. a memory access support circuit that receives a signal and ends the write operation; a mode setting circuit that sets and holds a mode according to a mode setting instruction input from the host processor and outputs this as a mode setting value; It is connected to the memory access support circuit, the mode setting circuit, and the memory, and when the mode setting value is "1", the content of the memory at the write address is read, and the content of the memory is read from the read memory content. The write data is subtracted, the result of this subtraction is written to the memory at the write address, and when it is detected that the result of this subtraction is "0", a detection signal is output, and the memory access sensor; f? -1- Sends the access end signal to the circuit, and if the mode setting value is "0", writes the write data to the memory at the write address, and sends the access end signal to the memory access support circuit. It is equipped with a modify circuit for sending out data.

5 Examples] Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a professional diagram showing one embodiment of the present invention.

In FIG. 1, one embodiment of the present invention includes a memory access support circuit 11 having an internal data register lla;
A memory interface circuit 10 includes a mode setting circuit 12 and a modifying circuit 13.

The memory interface circuit 10 has signal lines 61 and 62
are connected to the system bus 60 of the host 1 to processor 20 via signal lines 63 and 65, respectively, to the data flow processors 21 and 22, which are connected to each other via signal lines 64; Signal lines 66, 67 and 68
It is connected to the memory 23 via.

The memory access support circuit 11 exchanges various command data and the like with the system bus 60 of the host processor/source 20 via a signal line 61, and sends and receives data from its output port to the data flow processor/source via a signal line 63. Output 1~-kun to 21 and execute the data flow process...121
The data flow from the signal line 64 to the brosé nosa 22
The l.-kun inputted to the data flow controller 22 and output via the signal line 65 is sent to the person's capo-I.
- input by signal lines 51, 52 and 53,
It exchanges signals with the modify circuit 13)
It is configured.

The mode setting circuit 12 receives a mode setting command from the system bus 6 (signal line 62) of the host processor 20, holds it in an internal register, and sets it as a mode setting value via a signal line 54. It is configured to output to the modify circuit 13 and control the operating mode of the modify circuit.

The modify circuit 13 exchanges signals with the memory access support circuit 11 via signal lines 51, 52 and 53, and the mode setting circuit 12 via a signal line 54.
It is controlled by the mode setting value inputted from the signal #! It is configured to perform a read or write operation to the memory 23 via 66, 67 and 68, and to send a detection signal to the host processor 20 via a signal line 70.

Read and write operations for the memory 23 are performed by an l-1 command input to the memory access sabot 1-circuit 11.

A token is data consisting of a data section, an identifier indicating the meaning of the data section, and a destination tag indicating the destination of the token.

In the case of memory writing, there is a data part which is the write data, a write data token with an identifier indicating that it is write data and a destination tag whose destination is the memory access support circuit, a data part which is the write address, and a write address. a write address token having an identifier indicating that the address is a write address token and a destination having a memory access support circuit as the destination;
This order is input to memory access support circuit E+11. Each of the memory access sabots 1 to 11 has a data register lla therein, and when a write data token is input, the write data of the data section is set and held in the data register 1],a. Next, when a write address token is input, the memory access support circuit 11 sends the write data read from the data register 11:L to the signal line 52 to the modify circuit 13, and sends the write address token to the modify circuit 13. A write address of the data section of the memory is outputted to the signal line 51, and a memory write command signal is outputted to the signal line 53, respectively, to instruct the write operation to the memory. The modify circuit 13 executes the write operation to the memory according to the above-mentioned instruction, and when it is completed, sends back an access completion signal to the memory access sabot 1 to circuit 11 via the signal line 53. The memory access support circuit 11 receives this access end signal and ends the memory write operation. In the case of a memory read, a read address token having a data part of the read address, an identifier indicating that it is a read address, and a destination tag indicating the memory access support circuit is used as the memory access support circuit. 11, the memory access support circuit 11 outputs the read address of the data part of the read address token to the signal line 51 and the memory read command signal to the signal line 53 to the modify circuit 13. Instructs read operation from memory. The modify circuit 13 executes the read operation from the memory according to the above-mentioned command, and when this is completed, it sends an access end signal to the memory access support circuit 11 via the signal line 53, and at the same time sends an access end signal to the memory access support circuit 11 via the signal line 53.
The read data read from the memory 23 is sent back via the memory access support circuit 2, and the read data is input to the memory access support circuit 11, thereby completing the read operation.

When the mode setting value input from the mode setting circuit 12 via the signal line 54 is "0", the modify circuit 13 transmits the signal line 5 from the memory access support 1 to the circuit 11.
1. The above-mentioned signals inputted through 52 and 53 are sent directly to the memory 2 through signal lines 66, 67 and 68, respectively.
The signals input from the memory 23 via the signal lines 67 and 68 are output as they are to the memory access sabot 1 to the circuit 11 via the signal lines 52 and 53, respectively. Accordingly, read and write operations for the memory 23 are executed as instructed by the memory access support circuit 11.

When the mode setting value is "1", when a memory read operation is instructed, the mode setting value is "0".
The operation is exactly the same as in the case of , but when a memory write operation is instructed, the memory content modification process is performed.

In the memory content modification/detection process, the memory access support circuit 11 sends a message to the modify circuit 13,
Write data read from data register lla of memory access support circuit 11 (hereinafter “C°
A write address of the data portion of the write address token is applied to a signal line 51, and a memory write command signal is applied to a signal line 53. In response to this, the modify circuit 13 first sends a memory read command signal to the memory 23 via the signal line 68 f: simultaneously to the signal line 5 of n'.
The memory read address (address A
) and read out the contents of address A (hereinafter referred to as "B"). This read °'13'' is the signal line (
57 to the modify circuit 13, and at the same time, an access end signal is inputted to the modify circuit 13 via a signal line 68.

Next, inside the modify circuit 13, from "°B" inputted via the signal line 67 to "°B" inputted via the signal line 51.
Subtraction of C' is performed and the subtraction result (B - C) is obtained. The modification circuit 11 converts this subtraction result (B-C) into “
9 which sends this as a detection signal to the host processor/source 20 via the signal line 71.
Next, the modify circuit 13 sends the memory 23 the following information:
A memory write command signal is outputted via the signal line 68, and at the same time, the address A is given as the write address via the signal line 66, and the subtraction result (B-C) is given as the write data via the signal line 67. writes the subtraction result (3-C) to address A. When this write operation is completed, an access end signal is sent back from the memory 23 to the modify circuit 13 via the signal line 68, and the modify circuit 13 accordingly stops the signal line 53 and sends the returned access end signal to the memory access support. As the circuit 11 receives the data, the memory access support 1/circuit 1
As soon as the memory write operation in 1 is completed, the memory 2
The content modification/detection process of the memory at address A in step 3 also ends.

The host processor 20 receives the detection signal via the signal line 70, generates an interrupt, knows the completion of parallel processing, and can move on to the next processing. In this case, Phos1~Process・
・/S only needs to perform the final processing after receiving an interrupt, so its burden is reduced.

FIG. 2 is a block diagram showing an embodiment of the pond of the present invention.

In another embodiment in FIG. 2, the detection signal is input to the merging circuit 24 via the signal line 70, and the output of the merging circuit 24 is
Upon receiving the detection signal, the one convergence recess d3.24, which is input to the data flow processor 21 via the signal line 71, generates a final token internally and inserts it into the output token to the signal line 71. This final token is manually input to the data flow processors 21 and 22 to start the next process, so that the synchronization process is executed without placing any burden on the host processor 20.

〔Effect of the invention〕

As explained above, the present invention provides a process for synchronizing end tokens that notify the end of multiple parallel processes and determining the completion of all processes by programming the flow for synchronizing ends 1 to -kun. or the host processor
It can be executed by a memory interface circuit equipped with memory content modification/detection processing that detects the subtraction of memory contents and the detection that the result of this subtraction is "0" without burdening l processing, and synchronization. The effect of speeding up and simplifying processing can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention, FIG. 2 is a block diagram showing an embodiment of the invention, and FIG. 3 is a data flow diagram showing the principle of synchronization processing. 10...Memory interface circuit, 11...Memory access support circuit, lla...Data register,
12... Mode setting circuit, 13... Modifying circuit, 20... Host processor, 21.22... Data flow processor, 23... Memory, 51-54
...Signal line, 60...System hash, 61-71.
··Signal line. Figure 1, Section 2, Figure 1,33 Procedural Amendment (Voluntary)

Claims (1)

[Claims] In a memory interface circuit connected to a host processor, a plurality of data flow processors connected in a ring shape, and a memory, the memory interface circuit executes a read/write operation to the memory according to a token instruction input from the data flow processor. , a memory access support circuit that outputs a write address and write data obtained by the input token instruction to instruct a write operation to the memory, and receives an access end signal as a response thereto to terminate the write operation; , a mode setting circuit that sets and holds a mode according to a mode setting instruction input from the host processor, and outputs the mode setting value as a mode setting value; and a memory access support circuit connected to the mode setting circuit and the memory; When the mode setting value is "1", the content of the memory at the write address is read, the write data is subtracted from the read memory content, and the subtraction result is written to the memory at the write address. , when detecting that the subtraction result is "0", outputs a detection signal and sends the access end signal to the memory access support circuit, and when the mode setting value is "0", the write A memory interface circuit comprising: a modify circuit that writes the write data into a memory at an address and sends the access end signal to the memory access support circuit.