JPH04190443A - Data transfer device - Google Patents

Abstract

PURPOSE:To increase the utilization efficiency of a system bus and to shorten the processing time by putting data on a data transfer request device together into data close to the bit width of a system bus and passing the data through the system bus. CONSTITUTION:A packing/unpacking part 9 is provided halfway in a transfer path and when data are transferred from the data transfer request DMA device 8 to a data transfer area 1, several data read out of the DMA device 8 are put together into data whose bit width is equal or close to the bit width of the system bus 2. When data are transferred from the transfer area 1 to the DMA device 8, the data are transferred to the packing/unpacking part 9 in units of the bit width of the system bus 2. Thus, the utilization efficiency of the system bus is improved and the occupation time of the system bus is shortened to improve the efficiency of processing.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a data transfer device that efficiently utilizes a system bus and can transfer data in a short time even if the bit width of data is smaller than the bit width of a system bus used for transfer.

[Conventional technology]

FIG. 2 shows a conventional data transfer device. In Fig. 2, 1 is a data transfer area, 2 is a system bus, 3 is a system interface, 4 is a device, 5 is a data transfer control unit, 6 is an address counter, 7 is a device interface, and 8 is a data transfer. Request device (hereinafter referred to as "DMA device") DMA-Dire
ct Memory AccessS). In such devices, the port width of the DMA device 8, and therefore the bit width of the data therefrom, is often smaller than the bit width of the system bus 2. As an example of such a case, the data bit width of the DMA device 8 is 8 bits, and the node width of the system bus 2 is 32 bits. Here is an example of the case where it is ↓. Data transfer is from DMA device 8 to data transfer area 1
or vice versa, from data transfer area 1 to DMA device 8. When transferring from the DMA device 8 to the data transfer area 1, the 8-bit wide data read from the DMA device 8 is transferred to the data transfer area 4. It passes through the system interface 3, enters the 32-bit wide 7-stem hash 2, and is written to the data transfer area 1. Address counter 6 specifies the address to be written. The reading from the DMA device 8 and the designation of the transfer direction of the device 4 are performed by a signal from the device interface 7, and the timing etc. of the transfer is controlled by the data transfer control section 5. . Transfer from data transfer area 1 to DMA device 8 is performed in the same manner, although the direction is opposite to that described above.

[Problem to be solved by the invention]

(Problems) However, the conventional data transfer device described above has the following problems. The first problem is that the system bus 2 is used inefficiently. The second problem is that the time that Nostem No. 2 is occupied is long, which delays other processing. (Explanation of the problem) As in the above example, if the system bus 2 is 32 bits and the data is 8 bits, when the data card passes through the system bus 2, only 4% of the data transfer capacity of the system bus 2 is used. This means that only one of the following methods is used, which is extremely inefficient. Furthermore, due to poor utilization efficiency, the system bus 2 is occupied for a long time considering the amount of data. For example, if the total amount of data to be transferred is 64 bits, if the data is transferred using the full transfer capacity (32-bit width) of No. 2, the transfer will be completed in two transfer cycles. , 8 bit width requires 8 transfer cycles. Since the system bus 2 is occupied during the transfer, other processing cannot be performed. Therefore,
This will delay other processing. An object of the present invention is to solve the above-mentioned problems.

[Means to solve the problem]

In order to solve the above problems, the present invention provides data transfer SJ
In a data transfer device that transfers data via the system bus between the f area and a data transfer requesting device having a bit width smaller than the bit width of the system bus, when transferring data from the data transfer requesting device to the data transfer area. The data transfer request device combines several pieces of data into data with a bit width that is the same as the bit width of the system bus, or a multiple of the bit width of the data and is closest to the bit width of the system bus, and vice versa. When transferring data from the transfer area to the data transfer requesting device, a pack-unpacking section is provided that divides the data into bit widths of the data transfer requesting device.

[For production]

When data is transferred between a DMA device and a data transfer area via a system bus, several pieces of data in the DMA device are grouped together and the bit width is the same as the bit width of the system bus, or the bit width of the data is and the system bus. data with a bit width closest to the bit width of the target width, and jug the system bus. This makes it possible to improve the system bus usage efficiency. Furthermore, since the time that the system bus is occupied is shorter than before, it is possible to make other processing wait shorter than before.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a data transfer device according to an embodiment of the present invention. The symbols correspond to those in FIG. 2, 4-1 is a device data bus buffer, 4-2 is a device access bus buffer, and 9 is a pack/unpack unit (Pack/Unpack unit).
10 is a register housing, and 11 is a register. The device data bus buffer 4-1 has the functions of the conventional device data bus buffer 4.
The device access path sofa 4-2 has an independent function of passing data, and the device access path sofa 4-2 has an independent function of passing access signals. Although these do not necessarily need to be independent, in the present invention, the pack-unpack unit 9 is provided on the data path, and control related to this is also added, making the control on the data path complicated. Therefore, in order to simplify control as much as possible, in this example, they are made independent. The operations of the parts designated by the same reference numerals as in the conventional example are substantially the same as in the conventional example, so a description thereof will be omitted, and only the different parts will be described below. The puncture unpacking section 9 is provided in the middle of the data transfer path, and when transferring data from the DMA device 8 to the data transfer area 1, it packs several pieces of data read from the DMA device 8. ), the bit width is the same as the bit width of the system bus 2, or a bit width that is a multiple of the bit width of the data and is closest to the bit width of the system bus 2. If the data of the DMA device 8 is 8 bits and the bit width of the system bus 2 is 32 bits, then the four pieces of data are combined into 32 bits of data. The dotted line dividing the register 11 into four units in FIG. 1 indicates that the register 11 is configured to accept four pieces of 8-bit data. Note that the designation of the transfer direction when data passes through the device data bus buffer 4-1 is performed by instructions from the device interface 7. The data grouped into 32 bits/7 bits is transferred from system interface 3 to system bus 2 to data transfer area l, but at this time, the 32 bit wide system bus 2
Since 100% of the transfer capacity of the system bus 2 is utilized, the system bus 2 is used efficiently. In addition, data that required four transfer cycles in the conventional example (8 bits 2 is occupied, and the time that other processes are made to wait is shorter than before. Conversely, when transferring data from data transfer area 1 to DMA device 8, data is transferred in units of bit width of 7 stem nodes 2, that is, 32 bits wide according to the upper part, and transferred to system bus 2.
．． It is transferred to the pack-unpack section 9 via the system interface 3. Therefore, in this case as well, data is sent while making full use of the transfer capacity of the system bus 2. The data sent to the pack unback section 9 is DMA
Divided into device 8 bit width data (Unpac
k), stored in the register 11, and sequentially sent to the DMA device 8. At that time, the device interface 7 specifies the transfer direction in the device data bus buffer 4-1.

【Effect of the invention】

As described above, in the data transfer device of the present invention, the DMA
When transferring from the device to the data transfer area, DMA
Combine several pieces of data read from the device into data with the same bit width as the pinot width of the system bus, or a multiple of the bit width of the data and the closest bit width to the bit width of the system bus, and pass it through the system bus. In addition, when transferring in the opposite direction, after passing through the system bus, the data is divided into bit widths of the DMA device and sent to the DMA device. Therefore, the system bus usage efficiency is improved. Furthermore, since the time that the system bus is occupied is shorter than before, the time that other processing is made to wait is shorter than before.

[Brief explanation of drawings]

FIG. 1: Data transfer device according to an embodiment of the present invention FIG. 2: In the diagram of a conventional data transfer device, 1 is a data transfer area, 2 is a system bus,
3 is a system interface, 4 is a high speed bus buffer, 4-1 is a device data hub, 4-2 is a device access hub, 5 is a data transfer control unit, 6 is an address counter, 7 is a device interface, 8 is a DMA device, 9 is a pack unback unit,
10 is a register buffer, and II is a register. Patent Applicant Fuji Xerox Co., Ltd. Representative Patent Attorney Tomio Honjo No. 1rlA Figure 2

Claims (1)

[Claims] In a data transfer device that transfers data via a system bus between a data transfer area and a data transfer requesting device having a bit width smaller than the bit width of the system bus, when transferring data from the data transfer requesting device to the data transfer area. To do this, combine several pieces of data from the data transfer requesting device into data with a bit width that is the same as the bit width of the system bus, or a bit width that is a multiple of the bit width of the data and is closest to the bit width of the system bus, and vice versa. A data transfer device comprising a pack-unpack unit that divides the data into bit widths of the data transfer requesting device when transferring data from the data transfer area to the data transfer requesting device.