JP2599805B2 - DMA controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller, and more particularly to a reduction in the circuit size and operation time of a decoder in a control circuit thereof.

[Conventional technology]

One of the transfer methods of the DMA controller is a dual address mode. In this method, a read operation, that is, a read cycle in which an address of a transfer source (hereinafter, referred to as a source) device is output and data is transferred from the source device to a data holding register provided in a DMA controller or lower (referred to as a temporary register). And a next write operation, that is, a write cycle in which the address of a transfer destination (referred to as a destination) device is output and data is transferred from the temporary register to the destination device as one transfer cycle, and the source device is a destination device. Transfer data to

The DMA transfer on the 32-bit bus will be described with reference to FIG.

A case where four bytes are transferred in one transfer cycle with a source address value of S + 1 and a destination address value of D + 1 will be described. S and D are multiples of 4.
Here, since the source address is S + 1, all four bytes cannot be read at one time. Therefore, the read cycle is 2
It is performed by bus access twice. First, 3 bytes are read, and 2 bytes of 1 byte are read twice to read 4 bytes. Similarly, at the time of write access, since the destination address is D + 1, the first 3-byte write operation and the second 1-byte write operation are performed.

The transfer cycle is started when the transfer request signal line 205 is asserted.

When a transfer request is input to the state generation circuit 201 together with the contents of the operation definition register 202 and the output value of the temporary counter 203, the state generation circuit 201 enters a read state and the R / W signal line 219
To output the read status and the address control line.
A request to output the source address S + 1 and a request to count up the source address for generating the second source address are output to the address control unit 200 through 207. Since the first read is 3 bytes, the count-up value here is 3. At this time, a count-up request is also issued to the temporary counter 203 via the temporary counter control line 208. The decoder 204 captures the output of the operation definition register 202, the read state of the state generation circuit 201, and the output value 0 of the temporary counter 203 at the start of the transfer, decodes that the first transfer is 3 bytes, and decodes the address.
A count amplifier value 3 for the temporary counter 203 and 200 is output as a control signal.

The address control unit 200 includes a state generation circuit 201 and a decoder 204.
, The source address is output to the address bus 212 and the counter operation is started. The value of the source address after the count operation is S + 4.
Similarly, the temporary counter 203 starts counting the count value in response to the input of the control signal from the state generating circuit 201 and the decoder 204. The output value of the temporary counter after the count operation is 3.

When the first transfer is completed, the state generation circuit 201 receives the input of the transfer request signal 205, the contents of the operation definition register 202,
The value of the temporary counter 203 is fetched again, and the next state is determined. In this case, since the value of the temporary counter 203 has not reached 4, the next state is still read, and the second read operation is started. Therefore, the state generating circuit 201 issues a request for outputting the source address S + 4 and a request for counting up the source address for generating the source address to be used in the next transfer cycle to the address control unit 200 as in the first read operation. At this time, a count-up request is also issued to the temporary counter 203.

The decoder 204 captures the operation definition register 202 and the output value 3 of the temporary counter 203, decodes that the second transfer is 1 byte, and outputs a count value 1 to the address control unit 200 and the temporary counter 203 as a control signal. I do. The address control unit 200 starts outputting the source address S + 4 to the address bus and starts the counter operation in response to the input of the control signal from the state generating circuit 201 and the decoder 204. The source address value after the count operation is S
+5. The temporary counter is a state generator
The count operation of the temporary counter 203 is started in response to the control signal input from the decoder 201 and the decoder 204. The count value after the count operation is 4.

When the second transfer is completed, the state generation circuit 201 captures the transfer request signal 205, the contents of the operation definition register 202, and the value of the temporary counter 203, and determines the next state. Since the temporary count value is 4 this time, the next state is the write state.

In the write state, the state generating circuit 201 issues a request for outputting the destination address D + 1 and a request for counting up the destination address for generating the destination address used in the second transfer to the address control unit 200. At this time, the temporary counter 20
A countdown request is issued to 3. The decoder 204 captures the output of the operation definition register 202, the write state of the state generation circuit 201, and the output value 4 of the temporary counter 203, decodes that the first write transfer is 3 bytes, and decodes the address control unit 200 and Temporary counter 203
Is output as a control signal.

The address control unit 200 starts outputting the destination address to the address bus and starts the counting operation in response to the input of the control signal.
Generate +4. At this time, the temporary counter 203 also performs a counting operation in response to the input of the control signal, and the temporary count value becomes 1. When the first transfer is completed, the state generation circuit 201 takes in the input, starts the second write operation because the temporary count value is 1, and sends a destination address output and a count-up request to the address control unit 200. And outputs a countdown request to the temporary counter 203.

Since the temporary count value is 1, the decoder 204 decodes that the second write is 1 byte, and outputs the count value 1 as a control signal. Address control unit 200
Performs the output of the destination address and count-up as in the first time, the temporary counter 203 also counts down, and the temporary count value becomes zero. When the second write operation is completed, the state generation circuit 20
Since 1 indicates that the temporary count value is 0, it is determined that the transfer cycle has ended, and the idle state is set until the next transfer request is asserted.

The above is the outline of the state control and address control of the 32-bit DMA controller.

[Problems to be solved by the invention]

In addition to the above transfer example, the 32-bit DMA controller operates in various sizes of data to be transferred from 1 byte to 8 bytes, and also has an address counting operation in upper direction, lower direction, fixed, etc., and combining them And the transfer will be a great variety. When the transfer operation becomes complicated, the transfer control signal pattern decoded by the decoder increases. As the number of input patterns and transfer patterns increases, they are decoded and the area of a decoder that generates control signals increases. Further, when the size of the decoder is increased, it takes a long time for decoding, and there is a problem that the operation speed is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and the same decoding process can be performed without performing separate decoding during a read operation and a write operation, thereby reducing the scale of the decoder. The goal is to get a DMA controller that can do it.

[Means for solving the problem]

The DMA controller according to the present invention includes a control circuit that controls a DMA transfer operation, an access detection unit that detects the number of bytes of access data in a read or write access operation, and an operation set value that defines each access operation. Storage means, state setting means for setting the state of the next access operation based on the current state of the access operation and the input signal, and read operation and write operation of the operation set value based on the set state of the access operation And a decoding means for decoding the select output and the access detection output and outputting a control signal.

[Action]

In the present invention, the number of bytes of the access data of the read or write access operation is detected, and an operation setting value defining the read or write operation is selected and output by the selection means, and the byte number and the select output are decoded. With this arrangement, the input to be decoded and the output to be decoded become the same at the time of reading and at the time of writing, that is, the signal processing pattern is halved, and the circuit scale of the decoder can be reduced.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a control circuit of a DMA controller according to one embodiment of the present invention. In the figure, reference numeral 101 denotes a state generating circuit (state setting means) for generating a state of a DMA operation and a control signal.
The output signal line 107 of the operation definition register 102 and the count value 117 of the temporary counter 103 are input to the address control unit 10.
The control signal for 0 is sent to the address control line 111, and the control signal for the temporary counter 103 is sent to the temporary counter control line 108.
Then, the control signal of the selector 105 is output to the R / W signal line 109.

102 is an operation definition register (storage means) for defining an operation
The operation definition register 102 has a source field for specifying a read operation, a destination field for specifying a write operation, and an operation field for specifying a general operation.

Reference numeral 103 denotes a temporary counter (access detection means) for counting the number of data held in the temporary register (data holding register).
The information on the number of transfers in the operation field 2 is fetched from the output 107, the temporary counter control line 108 output from the state generation circuit 101, and the control signal 112 from the decoder 104.
And outputs a counter value to a counter output line 117, and selectively outputs a counter output value and an inverted value from the output signal line 110 according to the state of the R / W signal line 109.

Reference numeral 104 denotes a decoder (decoding means) for generating a control signal for the address control unit 100 and the temporary counter 103, and a control signal for the address control line 100 from the address control line 113 and a control signal for the temporary counter 103 for the temporary counter control signal line. Output from 112.

Reference numeral 115 denotes a selector (selecting means) for switching one of two signals from the operation definition register 102 to the decoder 104, and a read operation definition portion of the operation definition register 102, that is, a source field and a write operation definition portion, Select the destination field according to the R / W signal line 109 output from the state generation circuit 101,
The contents of the register in the selected field are input to the decoder 104. An address control unit 100 generates and outputs an address to be output to the address bus 116 based on control signals from the state generation circuit 101 and the decoder 104. Address control unit 10
There are two addresses generated at 0, a source address used in a read operation and a destination address used in a write operation.

Hereinafter, in the operation of the present embodiment, the source and destination addresses are S + 1 and 4 respectively in the transfer of 4 bytes.
The case of D + 1 (S and D are multiples of 4), that is, the case where the source and destination both transfer the first 3 bytes and the second 1 byte will be described as an example.

The transfer is started when the transfer request signal line 106 is asserted.

When a transfer request is input to the state generation circuit 101 together with the contents of the operation definition register 102 and the value of the temporary counter 103, the state generation circuit 101 enters a read state, and the address control line 1
A request to output the source address S + 1 and a request to count up the source address for generating the second source address are output to the address control unit 100 by 11. Since the first read is 3 bytes, the count-up value here is 3. At this time, a request for a count operation is issued to the temporary counter 103 via the temporary counter control line 108, and a read state is output from the R / W signal line 109 to the selector 105.

Since the R / W signal line 109 is in the read state, the selector 105 outputs the source field of the operation definition register 102 to the decoder 104. Also, the decoder 104 captures the source field of the operation definition register 102 from the selector output line 115, the operation field from the operation definition register output signal line 107, and the output value 0 of the temporary counter 103 from the output signal line 110 at the start of the transfer. It decodes that the first transfer is 3 bytes, and the address control unit 10
It outputs 0 and the count value 3 for the temporary counter 103 as a control signal.

The address control unit 100 includes a state generation circuit 101 and a decoder 10.
By input via control signal lines 111 and 113 from 4,
The output of the source address to the address bus 116 and the counter operation are started. The value of the source address after the count operation is S + 4.

Similarly, the temporary counter 103 starts counting the temporary count value in response to the input of the control signal from the state generating circuit 101 and the decoder 104. The count value of the temporary count value output signal line 117 after the count operation is 3
And the output of the output signal line 110 (the number of bytes of the access data) is also 3. When the first transfer is completed, the state generation circuit 101 takes in the input of the transfer request signal line 106, the contents of the operation definition register 102, and the value of the temporary counter 103 again, and determines the next state. In this case, since the value of the temporary counter 103 has not reached 4, the next state is still read, and the second read operation is started. Accordingly, the state generating circuit 101 issues a request for outputting the source address S + 4 and a request for counting up the source address for generating a source address to be used in the next transfer cycle to the address control unit 100, as in the first read operation. At this time, a count-up request is also issued to the temporary counter 103. Since the state is lead, R / W signal line 109
Still shows the read state, and the selector also outputs the source field of the operation definition register 102 to the decoder 104.

Then, the decoder 104 takes in the contents of the operation definition register 102 and the output value 3 of the temporary count 103, decodes that the second transfer is 1 byte, and controls the count value 1 for the address control unit 100 and the temporary counter 103. Output as a signal. The address control unit 100 starts outputting the source address S + 4 to the address bus and starts the counter operation in response to the input of the control signal from the state generating circuit 101 and the decoder 104. The source address value after the count operation is S + 5. At this time, temporary counter 103 starts counting a temporary count value in response to input of a control signal from state generating circuit 101 and decoder 104. Temporary count value output line after count operation
The value of 117 is four.

When the second transfer is completed, the state generation circuit 101 takes in the transfer request signal line 106, the contents of the operation definition register 102, and the count value of the temporary counter, and determines the next state. Since the temporary count value is 4 this time, the next state is the write state.

In the write state, the state generating circuit 101 issues a request for outputting the destination address D + 1 and a count-up request for the destination address for generating the destination address used in the second transfer to the address control unit 100. At this time, the temporary counter 103
, A countdown request is issued from the control line 108, and a write state is output from the R / W signal line 109 to the selector 115. The selector 105 outputs the destination field of the operation definition register 102 to the decoder 104. R / W signal line 109
The temporary counter 103 that has detected that the writing operation has entered the write state outputs an inverted output (the number of bytes of access data) obtained by subtracting the count value from the number of bytes transferred in the transfer cycle to the output signal line 110. In this case, the number of transfer bytes is 4, and the count value is 4, so the inverted output is 0. The decoder 104 takes in the operation definition register 102 and the value 0 of the output signal line 110 of the temporary counter 103, decodes that the first write transfer is 3 bytes, and counts the count value 3 for the address control unit 100 and the temporary counter 103. Is output as a control signal.

The address control unit 100 starts outputting the destination address to the address bus 116 and starts the counter operation in response to the input of the control signal, and generates the second destination address D + 4. The temporary counter 103 also performs a counting operation in response to the input of the control signal, and the value of the temporary count value output line 117 becomes 1. Also, since the data is in the write state, the value of the output signal line 110 is changed from the transfer byte number 4 to the count value 1
Is subtracted by 3. When the first transfer is completed, the state generation circuit 101 takes in the input, starts the second write operation because the temporary count value is 3, and sends a destination address output and a count-up request to the address control unit 100. And outputs a countdown request to the temporary counter 103. Since the value of the output signal line 110 of the temporary counter 103 is 3, the decoder 104 decodes that the second write is 1 byte, and outputs a count value 1 as a control signal. The address control unit 100 outputs and counts up the destination address as in the first time, the temporary counter 103 also counts down, and both the temporary count value and the output value are 0.
Becomes When the second write operation is completed, the state generation circuit 101 determines that the transfer cycle is completed because the output value of the temporary counter 103 is 0, and enters the idle state until the next transfer request is asserted.

As can be understood from the above description, the output value from the temporary counter 103, which is the input to the decoder 104, is the same in both the read and write states.
Input is switched by the selector 105, so the decoder 104
Is indistinguishable from. In other words, since the decoder can output the same decoded output with respect to the input at the time of reading and at the time of writing, there is no need to distinguish between the reading state and the writing state.
The size of the decoder is reduced by half.

As described above, in the present embodiment, the temporary counter 103
When reading, the same value as the count value is output to the decoder 104, and when writing, the inverted value obtained by subtracting the count value from the number of transfers is output to the decoder 104, so that the output of the temporary counter input to the decoder 104 is It always indicates the number of bytes transferred regardless of the time of reading or writing. Further, a selector 105 is provided at a stage preceding the decoder 104, and a read operation definition portion (source field) and a write operation definition portion (destination field) of the operation definition register are switched depending on the state and input to the decoder 104. It does not matter whether the decoder 104 is reading or writing,
The input to be decoded and the output to be decoded can be made the same at the time of reading and at the time of writing, so that the decoder can be reduced in size and the operation time can be reduced.

〔The invention's effect〕

As described above, according to the DMA controller of the present invention, the number of bytes of the access data of the read or write access operation is detected, and the operation setting value that defines the read or write operation is selected and output by the selection unit, and is output. Since the number of bytes and the select output are decoded, the input to be decoded and the output to the same at the time of reading and at the time of writing become the same, that is, the signal pattern to be decoded is halved. There is an effect that the scale can be reduced and the time for the decoding operation can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a control circuit of a DMA controller according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the control circuit, and FIG. FIG. 4 is a block diagram showing the configuration of the circuit, and FIG. 4 is a waveform diagram for explaining the operation of the conventional circuit. 100 is an address control circuit, 101 is a state generating circuit (state setting means), 102 is an operation definition register (storage means), 103 is a temporary counter (access detecting means), 104 is a decoder (decoding means), and 105 is a selector (select). means)
It is. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A read access operation of data from a transfer source device to a register having a data holding register,
In a DMA controller that performs a DMA transfer operation including a write access operation of data from the register to a transfer destination device, a control circuit that controls the DMA transfer operation includes an access that detects the number of bytes of access data in each access operation. Detecting means; storage means for holding operation set values defining the above-mentioned access operations; state setting means for setting the next access operation state based on the current access operation state and an input signal; Selecting means for selecting and outputting the operation set value between the read operation and the write operation based on the state of the access operation, and decoding means for decoding the select output and the access detection output and outputting a control signal. A DMA controller characterized by having a circuit configuration including: