JPS62136060A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62136060A
JPS62136060A JP27730285A JP27730285A JPS62136060A JP S62136060 A JPS62136060 A JP S62136060A JP 27730285 A JP27730285 A JP 27730285A JP 27730285 A JP27730285 A JP 27730285A JP S62136060 A JPS62136060 A JP S62136060A
Authority
JP
Japan
Prior art keywords
external connection
leads
bent
mounting
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27730285A
Other languages
Japanese (ja)
Inventor
Tatsuya Hirai
達也 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP27730285A priority Critical patent/JPS62136060A/en
Publication of JPS62136060A publication Critical patent/JPS62136060A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Abstract

PURPOSE:To facilitate connecting external connection leads to the mounting surface of a printed circuit board or the like without providing insertion holes or jigs on the mounting surface and improve a mounting integration density by a method wherein tip parts of the respective adjoining leads for external connection are bent in such a manner that the directions of the bent parts are opposite to each other and the bent arts exist on an identical plane. CONSTITUTION:The tip pars 2a of external connection leads 2 are bent in such a manner that the lower surfaces of the tip parts of the mutually adjoining leads 2 exist on an identical plane and the directions of the bending of the mutually adjoining leads 2 are opposite to each other. With this constitution, a zigzag line package 1 can be mounted on a printed circuit board or the like without providing mounting holes or sockets so that the volume required for mounting can be reduced, workability can be improved and lead processing cost can also be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置に係り、特にその外部接続用リー
ドの形状に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the shape of an external connection lead thereof.

〔従来の技術〕[Conventional technology]

第３図は従来のジグザグインラインパッケージ型の半導
体装置を示す斜視図であシ第４図はその側面図である。FIG. 3 is a perspective view showing a conventional zigzag in-line package type semiconductor device, and FIG. 4 is a side view thereof.

（１）はパッケージ本体、（２）はパッケージ本体から
このパッケージ本体主面に並行に導出された外部接続用
リードであり、全体として千鳥状をなすいわゆるジグザ
グインライン構成のものである。(1) is a package body, and (2) is an external connection lead led out from the package body in parallel to the main surface of the package body, and has a so-called zigzag in-line configuration that has a staggered shape as a whole.

外部接続用リード（２）はそのリード先端に向かうにつ
れて、テーパ状に細くなっている。The external connection lead (2) tapers toward its tip.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のジグザグインラインパッケージ形の半導体装置は
以上のように構成されているので、プリント基板等の取
付面への接続は、外部接続用リードを前記取付部の挿入
穴に挿入するか、またはソケット等の取付治具に挿入し
なければならない。従って前記プリント基板等の取付面
に挿入穴を設けるか、または取付治具を設けることが必
要であった。また、取付形状が縦型となるため、半導体
装置の高さがデュアルインライン形等のフラット形パッ
ケージに比べて高くなるという欠点があった。Since the conventional zigzag in-line package type semiconductor device is configured as described above, connection to the mounting surface of a printed circuit board, etc. can be made by inserting an external connection lead into the insertion hole of the mounting section, or by using a socket, etc. must be inserted into the mounting jig. Therefore, it is necessary to provide an insertion hole in the mounting surface of the printed circuit board or the like, or to provide a mounting jig. Further, since the mounting shape is vertical, there is a drawback that the height of the semiconductor device is higher than that of a flat package such as a dual in-line type.

この発明は上記のような従来の欠点を解消するためにな
されたもので、プリント基板等の取付面に半導体装置の
外部接続用リードを接続する挿入穴またに治具を設ける
ことなく、前記取付面に前記外部接続用リードを接続で
きるとともＶＣ、実装集積密度の向上を計ることを目的
とする。This invention has been made in order to eliminate the above-mentioned drawbacks of the conventional art, and it is possible to mount the mounting surface without providing a jig or an insertion hole for connecting external connection leads of a semiconductor device to the mounting surface of a printed circuit board or the like. The purpose is to be able to connect the external connection leads to the surface and to improve the VC and packaging integration density.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、外部接続用の隣接した各
リードを、そのリード先端部が互いに逆方向全量き、各
リード先端部下面が、同一平面となるように折曲げたも
のである。In the semiconductor device according to the present invention, adjacent leads for external connection are bent so that the leading ends of the leads are completely turned in opposite directions, and the lower surfaces of the leading ends of the leads are on the same plane.

〔作用〕[Effect]

この発明における半導体装置は外部接続用の各リード先
端部が同一平面となるように折曲げられているため、前
記半導体装置の取付面には挿入用の取付穴環ｆ、設ける
ことなく、大袋状態で収付けられる。Since the semiconductor device according to the present invention is bent so that the tips of each lead for external connection are on the same plane, there is no mounting hole ring f for insertion on the mounting surface of the semiconductor device, and the semiconductor device is in a large bag state. It can be stored in.

〔実施例〕〔Example〕

第１図はこの発明の一実施例を示す斜視図であり、第２
図はその側面図である。図中、第３図、第４図と同一符
号は同一１だは相当部分？表わすものであり説明は省略
する。FIG. 1 is a perspective view showing one embodiment of the present invention, and FIG.
The figure is a side view thereof. In the figure, the same numbers as in Figures 3 and 4 are the same 1, or are they corresponding parts? This is a representation, and the explanation will be omitted.

（２ａ）は外部接続用リードの先端部であって、隣接す
るリードの先端部下面が互いに同一平面となるとともは
、前記外部接続用リードの先端部（２ａ）が逆方向に折
曲げられる。(2a) is the tip of the external connection lead, and when the lower surfaces of the tips of adjacent leads are on the same plane, the tip (2a) of the external connection lead is bent in the opposite direction.

このような構造にすることにより、ジグザグインライン
型パッケージ？プリント基板等に取付穴またはソケット
等を設けることなく、１■付けることができ、実装に用
する容積を少なくし、作業性を高め、リード加工費を低
減できる。Is it possible to create a zigzag inline package by creating a structure like this? It can be mounted on a printed circuit board or the like without providing a mounting hole or socket, reducing the volume used for mounting, improving workability, and reducing lead processing costs.

〔発明の効果〕〔Effect of the invention〕

以上のようは、この発明によれば、斤いに：隣接する外
部接続用リードを、その外部接続用リードの先端部が雇
いに逆方向を向き、かつ各リード先端部下面が同一平面
となるように折り曲げたので、プリント基板等の取付面
上に取付穴を設けることなく、直接半導体装置を実装す
ることができ、かつ、半導体装置取付高さ？小さくする
ことによって集積密度を向上できる利点がある。As described above, according to the present invention, the tips of the adjacent external connection leads are oriented in opposite directions, and the lower surfaces of the tips of each lead are on the same plane. Since it is bent like this, it is possible to directly mount the semiconductor device without creating a mounting hole on the mounting surface of the printed circuit board, etc., and the mounting height of the semiconductor device can be reduced. There is an advantage that the integration density can be improved by making the size smaller.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図はこの発明の一実施例を示す釘Ｆ視図と
側面図、第３図、第４図は従来のジグザグインライン型
の半導体装置を示す斜視図と側面図である。 図においてＨｌはパッケージ本体、（２１は外部接続用
リード、（２１Ｌ）は外部接続用リード先端部である。 図中、同一符号は同一または相当部分を示す。1 and 2 are a perspective view and a side view of a nail F showing an embodiment of the present invention, and FIGS. 3 and 4 are a perspective view and a side view of a conventional zigzag in-line type semiconductor device. In the figure, Hl is the package body, (21 is a lead for external connection, and (21L) is the tip of the lead for external connection. In the figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] （１）パッケージ本体の下面から、複数の外部接続用の
リードが前記パッケージ本体の主面に並行に所定の間隔
で導出され、かつ、千鳥形状をなしているジグザグイン
ラインパッケージ型の半導体装置において、隣接した外
部接続用の各リードの先端部は、互いに逆方向に折曲げ
られ、かつ、前記各リードの先端部の下面が同一平面と
なるような取付部を備えたことを特徴とする半導体装置
。(1) A zigzag in-line package type semiconductor device in which a plurality of external connection leads are led out from the bottom surface of the package body at predetermined intervals in parallel to the main surface of the package body, and have a staggered shape, A semiconductor device characterized in that the tips of adjacent leads for external connection are bent in opposite directions, and the semiconductor device is provided with a mounting portion such that the lower surfaces of the tips of the leads are on the same plane. .
JP27730285A 1985-12-09 1985-12-09 Semiconductor device Pending JPS62136060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27730285A JPS62136060A (en) 1985-12-09 1985-12-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27730285A JPS62136060A (en) 1985-12-09 1985-12-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62136060A true JPS62136060A (en) 1987-06-19

Family

ID=17581641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27730285A Pending JPS62136060A (en) 1985-12-09 1985-12-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62136060A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01187960A (en) * 1988-01-22 1989-07-27 Mitsubishi Electric Corp Semiconductor device
US5574310A (en) * 1991-05-17 1996-11-12 Fujitsu Limited Semiconductor package for surface mounting with reinforcing members on support legs
US5831332A (en) * 1991-05-17 1998-11-03 Fujitsu Limited Semiconductor package for surface mounting

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS622638A (en) * 1985-06-28 1987-01-08 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS622638A (en) * 1985-06-28 1987-01-08 Toshiba Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01187960A (en) * 1988-01-22 1989-07-27 Mitsubishi Electric Corp Semiconductor device
US5574310A (en) * 1991-05-17 1996-11-12 Fujitsu Limited Semiconductor package for surface mounting with reinforcing members on support legs
US5831332A (en) * 1991-05-17 1998-11-03 Fujitsu Limited Semiconductor package for surface mounting
US5861669A (en) * 1991-05-17 1999-01-19 Fujitsu Limited Semiconductor package for surface mounting

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