JPS62134950A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS62134950A
JPS62134950A JP60275420A JP27542085A JPS62134950A JP S62134950 A JPS62134950 A JP S62134950A JP 60275420 A JP60275420 A JP 60275420A JP 27542085 A JP27542085 A JP 27542085A JP S62134950 A JPS62134950 A JP S62134950A
Authority
JP
Japan
Prior art keywords
lead
integrated circuit
leads
island
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60275420A
Other languages
Japanese (ja)
Inventor
Yoshinori Sato
義則 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60275420A priority Critical patent/JPS62134950A/en
Publication of JPS62134950A publication Critical patent/JPS62134950A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To mount bonding pads of the same signals at two or more positions on an integrated circuit chip and to prevent an operating range of a circuit operation from narrowing by mounting the other end of an additional lead connected at its one end with one of first layer lead groups and the end of the one lead near two sides disposed at the opposite sides of an island. CONSTITUTION:The ends of leads of first layer lead groups A1-A12 are connected by bonding wirings 5 with bonding pads P1-P12 on an integrated circuit chip 4 disposed oppositely at near positions, and the ends of additional leads B1, B2 are further connected by bonding wirings with bonding pads P1', P7' disposed oppositely thereto. When the lead A1 is connected, for example, with a ground potential and the lead A7 is connected to a power source voltage, the leads B1, B2 are also connected respectively with the ground potential and the power source voltage so that the pads P1', P2' and P7, P7' disposed at two sides disposed at opposite sides on the chip are connected with the same ground potential and power source voltage.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、リードフレームを用いて外部リードのリード
付は組立が行われた集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device in which external leads are assembled using a lead frame.

〔従来の技術〕[Conventional technology]

第２図は、従来のパッケージ前の集積回路装置の平面図
である。図において、集積回路チップ４はリードフレー
ムのアイランド３に固着され、アイランドの周妙に先端
が集るように配置さｎたリードフレームの多数のり−ド
Ａ　１　＝　Ａ　１Ｈの先端部と、集積回路チップ４の
上のポンプイングツくツドＰ１〜Ｐ１！トの間がボンデ
ィングワイヤ５で接続されている。このように、集積回
路チップが固着されるアイランドと、その周りに配置さ
れた多数のリードが、外枠１により一体に連結された（
連結部は図示せず）リードフレームは一層の金属板から
形成されており、このため、外部からの信号は、通常１
本の特定のリードに接続されるだけであった。FIG. 2 is a plan view of a conventional integrated circuit device before packaging. In the figure, an integrated circuit chip 4 is fixed to an island 3 of a lead frame, and the tips of a large number of leads A 1 = A 1H of the lead frame are arranged so that the tips are gathered around the periphery of the island. Pumping tubes P1 to P1 on circuit chip 4! A bonding wire 5 connects between the two ends. In this way, the island to which the integrated circuit chip is fixed and the numerous leads arranged around it are integrally connected by the outer frame 1 (
(Connections not shown) The lead frame is formed from a single layer of metal plate, so external signals are usually
It was just connected to a specific lead in the book.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のリードフレームは、１層の金属層から成
っているので、集積回路チップ上のポンディングパッド
の位置はリードフレームの位置によって制約を受けると
いう欠点があった。すなわち、゛ポンディングパッドは
、接続相手のリードの近傍の集積回路チップ上に配置し
なけれはならず、集積回路チップ上の反対側でその信号
を使用する場合は、集積回路チップ上の配線によって、
チップの反対側へ信号を運ぶことが必要であった。The conventional lead frame described above has the disadvantage that the position of the bonding pad on the integrated circuit chip is restricted by the position of the lead frame because it is made of one metal layer. That is, the bonding pad must be placed on the integrated circuit chip near the leads to which it connects, and if the signal is used on the other side of the integrated circuit chip, it must be placed on the integrated circuit chip by the wiring on the integrated circuit chip. ,
It was necessary to carry the signal to the other side of the chip.

今後、半導体記憶装置が大容量化するにつれてチップサ
イズが大きくなっていくが、その場合、１つの信号配線
をチップの一端のポンディングパッドから反対側の端ま
で延はすと配線抵抗が大きくなり、回路動作上の不具合
を生じてしまうという問題がしばしば生じていた。In the future, as the capacity of semiconductor memory devices increases, the chip size will increase, but in that case, if one signal wiring is extended from the bonding pad at one end of the chip to the opposite end, the wiring resistance will increase. However, this often causes problems in circuit operation.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点に対し、本発明は、アイランドと一体であっ
た第１層のリード群と、このリード群のうちの一つのリ
ードに一端が接続され、絶縁物を介して前記リード群の
うちの複数のリードと交差して、前記アイランドをはさ
んだ反対側筐たは反対側近くまで他端が延在された付加
リードとを有し、前記アイランドに固着された集積回路
チップ上の、一つの信号線に接続される複数のポンディ
ングパッドのそれぞれの近くに、前記一つのリードと付
加リードの先端をそれぞれ配置する。In order to solve the above problems, the present invention includes a first layer lead group that is integrated with the island, one end of which is connected to one lead of the lead group, and one end of the first layer of leads that is integrated with the island. an additional lead that intersects with the plurality of leads and has its other end extended to the opposite side of the case across the island or close to the opposite side; The tips of the one lead and the additional lead are respectively arranged near each of the plurality of bonding pads connected to the signal line.

〔実施例〕〔Example〕

つき′に本発明を実施例により説明する。 The present invention will now be explained by way of examples.

第１図は本発明の一実施例のパッケージ前の平面図であ
る。第１図において、リードフレームの外枠ｌに吊りビ
ン２でもって連結されているアイランド３には、集積回
路チップ４が固着され、外枠ｌにタイバー（図示されて
いない）で連結された１２本の第１層リード群のリード
Ａ　Ｉ”’−’　Ａ　１２の先端部が、アイランド３の
周囲を囲んで配置されている。また、第１層リード群の
うちの一つのり−ドへ１には、接続点６において付加リ
ードＢ１の一端が接続され、付加゛リードＢ１は、絶縁
物合間にはさんでＡ２〜ＡＢ’）−ドと交差し、その他
端はＡｌｌ　　リードの先端と並んだ位置に露呈されて
いる。またｓ　Ａ？　　リードにもＡ１　リードと同様
に付加リードＢ、の一端が接続裳７において接続され、
途中、Ａｇ〜ｋ１２９−ドと絶縁物をはさんで交差し、
その他端はリード人１！の先端と並んだ位置に露呈され
ている。しかして、第１層リード群Ａｌ〜Ａ１２の各リ
ードの先端部は、相対して近くに位置する集積回路チッ
プ４上のポンディングパッドＰ１〜Ｐ１１とそれぞれボ
ンディングワイヤ５で接続されているが、さらに、付加
リードＨ１ｔＪの先端も相対するポンディングパッドＰ
　１’　＊　Ｐ　？’にそれぞれボンディングワイヤで
接続されている。ここで、例えばＡＩ　Ｊ−ドを接地電
位、Ａ７９−ドを電源電圧に接続するとすれば、付加リ
ードＢ。FIG. 1 is a plan view of an embodiment of the present invention before being packaged. In FIG. 1, an integrated circuit chip 4 is fixed to an island 3 connected to an outer frame l of the lead frame by a hanging pin 2, and an integrated circuit chip 4 is fixed to an island 3 connected to an outer frame l by a tie bar (not shown). The tips of the leads A I"'-' A 12 of the first layer lead group of the book are arranged surrounding the island 3. In addition, the tips of the leads A I"'-' A 12 of the first layer lead group are arranged surrounding the island 3. One end of the additional lead B1 is connected at the connection point 6, and the additional lead B1 intersects with the A2 to AB') leads between the insulators, and the other end is aligned with the tip of the All lead. In addition, one end of the additional lead B is connected to the sA? lead in the same way as the A1 lead at the connection sleeve 7,
On the way, it intersects the Ag~k129-de with an insulator in between,
The other end is lead person 1! It is exposed in line with the tip of the. Thus, the tips of the leads of the first layer lead group Al to A12 are connected to the bonding pads P1 to P11 on the integrated circuit chip 4 located relatively close to each other by bonding wires 5, respectively. Furthermore, the tip of the additional lead H1tJ is also connected to the opposing bonding pad P.
1' * P? ' are connected to each other with bonding wires. Here, for example, if the AI J- node is connected to the ground potential and the A79- node is connected to the power supply voltage, the additional lead B.

およびＢ、もそれぞれ接地電位と電源電圧につながり、
チップ上の互いに反対側に位置する２辺にそれぞれ配置
されているポンディングパッドＰ１とＰ１′、ならびに
ＰフとＰ７′は同一接地電位、電源電圧に接続されてい
ることになる。and B are also connected to ground potential and power supply voltage respectively,
The bonding pads P1 and P1', as well as the bonding pads P1 and P7', respectively arranged on two opposite sides of the chip, are connected to the same ground potential and power supply voltage.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は一端が第１層リード群の
一つに接続された付加リードの他端と、前記の一つのリ
ードの先端とを、アイランドの互いに反対側に位置する
２辺の近傍に設置することができ、その結果、集積回路
チップ上の２箇所に配置したポンディングパッドと同一
信号の２個のリードとを、ボンゲイングワイヤーで接続
することが可能となる。よって、集積回路チップ上に２
箇所以上に同一信号のポンディングパッドが設置できる
ため、接地電位、または電源電位に利用した場合、接地
電位の上昇または電源電位の降下が少なくなり、回路動
作上の動作範囲を狭くなることを防止できる。As explained above, the present invention connects the other end of the additional lead, one end of which is connected to one of the first layer lead group, and the tip of the one lead, to two sides of the island located on opposite sides. As a result, it is possible to connect bonding pads placed at two locations on an integrated circuit chip to two leads of the same signal using a bonding wire. Therefore, 2
Since bonding pads with the same signal can be installed in more than one location, when used for ground potential or power supply potential, the rise in ground potential or drop in power supply potential is reduced, and the operating range of the circuit is prevented from narrowing. can.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例のパッケージ前の平面図、第
２図は従来の集積回路装置のパッケージ前の平面図であ
る。 ｌ・・・・・・外枠、２・・・・・・吊りビン、３・・
・・・・アイランド、４・・・・・・集積回路チップ、
５・・・・・・ポンティングワイヤ、６，７・・・・°
・接続点、Ａ電〜Ａｔｚパ°゛°゛第１層リード群、Ｂ
ｌ　＋　Ｂ、・・・・・・付加リード、Ｐ１〜Ｆ’ｔｚ
・・・・・・ボンティ／ダハノド。FIG. 1 is a plan view of an embodiment of the present invention before the package, and FIG. 2 is a plan view of the conventional integrated circuit device before the package. l...Outer frame, 2...Hanging bottle, 3...
...Island, 4...Integrated circuit chip,
5...Ponting wire, 6,7...°
・Connection point, A wire ~ Atz pad °゛°゛1st layer lead group, B
l + B,...Additional lead, P1~F'tz
...Bonti/Dahanod.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を固着するアイランドと、前記アイランドの
周囲に内端部が集るように配置された多数のリードとを
もつリードフレームの前記アイランドに集積回路チップ
が固着され、このチップのボンディングパッドと前記リ
ード内端との間がボンディングワイヤで接続された集積
回路装置において、前記多数のリードは、前記アイラン
ドと一体であった第１層リード群と、この第１層リード
群のうちの一つのリードと一端が接続され、絶縁物を間
にはさんで前記リード群と交差し、他端が前記アイラン
ドを間にした反対側または反対側近くに延在された付加
リードとから形成されていることを特徴とする集積回路
装置。An integrated circuit chip is fixed to the island of a lead frame, which has an island to which a semiconductor element is fixed, and a large number of leads arranged so that their inner ends are gathered around the island, and the bonding pads of this chip and the leads are In an integrated circuit device in which the inner ends of the leads are connected by bonding wires, the plurality of leads include a first layer lead group that is integrated with the island, and one lead of the first layer lead group. and an additional lead connected at one end, intersecting the group of leads with an insulator in between, and the other end extending to the opposite side or near the opposite side with the island in between. An integrated circuit device characterized by:
JP60275420A 1985-12-06 1985-12-06 Integrated circuit device Pending JPS62134950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60275420A JPS62134950A (en) 1985-12-06 1985-12-06 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60275420A JPS62134950A (en) 1985-12-06 1985-12-06 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62134950A true JPS62134950A (en) 1987-06-18

Family

ID=17555257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60275420A Pending JPS62134950A (en) 1985-12-06 1985-12-06 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62134950A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5534729A (en) * 1993-06-29 1996-07-09 Texas Instruments Incorporated Integrated circuit lead frame for coupling to non-neighboring bond pads

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5534729A (en) * 1993-06-29 1996-07-09 Texas Instruments Incorporated Integrated circuit lead frame for coupling to non-neighboring bond pads

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