JPS63308331A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten the developing time of a package and to reduce the development cost by providing a patterned conductor between pads on a semiconductor chip and pins of the package, and altering the pattern. CONSTITUTION:An insulating land 3 with 16 patterned conductors C1-C16 on the surface surrounding a semiconductor chip l is provided between the semiconductor chip 1 provided with 16 pads D1-D16 on the upper periphery and a package 2 provided with the chip 1 on the center and having 16 pins P1-P16. The conductors C formed on the land 3 are patterned in alignment with the pin positions of the thus used package 2. Thus, since the lengths of all the leads can be shortened, it can prevent the leads from hanging or the flowing from deforming, thereby shortening the developing time of the package and reducing the development cost of the package.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a method of connecting external connection terminals on a semiconductor chip and lead wires of a lead wire attachment portion of a package.

[Conventional technology]

Generally, in a semiconductor device, circuit elements are fabricated within a single semiconductor chip such as silicon, and multiple external connection terminals (hereinafter referred to as pads) provided at the periphery of the top surface of the semiconductor chip are connected to the leads of the package. It is electrically connected to the outside by connecting a wire attachment part (hereinafter referred to as a bottle) with a lead wire made of aluminum or the like.

In conventional semiconductor devices, each required circuit function is formed on a semiconductor chip, and the connection pattern between pads and bins of the semiconductor chip is determined in accordance with a standardized package such as a 14.16-bin DIP. Therefore, this connection pattern is generally fixed for each semiconductor chip and does not pose much of a problem.

However, recently, mask slices have been created like gate arrays, and tens to dozens of slices have been created from one master slice.
Various types of semiconductor devices with tens of thousands of gates are now being manufactured, and depending on the number of inputs and outputs of these semiconductor chips, for example, 28, 64, 100.208
They are packaged in different number of bottles like bottles. Also, depending on the implementation in the device, it is housed in different types of packages such as DTP, PGA, and flat + PLCC.

In this case, since each semiconductor chip is formed using one mask slice, all of its pads are arranged in the same way, so the connection pattern of the lead wires is determined to match the package bins. There must be.

Furthermore, changing the wiring layout of the package to match the semiconductor chip is disadvantageous in terms of development time and cost.

FIG. 3 is a plan view of an example of a conventional semiconductor device.

As shown in FIG. 3, the 16 pads D1 to D16 formed on the periphery of the semiconductor chip 1 and the 16 pins 21 to P16 formed on the package 2 are arranged in aluminum by corresponding numbers. It is connected with lead wire 6.

In this case, the lead wires between the pad D6 and the bottle P6 and between the pad DI4 and the bottle P14 are particularly long due to the positional relationship between the pad and the bottle.

[Problem that the invention seeks to solve]

In the conventional semiconductor device described above, the lead wires may become long depending on the positional relationship between the pads on the semiconductor chip and the bottle of the package, so deformations such as sagging or flowing lead wires are likely to occur, and the edges of the semiconductor chip or contact with adjacent lead wires, causing short-circuit failure. For this reason, if the same semiconductor chip is housed in multiple types of packages, the wiring layout of the package must be changed, which results in longer package development time and higher package development costs.

An object of the present invention is to provide a semiconductor device that can shorten package development time and reduce package development costs.

[Means for solving problems]

A semiconductor device of the present invention includes a semiconductor chip having a plurality of external connection terminals formed on the periphery of the upper surface, a package having the semiconductor chip fixed in the center and having a plurality of lead wire attachment parts.
an insulating land provided between the semiconductor chip and the package and having a plurality of conductive portions formed on its surface;
A plurality of first lead wires that connect the external connection terminal and the corresponding conductor part, and a plurality of second lead wires that connect the conductor part and the corresponding lead wire attachment part. be done.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a first embodiment of the invention.

As shown in Figure 1, there are 16 pads D on the periphery of the top surface.
1 to D16, a package 2 with the semiconductor chip 1 fixed in the center and having 16 bins P1 to P16, and a package 2 surrounding the semiconductor chip 1 between the semiconductor chip 1 and the package 2. An insulating land 3 with 16 patterned conductor parts C1 to Ct6 formed thereon and a conductor part C corresponding to the pads D1 to D16.
1 to C16, and the vials 2 corresponding to the conductor parts C and C16.
and aluminum second lead wires 5 connecting the terminals 1 to PI6, respectively.

By patterning the conductor portion formed on the land 2 according to the pin arrangement of the package 2 to be used in this way, the length of all the lead wires can be shortened, thereby preventing deformation such as sagging or flowing of the lead wires. This can prevent the lead wires from coming into contact with the edges of the semiconductor chip or adjacent lead wires, thereby preventing short-circuit failures.

FIG. 2 is a plan view of a second embodiment of the invention.

As shown in FIG. 2, in the second embodiment, a semiconductor chip i
, four conductor parts C21 to C facing only one side of
24 patterned insulating land 3. has been established.

This is a semiconductor chip 1. When a semiconductor chip is equipped with large-scale circuits such as a microcomputer or memory, and its peripheral circuitry is configured by a gate array, the pads on the other three sides of the semiconductor chip are designed to fit each package. Land 3. has conductor portions C21 to C24 corresponding to only one side of the semiconductor chip including the gate array. It has been established.

In the second embodiment, the pattern of the conductor portion C21"""C24 is designed corresponding to one side of the semiconductor chip, so it corresponds to the four sides of the first embodiment shown in FIG. This method has the advantage that the development time can be further shortened and the development cost can be reduced compared to designing the pattern of the conductor part.

〔Effect of the invention〕

As explained above, the semiconductor device of the present invention provides a patterned conductive portion between the pad on the semiconductor chip and the bottle of the package, and by changing this pattern,
Since the same semiconductor chip can be housed in various packages having different shapes, the package development time is shortened and the development cost is reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a first embodiment of the invention, FIG. 2 is a plan view of a second embodiment of the invention, and FIG. 3 is a plan view of an example of a conventional semiconductor device. 1.1. ...Semiconductor chip, 2...Package, 3
．． 3. ...Land, 4.5.6...Lead wire, C1
-C16+ C21-C24...Conductor part, D1-D
16...Pad, P, ~P16...Bin. Agent Patent Attorney Susumu Uchihara (':. 1 Sensen Honhon Nafa 4.5 Hood Nara, Ct~C〃 Conductor π
V. DI-ρJbah", β~I:/i Goshi. Figure Z

Claims (1)

[Claims] A semiconductor chip having a plurality of external connection terminals formed on the periphery of the upper surface, a package having the semiconductor chip fixed in the center and having a plurality of lead wire attachment parts, and disposed between the semiconductor chip and the package. an insulating land having a plurality of conductor parts formed on its surface; a plurality of first lead wires connecting the conductor parts corresponding to the external connection terminal;
A semiconductor device comprising: a plurality of second lead wires connecting the conductor portion and the corresponding lead wire attachment portion.