JPS62133439U - - Google Patents

Info

Publication number
JPS62133439U
JPS62133439U JP1973586U JP1973586U JPS62133439U JP S62133439 U JPS62133439 U JP S62133439U JP 1973586 U JP1973586 U JP 1973586U JP 1973586 U JP1973586 U JP 1973586U JP S62133439 U JPS62133439 U JP S62133439U
Authority
JP
Japan
Prior art keywords
flop
type flip
stage
flip
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1973586U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1973586U priority Critical patent/JPS62133439U/ja
Publication of JPS62133439U publication Critical patent/JPS62133439U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す回路図、第
2図は6分の1の分周比で出力する場合のタイミ
ングチヤート、第3図は5分の1の分周比で出力
する場合のタイミングチヤートである。 1,2,3……D形フリツプフロツプ、4……
オアゲート、5……スイツチ。
Fig. 1 is a circuit diagram showing an example of this invention, Fig. 2 is a timing chart when outputting at a frequency division ratio of 1/6, and Fig. 3 is a timing chart for outputting at a frequency division ratio of 1/5. This is a timing chart for the case. 1, 2, 3...D-type flip-flop, 4...
Orgate, 5...Switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] D形フリツプフロツプを複数段に縦続接続し、
初段のD形フリツプフロツプの入力端子と最終段
のD形フリツプフロツプの反転出力端子とを接続
し、各段のリセツト端子を互いに接続し、さらに
初段の初段のD形フリツプフロツプのリセツト端
子と最終段のD形フリツプフロツプの出力端子と
を選択手段の切換えにより選択的に接続可能とし
たことを特徴とする分周回路。
D-type flip-flops are connected in cascade in multiple stages,
The input terminal of the D-type flip-flop in the first stage is connected to the inverted output terminal of the D-type flip-flop in the final stage, the reset terminals of each stage are connected to each other, and the reset terminal of the D-type flip-flop in the first stage and the D-type flip-flop in the final stage are connected. 1. A frequency divider circuit that can be selectively connected to an output terminal of a flip-flop by switching selection means.
JP1973586U 1986-02-13 1986-02-13 Pending JPS62133439U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1973586U JPS62133439U (en) 1986-02-13 1986-02-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1973586U JPS62133439U (en) 1986-02-13 1986-02-13

Publications (1)

Publication Number Publication Date
JPS62133439U true JPS62133439U (en) 1987-08-22

Family

ID=30814598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1973586U Pending JPS62133439U (en) 1986-02-13 1986-02-13

Country Status (1)

Country Link
JP (1) JPS62133439U (en)

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