JPS62130511A - 半導体素子製造方法 - Google Patents

半導体素子製造方法

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Publication number
JPS62130511A
JPS62130511A JP60269396A JP26939685A JPS62130511A JP S62130511 A JPS62130511 A JP S62130511A JP 60269396 A JP60269396 A JP 60269396A JP 26939685 A JP26939685 A JP 26939685A JP S62130511 A JPS62130511 A JP S62130511A
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Prior art keywords
ion
iii
substrate
compound semiconductor
ion implantation
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Pending
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JP60269396A
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Inventor
Takaro Kuroda
崇郎 黒田
Takeyuki Hiruma
健之 比留間
Hiroyoshi Matsumura
宏善 松村
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Hitachi Ltd
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Hitachi Ltd
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Priority to JP60269396A priority Critical patent/JPS62130511A/ja
Priority to US06/937,019 priority patent/US4766092A/en
Publication of JPS62130511A publication Critical patent/JPS62130511A/ja
Pending legal-status Critical Current

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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 [発明の利用分野〕 本発明は、化合物半導体層を元素半導体基板結晶上にエ
ピタキシャル成長させる方法に係り、特にSl、Ge等
の単体元素基板結晶表面にイオン注入を行なって該基板
結晶表面の格子定数をG a A s、InP等のm−
v族あるいはZnS等の■−■族化合物半導体の格子定
数に近づける方法に関する。
〔発明の背景〕
最近、SiやGeを基板とし、該基板上のM。
CVD法(有機金属化学蒸着法)やMBE法(分子線エ
ピタキシィ法)による低温成長により、半導体レーザや
HEMT (高電子移動度トランジスタ)の試作が行な
われている。GeあるいはGeをエピタキシャル成長さ
せたSi基板上にG a A s層をエピタキシャル成
長させる場合には、該エピタキシャル成長層へのGaの
オートドーピングが問題になる。Si基板上に直接G 
a A s層を成長させると、クロスハツチ(格子縞)
状のミスフィツト(格子不整合)転位が発生しやすい。
また、Ge、SiとAs、Pの結合力の方が、Ge、 
SLとGe、Aa等との結合力より強いことと、表面の
凹凸やステップが原因となって、アンチフェイズドメイ
ン(Anti phase Domain)と呼ばれる
一種の双晶構造が発生しやすい欠点がある。
〔発明の目的〕
本発明は、前述した従来技術の欠点を解消し、m−v族
あるいは■−■族化合物半導体層を表面上に形成しうる
ようなSi、Ge等からなる単体元素半導体基板結晶の
製造方法を提供することにある。
〔発明の概要〕 本発明は、Si、Geからなる半導体基板結晶の表面近
傍にあらかじめ0.5〜5μmの深さの領域にほぼ均一
濃度に該基板結晶の格子常数を適度に増大させるような
元素を高エネルギーイオン注入を行なって、その上にエ
ピタキシャル成長させる■−■族あるいはn−VI族化
合物半導体層との格子整合性を改善するようにしたもの
である。ここでイオン注入深さを0.5〜5umに選ん
だのは、0.5−以下ではイオン注入による効果が未だ
不足であり、また、5声如何に選んだのは、これ以上で
イオン注入エネルギーが大きくなり過ぎて実用的でなく
なるためである。
さらに、前記基板結晶表面に周期3000Å以下、振幅
1000Å以下の周期溝を形成しておくことにより、該
溝の底部から優先的に結晶成長が始まり、全体に拡がっ
て行くので、アンチフェイズドメインの発生を抑止する
ことも可能である。
〔発明の実施例〕
以下、本発明の詳細を実施例に基づいて説明する。
実施例 1 直径200 meφの(100)面Siウェハを通常の
有機洗浄処理した後、2群に分け、一群はそのままHF
:HNO3系エツチング液によりエツチングした後、直
ちにMOCVD法又はMBE法によりGaMAs系半導
体レーザ構造をエピタキシャル成長させたもの(比較例
)と、上記エツチング処理後、高エネルギーイオン注入
装置によりSi基板全面に表面から深さ3−までlXl
01g〜I X 101021r’の濃度でGeイオン
を注入した後。
比較例と同様にしてGaAuAs系半導体レーザを作製
したもの(本発明)とについて、表面状態と素子特性を
比較した。
Si基板上に半導体レーザ構造を直接成長させた結晶に
は、部分的にミスフィツト転位によるクロスハツチパタ
ーンの発生が見られ、レーザのしきい値は高く、寿命は
千時間以下のものがしばしば見られた。一方Geをイオ
ン注入した後、その上にエピタキシャル成長させた結晶
では、ミスフィツト転位発生はなく1通常のG、aAs
化合物半導体単結晶を基板として成長させた素子と同等
の性能及び寿命が得られた、この差はイオン注入層がS
L本来の格子定数よりも大きい値となることによりGa
A11As成長層との格子整合がよくなり、内部応力が
低減されたためと考えられる。また、Si基板表面のG
e′a度が高いものほど表面の鏡面性は向上した。
実施例 2 直径200 mφの(100)面Siウェハに、Snを
高エネルギーイオン注入法により2虜の深さまでlXl
0”〜1×102′′ロー3の濃度でイオン注入した後
、その上にGaAuAs系半導体レーザをM。
CVD法及びMBE法でエピタキシャル成長させたもの
と、GaAs基板上に上記レーザを直接成長させたもの
とについて、表面状態と素子特性を比較した。その結果
、Snイオン注入の場合には。
濃度が5X101g■−1を越えた注入層内には微小な
析出物が発生したが、この上に成長させたGaAAAs
層の表面モホロジーには影響はなく。
鏡面が得られた。また、レーザの特性及び寿命は、G 
a A s基板上に成長させたものと大差なかった。
さらに、Si基板結晶のごく表面(〜0.2虜以内)の
Si中のモル比をXとした場合の平均格子定数τは a=x・ (Sn格子定数6.46人)+ (1−x)
 ・(Siの格子定数5.43人)で表わされ、ここで
、Xを45%の高濃度にした場合には aΣ5.90人χInPの格子定数 となる。この上にInPに格子整合したInGaAsP
系半導体レーザをMOCVD法あるいはMBE法で作製
したところ、鏡面となり、この場合にもミスフィツト転
位の発生を防止できることがわかった。
以上述べてきた他に、Ge単結晶(100)ウェハにS
n をイオン注入したものを基板として、InGaAs
P系半導体レーザをエピタキシャル成長させたところ、
上記の場合と同様良好な特性が得られた。
また、以上の方法はZnS (格子定数5.420)、
CdS (格子定数5.832)等の■−■族化合物半
導体にも適用できた。
〔発明の効果〕
以上説明したところから明らかなように、本発明の方法
は、イオン注入法を用いているので、ウェハ面内の均一
性にすぐれており、特に多数の素子を同一ウェハ上に集
積できる点で、従来のGaAs、InP等の基板を用い
る場合に比べ、生産性、価格上有利である。

Claims (4)

    【特許請求の範囲】
  1. (1)GeあるいはSiからなる単結晶基板の表面から
    該単結晶の平均格子定数を所定量だけ増大せしめるイオ
    ン種元素を0.5〜5μmの深さにまで高エネルギーイ
    オン注入したものを基板結晶とし、該基板結晶のイオン
    注入面上にIII−V族あるいはII−VI族化合物半導体層
    をエピタキシャル成長させることを含むことを特徴とす
    る半導体素子製造方法。
  2. (2)特許請求の範囲第1項記載の半導体素子製造方法
    において、前記イオン種元素がGe、Sn、Inまたは
    Sbであることを特徴とする半導体素子製造方法。
  3. (3)特許請求の範囲第1項記載の半導体素子において
    、前記単結晶基板がSi、前記イオン種元素がGe、か
    つ前記III−V族化合物半導体がGaAsもしくは、格
    子定数がGaAsに近いIII−V族混晶であることを特
    徴とする半導体素子製造方法。
  4. (4)特許請求の範囲第1項記載の半導体素子製造方法
    において、前記イオン種元素がSn、前記III−V族化
    合物半導体がInPであることを特徴とする半導体素子
    製造方法。
JP60269396A 1985-12-02 1985-12-02 半導体素子製造方法 Pending JPS62130511A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP60269396A JPS62130511A (ja) 1985-12-02 1985-12-02 半導体素子製造方法
US06/937,019 US4766092A (en) 1985-12-02 1986-12-02 Method of growing heteroepitaxial InP on Si using Sn substrate implantation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60269396A JPS62130511A (ja) 1985-12-02 1985-12-02 半導体素子製造方法

Publications (1)

Publication Number Publication Date
JPS62130511A true JPS62130511A (ja) 1987-06-12

Family

ID=17471822

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Application Number Title Priority Date Filing Date
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Country Status (2)

Country Link
US (1) US4766092A (ja)
JP (1) JPS62130511A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01211913A (ja) * 1988-02-19 1989-08-25 Nippon Telegr & Teleph Corp <Ntt> エピタキシャル成長方法

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JP2569058B2 (ja) * 1987-07-10 1997-01-08 株式会社日立製作所 半導体装置
JP2619407B2 (ja) * 1987-08-24 1997-06-11 株式会社日立製作所 半導体装置の製造方法
JPH01207920A (ja) * 1988-02-16 1989-08-21 Oki Electric Ind Co Ltd InP半導体薄膜の製造方法
US5168077A (en) * 1989-03-31 1992-12-01 Kabushiki Kaisha Toshiba Method of manufacturing a p-type compound semiconductor thin film containing a iii-group element and a v-group element by metal organics chemical vapor deposition
FR2661040A1 (fr) * 1990-04-13 1991-10-18 Thomson Csf Procede d'adaptation entre deux materiaux semiconducteurs cristallises, et dispositif semiconducteur.
US6130160A (en) * 1996-10-02 2000-10-10 Micron Technology, Inc. Methods, complexes and system for forming metal-containing films
EP1571241A1 (en) * 2004-03-01 2005-09-07 S.O.I.T.E.C. Silicon on Insulator Technologies Method of manufacturing a wafer
CN102439696A (zh) * 2009-05-22 2012-05-02 住友化学株式会社 半导体基板及其制造方法、电子器件及其制造方法
KR102502885B1 (ko) 2015-10-06 2023-02-23 삼성전자주식회사 반도체 장치 및 그 제조 방법

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6164119A (ja) * 1984-09-05 1986-04-02 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

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