JPS6213043A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6213043A
JPS6213043A JP60151636A JP15163685A JPS6213043A JP S6213043 A JPS6213043 A JP S6213043A JP 60151636 A JP60151636 A JP 60151636A JP 15163685 A JP15163685 A JP 15163685A JP S6213043 A JPS6213043 A JP S6213043A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
integrated circuit
protective film
surface protective
mosaic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60151636A
Other languages
Japanese (ja)
Inventor
Masanori Ekuni
江国　正典
Masao Furuta
古田　征男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60151636A priority Critical patent/JPS6213043A/en
Publication of JPS6213043A publication Critical patent/JPS6213043A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To measure potential information on wirings under a surface protective film through a measuring electrode pattern by dispersively arranging conductive substance patterns infinitely in a mosaic or matrix shape on the uppermost surface protective film of a semiconductor integrated circuit element. CONSTITUTION:Measuring electrode patterns 6 are arranged in a mosaic or matrix shape on a surface protective film 4 except the leads of external electrode wirings 11-14 of bonding pads 7-10, and the intervals are the minimum size or less when forming a semiconductor integrated circuit element. Thus, even when the layout of the wiring pattern directly under the film 4 is altered, potential information of the wiring pattern directly thereunder can be measured by any of the patterns 6 arranged in a mosaic or matrix shape.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は配線パターンの上層に表面保護膜を有する半導
体集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit having a surface protective film over a wiring pattern.

従来の技術 半導体集積回路の診断方式として電子プローブを用いる
方法が近年不可欠となりつつある。第２図は配線パター
ンの」二層に表面保護膜を有する一般的な半導体集積回
路の断面図である。１は半導体基板、２は下層絶縁膜、
３は配線パターン、４は表面保護膜である。この構造に
おいて配線パターン３の電位情報を測定する方法として
、配線パ２　・・−。BACKGROUND OF THE INVENTION In recent years, methods using electronic probes have become indispensable as a diagnostic method for semiconductor integrated circuits. FIG. 2 is a sectional view of a general semiconductor integrated circuit having a surface protective film on two layers of a wiring pattern. 1 is a semiconductor substrate, 2 is a lower layer insulating film,
3 is a wiring pattern, and 4 is a surface protective film. As a method of measuring the potential information of the wiring pattern 3 in this structure, the wiring pattern 2 .

ターン３上の表面保護膜に電子ビーム（以下ＥＢと記す
）を照射し、発生した２次電子（以下ＳＲと記す）量を
検出することにより行ってきた。しかし、この方法では
表面保護膜４がＥＢ熱照射よりチャージアップし、ＳＥ
量が徐々に域少するため、ＳＥの測定波形が経時変化す
るという問題がある。この問題を解決するだめの一方策
を示したものが第３図である。つまり、配線パターン３
上の表面保護膜４上に導電性物質から成る測定電極パタ
ーン５を形成することにより、配線パターン３上の表面
保護膜４が一種のコンデンサの役割りをはだし、配線パ
ターン３の電位情報が、容量カップリングにより、測定
電極パターン５に現われることを利用するものである。This was done by irradiating the surface protective film on the turn 3 with an electron beam (hereinafter referred to as EB) and detecting the amount of secondary electrons (hereinafter referred to as SR) generated. However, in this method, the surface protective film 4 is charged up due to EB heat irradiation, and SE
Since the amount gradually decreases, there is a problem that the measured SE waveform changes over time. FIG. 3 shows one possible solution to this problem. In other words, wiring pattern 3
By forming the measurement electrode pattern 5 made of a conductive material on the upper surface protection film 4, the surface protection film 4 on the wiring pattern 3 plays the role of a kind of capacitor, and the potential information of the wiring pattern 3 is , which takes advantage of the fact that it appears on the measurement electrode pattern 5 due to capacitive coupling.

測定の方法は、測定電極パターン５にＥＢを照射するこ
とにより、配線パターン３の電位情報を表面保護膜を介
して測定電極パターン５から検知する。The measurement method is to irradiate the measurement electrode pattern 5 with EB and detect the potential information of the wiring pattern 3 from the measurement electrode pattern 5 through the surface protective film.

発明が解決しようとする問題点 この場合、測定電極パターンは配線パターンに合わせて
製作しているため配線パターンのレイアウド変更のたび
に測定電極パターンのレイアウト変更を行わなければな
らず、非常に不経済であった。Problems to be Solved by the Invention In this case, since the measurement electrode pattern is manufactured to match the wiring pattern, the layout of the measurement electrode pattern must be changed every time the layout of the wiring pattern is changed, which is extremely uneconomical. Met.

本発明は、表面保護膜を有する半導体集積回路において
、電子プローブにより表面保護膜下の配線の電位情報を
測定するために、測定電極パターンを変更せずに、いず
れの半導体集積回路にも連木発明は、外部電極取り出し
部を除いた半導体集積回路素子の表面保護膜最上面に、
導電性物質のパターンをモザイク状または網目状に無数
に分散配列した半導体集積回路である。In order to measure the potential information of the wiring under the surface protective film using an electronic probe in a semiconductor integrated circuit having a surface protective film, the present invention is capable of connecting any semiconductor integrated circuit without changing the measurement electrode pattern. The invention provides that the top surface of the surface protective film of the semiconductor integrated circuit element excluding the external electrode extraction portion,
It is a semiconductor integrated circuit in which a countless number of conductive material patterns are distributed and arranged in a mosaic or mesh pattern.

作用 本発明は表面保護膜下の配線の電位情報をＥＢ熱照射よ
るチャージアップなしに測定するだめの測定電極パター
ンのレイアウトを、モザイク状または網目状に配列した
ことにより、半導体装置の配線パターンのレイアウト変
更に依存しない一定の測定電極パターンでもって、半導
体集積回路の配線電位情報が得られる。Function The present invention improves the wiring pattern of semiconductor devices by arranging the layout of the measurement electrode pattern in a mosaic or mesh pattern to measure the potential information of the wiring under the surface protective film without charge-up due to EB heat irradiation. Wiring potential information of a semiconductor integrated circuit can be obtained using a constant measurement electrode pattern that is independent of layout changes.

実施例 第１図は、本発明に係る測定電極パターンを表面絶縁膜
４上に測定電極パターン６を適度な相互間隔で網目状に
配列した半導体集積回路の外観図である。測定電極パタ
ーン６はアルミニウム、ポリシリコン等導電性物質であ
ればよい。Embodiment FIG. 1 is an external view of a semiconductor integrated circuit in which measurement electrode patterns 6 according to the present invention are arranged on a surface insulating film 4 in a mesh pattern at appropriate intervals. The measurement electrode pattern 6 may be made of a conductive material such as aluminum or polysilicon.

上記測定電極パターン６はボンディングパソド部７，８
，９．１０等外部電極ワイヤ１１．１２゜ｊ３．１４へ
の取り出し部を除いた表面保護膜上にモザイク状または
網目状に配列されており、それぞれの間隔は半導体集積
回路素子形成時の最小寸法以上である。測定電極パター
ン６０個々の平面形状は、円形、方形いずれでもよい。The measurement electrode pattern 6 is the bonding pad portion 7, 8.
, 9.10 etc. External electrode wires 11.12゜j3.10 etc. are arranged in a mosaic or mesh pattern on the surface protective film excluding the lead-out portion to It is larger than the dimensions. The planar shape of each measurement electrode pattern 60 may be either circular or square.

以上のようにモザイク状または網目状に測定電極パター
ン６を形成しておくことにより、表面絶縁膜４直下の配
線パターンのレイアウト変更が行われた場合でも、上記
モザイク状または網目状に配列された測定電極パターン
６のいずれかにより、その直下の配線パターンの電位情
報を測定すると５ｔ・ とが可能に々る。By forming the measurement electrode pattern 6 in a mosaic or mesh pattern as described above, even if the layout of the wiring pattern directly under the surface insulating film 4 is changed, the measurement electrode pattern 6 arranged in the mosaic or mesh pattern can be changed. If any of the measurement electrode patterns 6 measures the potential information of the wiring pattern directly below it, it is possible to obtain 5t.

発明の詳細 な説明してきたように、本発明によれば配線パターン等
のレイアウト変更による測定電極パターンのレイアウト
変更を必要とせず、表面保護膜下の配線の電位情報をＥ
Ｂプローブにより、測定電極パターンを介して測定する
ことが可能と々す、非常に経済性に秀れている。As described in detail, according to the present invention, it is not necessary to change the layout of the measurement electrode pattern by changing the layout of the wiring pattern, etc., and the potential information of the wiring under the surface protective film can be
The B probe makes it possible to measure through the measurement electrode pattern, which is very economical.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例半導体集積回路の外観図、第２
図は配線の上層に表面保護膜を有する従来例半導体集積
回路の概略断面図、第３図は測定電極パターンを表面保
護膜上に形成した従来例半導体集積回路の概略断面図で
ある。 １・・・・・シリコン基板、２・・・・・・下層絶縁膜
、３・・・配線パターン、４・・・・・表面保護膜、５
，６・・・・・・測定電極パターン、７，８，９．１０
・・・・・・ポンディングパッド部、１１．１２，１３
．１４・・・・・・外部電極ワイヤ。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第３
図FIG. 1 is an external view of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG.
The figure is a schematic cross-sectional view of a conventional semiconductor integrated circuit having a surface protective film on the upper layer of wiring, and FIG. 3 is a schematic cross-sectional view of a conventional semiconductor integrated circuit in which a measurement electrode pattern is formed on the surface protective film. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Lower insulating film, 3...Wiring pattern, 4...Surface protection film, 5
, 6...Measurement electrode pattern, 7, 8, 9.10
・・・・・・Ponding pad part, 11.12,13
．． 14...External electrode wire. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
figure

Claims (1)

【特許請求の範囲】[Claims] 外部電極取り出し部を除いた半導体集積回路素子の表面
保護膜最上面に導電性物質のパターンをモザイク状また
は網目状に無数に分散配列したことを特徴とした半導体
集積回路。1. A semiconductor integrated circuit characterized in that numerous patterns of conductive material are dispersed and arranged in a mosaic or mesh pattern on the uppermost surface of a surface protective film of a semiconductor integrated circuit element excluding an external electrode lead-out portion.
JP60151636A 1985-07-10 1985-07-10 Semiconductor integrated circuit Pending JPS6213043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60151636A JPS6213043A (en) 1985-07-10 1985-07-10 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60151636A JPS6213043A (en) 1985-07-10 1985-07-10 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6213043A true JPS6213043A (en) 1987-01-21

Family

ID=15522875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60151636A Pending JPS6213043A (en) 1985-07-10 1985-07-10 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6213043A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5194931A (en) * 1989-06-13 1993-03-16 Kabushiki Kaisha Toshiba Master slice semiconductor device
US5618431A (en) * 1994-11-16 1997-04-08 Best Industries, Inc. Method of cleaning floating filter medium for biological filtering apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5194931A (en) * 1989-06-13 1993-03-16 Kabushiki Kaisha Toshiba Master slice semiconductor device
US5618431A (en) * 1994-11-16 1997-04-08 Best Industries, Inc. Method of cleaning floating filter medium for biological filtering apparatus

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