JPS62128546A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a direct contact having high reliability, to reduce the occupying area of a transistor and to improve the degree of integration by directly connecting electrodes for the transistor by using a silicified film consisting of a high melting-poing metal. CONSTITUTION:Side walls 6a, 6b formed by an insulator are shaped to the side surfaces of the peripheral sections of a wiring 5a composed of first polysilicon and a gate electrode 5b. Only the side wall 6a is removed selectively through photoengraving and an etching method, and a high melting-point metallic film 7 is shaped through a sputtering method, a CVD method or the like. The high melting-point metallic film 7 is silicified through heat treatment, and the high melting-point metallic film 7 not reacted on the side walls 6b and on a thick insulating film 2 is removed through the etching method. The formed silicified films have electric resistance lower than a conventional method, and connect a gate and a source or a drain. The silicified films are connected in the side section of the periphery of a wiring film consisting of first polysilicon, thus remarkably reducing an area required as a contact surface.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and particularly relates to a semiconductor integrated circuit device using a silicided film of a high melting point metal as a wiring material and a method for manufacturing the same. It is something.

[Prior Art] In a semiconductor IJ integrated circuit, in order to improve the concentration of 81 degrees, the gate of an insulated gate field effect transistor (hereinafter referred to as "M-S transistor") is connected to another M-S transistor or the same M-S transistor. It is necessary to use direct contact technology, which connects the source or drain of an engineering S transistor directly with silicon material, and this technology is especially essential for 7-lip and 70-tube type circuits such as memory cells of static random access memories. 3 and 4 show a conventional M/S integrated circuit device and direct contact according to its manufacturing method in the order of steps, and the conventional technology will be explained below using these figures.

First, FIG. 3 shows a method of extending the gate formed of the first polysilicon to the source/drain region of another MI transistor to form a direct contact. That is, as shown in Figure 3, a thick insulating film (two thick insulating films for isolation between elements) is formed on the surface of a P-type silicon substrate (Ti).
), then the thin gate insulating film [3] is thermally oxidized, OVD
After forming contact holes (9) by photolithography and etching, selectively form contact holes (9) by photolithography and etching.
Next, an N-type diffusion #+41 is formed near the surface of the silicon substrate +13 by ion implantation, thermal diffusivity, or the like.

Next, as shown in FIG. 3 fbl, a first polysilicon layer t51f is formed by OVD method or the like.

Next, as shown in FIG. 3(0), a first polysilicon@+51 t-pattern is formed by photoengraving and etching. (5a) and gate electrode (5b)e are formed.

Next, a silicon substrate (
An N-swelled diffusion layer (+a, 4b) ft is formed near the surface of the wafer. Through the above steps, wiring made of 41 polysilicon (
5a) is connected to the N-swelled diffusion layer (4a) which is the source or drain of the M/S transistor (+61) via the contact surface (1o) and the N-swelled diffusion layer (4).

Since this method includes the step of etching the thin gate insulating film (3), the gate insulating film is contaminated by resist, etc., resulting in a problem of lowering the yield and reliability.

There is a conventional example shown in FIG. 4 as an improved version of this.

This is a method of connecting via a second polysilicon pattern. First, as shown in Figure 4 (8L1), a thick insulating film (2) for isolation between elements, a thin gate insulation film (3), and @l A layer made of polysilicon, ffl (5a), a gate electrode (
5b), N swelling diffusion layer (4a s 4 b) f 3rd
It is formed by the same method as the conventional example shown in the figure.

Next, an RC insulating film (1) is formed by the same method as the gate insulation film, and by photolithography and etching, the portion spanning the -481 polysilicon wiring (5a) and the N-swelled diffusion layer (4a) is etched. The insulating film (11) and the gamma gate insulating film (3) are completely removed to form a large contact hole ua'i.Next, a second polysilicon film layer is formed by OVD method or the like, and buttering is performed. Then, the excess second polysilicon film is removed.The result is shown in FIG.

Through the above steps, the wiring made of the first polysilicon (5
a) Contact surface 11 second polysilicon layer (MIS, contact surface 101 t'' through) transistor #J
The N-swelled diffusion layer (4a
) is connected.

This method can prevent contamination of the thin gate insulating film (3), but it also prevents contamination of the thin gate insulating film (3).
There is a problem in that the number of steps increases as in the case of forming 3).

[Problem that the invention seeks to solve]

As mentioned above, in conventional semiconductor integrated circuit devices, in addition to the problems of contamination of the gate insulating film and an increase in the number of steps,
In circuit design, it is necessary to specifically accommodate the area required for the contact surface, resulting in a problem of increasing the area occupied by the MI transistor.

This invention was made to solve the above-mentioned problems, and it forms a direct contact with a small number of steps,
It is an object of the present invention to improve the yield and reliability, and to significantly reduce the area of the contact surface, thereby reducing the area occupied by the transistor and improving the degree of integration.

[Means for solving problems]

In the semiconductor integrated circuit device 2 according to the present invention, the connection between the electrodes of the transistor is realized by direct contact using a silicided film of a high melting point metal.

A method of manufacturing a semiconductor integrated circuit device according to the invention includes forming a high melting point metal on a silicon substrate and a silicon layer formed on the silicon substrate, and siliciding the metal by heat treatment.

[Effect]

The refractory metal silicide film of this invention allows direct contact between the silicon substrate and the silicon layer formed on the silicon substrate with low electrical resistance, reducing the margin for contact required in circuit pattern design. By making it unnecessary, the area occupied by the transistor fc', )R is reduced.

〔Example〕

The present invention will be explained below based on the embodiment g7IIIC shown in the drawings. FIG. 1 shows a semiconductor 1Jk8 according to an embodiment of the present invention.
11 shows the manufacturing method of the circuit device in the order of steps.

FIG. 1+al is basically in the same state as FIG. 4 fat, except that the area of the N-swelled diffusion layer (4a) is reduced compared to the conventional one, as will be described later.

In the method according to this embodiment, after the state shown in FIG.
Wiring (5a) made of polysilicon and gate polarization (5b)
A side wall (
aa, flb) f form. This side wall (6
A and ab) are formed, for example, by depositing a silicon oxide film over the entire surface and then anisotropically etching it.

This state is shown in FIG. 1 (b+).

Next, as shown in Figure 1 (0), the side wall (6a
) is selectively removed by photolithography and etching, and then a high melting point metal film (7) is formed by sputtering, OVD, or the like. Examples of the high melting point metals include tungsten (W), molybdenum (Mo), titanium (71 tantalum (Ta), chromium (Cr), vanadium (V), niobium (ah), and zirconium (Zr)).

The above-mentioned high melting reference 14 film (7) is turned into silicide by heat treatment, and is formed on the side wall (8b) and the thick insulating film (2).
) The unreacted high melting point metal film on (7) is removed by t-etching.

FIG. 2 shows an enlarged view of the state immediately after the heat treatment, showing silicided films (8a, 8b) formed near the surfaces of the wiring (5a) and the diffusion layers (4a, 4b).

Since the silicide film (8C) also grows in the lateral direction, the silicide film (8a) is continuous without being divided in the area diagram under the condition that the gate insulating film is sufficiently thin. On the other hand, since the insulator formed in the region (sidewall (fll) in Bl) is sufficiently thin, the silicided film (8a, 8c) formed on the diffusion layer (4a, 4b) and the gate electrode (5b) are The silicided film formed is not continuous, and an unreacted high melting point metal film (7) remains on the sidewall (6b). In this state, the high melting point metal film (7) is selectively removed by the entire etching method.

In the above embodiment, the N-swelled diffusion layer is formed on a P-type silicon substrate, but the P-swelled diffusion layer may be formed on an N-type silicon substrate.

Further, although the connection between M and S transistors that are in contact with each other has been described, it is also possible to connect between the gate and source or drain of the same transistor.

In this invention, the process of etching the gate insulating film +3) and completely forming the diffusion layer 14) shown in FIG.
By forming a silicided film of a high melting point metal on the first polysilicon wiring (5a) and the diffusion layer (4a) which is the source or drain region without the need for a forming process, direct contact can be established. It is characterized by doing.

The silidized layer formed as described above fully connects the gate and source or drain with a lower electrical resistance than in the conventional method. Since this connection is made in the wound area around the wiring pattern made of the first polysilicon, the area required for the contact surface can be significantly reduced compared to the conventional method.

〔Effect of the invention〕

As described above, according to the present invention, since the electrode gap is directly connected to 7 of the transistor using a silicided film of a refractory metal, highly reliable direct contact can be realized, and the area occupied by the transistor can be completely reduced. Even a small amount has the effect of improving the degree of integration.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing a semiconductor integrated circuit device and a manufacturing method thereof according to an embodiment of the present invention, and FIGS. 3 and 4 are cross-sectional views showing a conventional semiconductor integrated circuit device and a manufacturing method thereof. It is. In the figure, 1 is a P-type silicon substrate, 2 is a thick insulating film for isolation between elements, 3 is a gate insulating film, 4 (+a, 4b)
is an N expansion diffusion layer, 5 is a first polysilicon film, 5a and 5b are interconnects and gate electrodes made of first polysilicon, respectively, 8 (aa, ab) is a puidoqual formed of an insulator, and 7 is a high melting point metal. 8 (8a, 8b, 8c) is a silicided film, 9 is a contact hole, 10 is a contact surface, 11 is an insulating film, 12 is a contact hole, 18 is a second polysilicon film, 14 is a contact surface, 15 is a In the M/S transistor, a continuous region of the AI/i silicide film, B is a discontinuous region of the silicide film. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (8)

[Claims] (1) A silicon substrate, an insulating film formed on the silicon substrate, a contact hole selectively formed in the insulating film, and a silicon layer made of silicon or polysilicon formed on the insulating film. and a silicided film of a refractory metal that is continuously formed on the bottom and sides of the contact hole and on the silicon layer, and is in direct contact with the silicon substrate. (2) The semiconductor integrated circuit device according to claim 1, wherein the silicon layer is made of polysilicon. (3) The semiconductor integrated circuit device according to claim 1 or 2, wherein the silicided film is in contact with a diffusion layer in the silicon substrate. (4) The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the diffusion layer is a source or drain region of an insulated gate field effect transistor. (5) The high melting point metal is tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), chromium (Cr), vanadium (V), niobium (Nb), zirconium (Zr), or A semiconductor integrated circuit device according to any one of claims 1 to 4, characterized in that it is a multilayer film or a mixed film of these. (6) a step of forming an insulating film having a contact hole on the silicon substrate; a step of selectively forming a silicon layer on the insulating film; 1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a high-melting point metal film using a heat treatment; and siliciding the high-melting point metal film by heat treatment. (7) The semiconductor integrated circuit according to claim 6, characterized in that the gate of the insulated gate field effect transistor is connected to the source or drain region of another transistor or the same transistor by a silicided film. Method of manufacturing the device. (8) Whether the high melting point metal film is tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), chromium (Cr), vanadium (V), niobium (Nb), or zirconium (Zr). 8. The method of manufacturing a semiconductor integrated circuit device according to claim 6 or 7, wherein the semiconductor integrated circuit device is a multilayer film or a mixed film thereof.