JPS62128541A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the degree of integration, to increase working speed and to prevent the generation of a soft-error by forming source-drain regions having occupying area of the irreducible minimum being required in the longitudinal direction of a gate electrode while connecting a field oxide film for isolating elements to a second field oxide film extending toward the gate electrode. CONSTITUTION:A first element isolation region (a field oxide film) 15 is formed through thermal oxidation. A polysilicon layer 17 is etched to shape a gate electrode 17a. A second element isolation region (a field oxide film) 15a is formed up to a nitride film pattern 19a through thermal oxidation. The ions of an N-type impurity are implanted to an exposed substrate surface to shape source-drain diffusion regions 21, 22. A contact window is bored to an insulating film 25, an aluminum layer is grown on the whole surface, an Al wiring 26 brought into contact with source-drain electrode 23, 24 is formed through patterning, and a cover film 27 is shaped onto the whole surface. The second field oxide film 15a is formed in a self-alignment manner in the longitudinal direction of the gate electrode 17a, thus inhibiting the source-drain regions at the irreducible minimum being required.

Description

[Detailed Description of the Invention] [Summary] The source and drain regions of the MISFET are self-aligned (self-aligned) in the longitudinal direction of the gate with respect to the gate electrode.
The present invention relates to a semiconductor device and a method for manufacturing the same, characterized in that the device is formed by the method of the present invention.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device in which source and drain regions are formed in the longitudinal direction of a gate electrode with the minimum required area, and a method for manufacturing the same.

[Conventional technology]

The old 5FET (Metal I
nsulator Semiconductor Fie
ld Effect Transistor, MIS
In these figures, 31 is a semiconductor substrate (for example, a silicon substrate), 32 is a field oxide film, 33 is a channel cut layer for preventing the formation of an inversion layer, and 34 is a source region. , 35 is a drain region, 36 is a gate electrode, 37 is an insulating film of, for example, phosphorus silicate glass (PSG), and 38 is, for example, a polycrystalline silicon (polysilicon) layer that constitutes a source electrode and a drain electrode. .

In FIG. 2, 40 is an element formation region, 50 is a gate electrode window, 60 is a contact window, and the outside of the region 40 is an element isolation region. The patterns 40, 50, 60 are also mask patterns for forming the regions and windows.

The elements shown in FIGS. 2 and 3 are used, for example, to constitute a memory cell of a random access memory (RAM, which may be a random access memory or a static RAM).

[Problem that the invention seeks to solve]

When forming the old 5FET described above, mask patterns 40, 50, and 60 are used, but in general, the misalignment of the mask is taken into account and a margin shown by l in Figure 3 is provided between these patterns. There was a need. As a result, the area occupied by the source and drain diffusion regions becomes correspondingly larger, which leads to a reduction in the degree of integration. Furthermore,
When forming a 1'lAM memory cell using MISFET, scaling (
Scaling) causes a decrease in capacitance, which causes the problem of soft errors due to alpha particles, etc. However, if the junction area is large, the probability that the charge generated when alpha particles are incident will be absorbed by the junction increases, and soft - The error rate increases, and from this point of view as well, it is important to reduce the bonding area as much as possible. Note that the above-mentioned α rays are unavoidably generated from the insulating film, wiring layer, packaging material, etc. formed on the substrate.

The present invention was created in view of these points, and an object thereof is to provide an old 5FET with increased integration, increased speed, and prevention of soft errors, and a method for manufacturing the same.

[Means for solving problems]

FIG. 1(h) is a sectional view of the embodiment of the present invention, and FIG. 1(1) is (
h) is a plan view of the device;

In the present invention, the source and drain regions 21 have the minimum required area in the longitudinal direction of the gate electrode 17a.
．． On the other hand, a second field oxide film 15 for element isolation is formed with a second gate electrode 22 extending toward the gate electrode 17a.
Field oxidation 11m15a is connected.

[Effect]

In the above MISFET, the area of the element Ii1 is:
The structure is such that a second field oxide film is added to the first field oxide film, and the source region and drain region are formed with the minimum required area, making it possible to build up a large stack and increase speed. - The occurrence of errors can be suppressed, and since the expanded field region is formed by self-line, it can be easily formed without leaving any margin for alignment.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

Refer to FIG. 1 fa): An initial oxide film (silicon dioxide (5i02) film) 12 is formed on a semiconductor substrate, for example, a p-type silicon substrate 11, and a silicon nitride film (Si3Ng film, hereinafter simply referred to as a nitride film) is formed on it. ) 13 is grown, the nitride film 13 is patterned as shown in the figure, impurities of the same conductivity type as the silicon substrate are ion-implanted at a high concentration for channel cutting, and the first element isolation region (field oxidation MIA) is formed by thermal oxidation. Make 15. In addition, in the figure, 14 is a channel cut layer.

Figure 1 (see BL: Nitride film 13 and initial oxide film 12 are removed by etching, and a gate oxide film (SiO+
16 is formed, then a polysilicon layer 17 for forming a gate electrode is grown, it is doped, and a nitride film 18 is grown on the doped polysilicon layer 17.

FIG. 1 (See C1: Using the nitride film pattern 18a obtained by patterning the nitride film 18 as a mask, the polysilicon layer 17 is etched to form a gate electrode 17a.

Refer to FIG. 1(d): A nitride film 19 is layered and grown on the entire surface as shown by the dotted line in FIG. .

Refer to FIG. 1(e): A second element isolation region (field oxide film) 15a is formed by thermal oxidation to extend beyond the channel cut layer 14 and reach the nitride film pattern 19a.

Refer to FIG. 1(f): When the nitride film pattern 19a and the 5iOz film 16 not masked by the polysilicon pattern 17a are etched and oxidized to form 5102M'A20, the oxidation rate of the doped polysilicon is that of single crystal silicon. Therefore, the oxide film on the gate electrode 17a is thicker than the oxide film formed on the substrate portion where the source and drain diffusion regions are to be formed. .

FIG. 1 (see gl) When the 5iOz film on the substrate is etched, a SiO+ film is formed around the gate electrode 17a with a thickness larger than that of the 5iO2 film on the substrate as described above. The 5i0211 center 20a remains around the exposed substrate surface.Ion implantation of an impurity of the conductivity type opposite to that of the substrate, that is, n-type, is performed to form source and drain diffusion regions 21.
22 (Create FIG. 1 (see hl). In FIG. 1 fg), the implanted impurity ions are shown by dotted lines. Next, for example, a polysilicon layer 23 is grown and patterned to form source and drain electrodes 23 and 24.

Refer to Figure 1 (h): PSG is grown on the entire surface to form an insulator 1*25, a contact window is opened in the insulating film 25, and aluminum (
i) Grow a layer and pattern it to form an Al wiring 26 that makes contact with the source and drain electrodes 23 and 24, and then cover the entire surface with a cover film 27 (nitride film or PS
GIIA).

In the above method, since the second field oxide 1115a is formed in the longitudinal direction of the gate electrode 17a in a self-aligned manner, the margin l shown in FIG. It becomes possible to suppress it. Therefore, the area affected by the incidence of α rays is narrowed, and the probability of soft errors occurring is reduced.

FIG. 1 (1) is a plan view of the element in FIG. 1 (hl), which shows the source.

A state in which drain regions 21 and 22 are formed in the longitudinal direction of the gate electrode 17a is shown.

〔Effect of the invention〕

As described above, according to the present invention, a highly integrated and high-speed MISFET is formed using Selfa Line, and its source and drain regions occupy the minimum necessary area, so The probability of soft errors is reduced, and the traditionally formed negative charges are reduced to sources,
There is no risk of entering the drain region and reducing the amount of charge held in the junction, causing the memory cell to erase its memory or cause malfunction.
This is effective for improving the reliability of RAM, etc.

[Brief explanation of drawings]

Fig. 1 (al to h) is a sectional view of the embodiment of the present invention, Fig. 1 (1) is a plan view of the element in the same figure (hl), Fig. 2 is a plan view of the conventional example, Fig. 3 is Fig. 2 1, 11 is a silicon substrate, 12 is a 5i02 film, 13 is a nitride film, 14 is a channel cut layer, 15 is a field oxide film, and 15a is a second field. Oxide film, 16 is 5i02 film, 17 is polysilicon layer, 17a is gate electrode, 18 is nitride film, 19 is nitride film, L9a is nitride 1 pattern, 20 and 20a are 5i02 film, 21 is source region, 22 is Drain region, 23 is a source electrode, 24 is a drain electrode, 25 is a PSG film, 26 is an Aβ wiring, 27 is a cover film. Hii tag #rdbI!] Figure 1 unpublished

Claims (2)

[Claims] (1) In a metal insulator semiconductor field effect transistor (MISFET), the source and drain regions (21,
22) is formed, and a gate electrode (15) is formed in the element isolation field region (15).
7a) second field oxide film (1) expanded towards
5a) is formed. (2) In forming a MISFET, a step of forming a first element isolation region (15) on a semiconductor substrate (11), a step of forming a gate oxide film (16) and a gate electrode film (17) on the substrate (11) in this order. A step of forming a silicon nitride film (18) on the silicon nitride film (18), a step of patterning the silicon nitride film (18) and a gate electrode film (17) to form a gate electrode (17a), a step of forming a silicon nitride film on the entire surface. (19) is layered, and then a silicon nitride film pattern (19) is grown around the electrode (17a).
Step of etching the silicon nitride film by anisotropic etching as surrounded by a) Step of forming a second element isolation region (15a) reaching the silicon nitride film pattern (19a) by oxidation, Step of etching the silicon nitride film pattern (19a) and gate electrode (17
A step of etching the oxide film not masked by step a) and oxidizing the gate electrode so as to surround it with the oxide film, and etching the oxide film until the substrate surface is exposed to form source and drain regions (21, 22). 1. A method of manufacturing a semiconductor device, comprising the step of forming a wiring (26) that diffuses impurities and makes contact with source and drain electrodes (23, 24).