JPS62125661A - Complementary insulated gate field effect transistor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a variation in a threshold value voltage due to a variation in a gate length by forming a length of an electrode material layer in a channel direction longer than a portion relating to an n-channel transistor at a portion relating to a p-channel transistor. CONSTITUTION:The length of a gate electrode of a p-channel MOS transistor is formed longer than that of an n-channel MOS transistor so that the effective lengths Lne, Lpe of the channels are equalized. Accordingly, if the length L of the electrode is varied when forming the electrode by etching, when a variation in the length L of the same value occurs in the p-channel and n-channel transistors, since the length L is longer in the p-channel transistor, the variation rate of the length L is small. On the other hand, since the length L is shorter in the n-channel transistor, a variation rate of the length L is large. Thus, a variation in a threshold value voltage Vt can be reduced to improve a yield of a product.

Description

TECHNICAL FIELD The present invention relates to complementary insulated gate field effect transistor integrated circuits and methods of manufacturing the same.

Background technology Complementary insulated gate field effect transistor integrated circuit (0M
In the manufacturing of O3IC:), as the devices become smaller, variations in device characteristics occur due to process fluctuations in each process step (variations in temperature, processing accuracy, operator operations, etc.), resulting in lower product yields. There was a drawback that it decreased.

For example, variations in device characteristics include variations in the threshold voltage (vt) of a transistor.
The process step that causes the variation in I
In C, pMO5 and nMOs are different. In other words, in nMOs transistors, the gate oxide film thickness (TO) is the main factor that changes the threshold voltage (vt), and in pMO3 transistors, the gate length (
L) is the main factor that causes the largest variation in threshold voltage (Vt).

Therefore, in the manufacturing process of miniaturized 0MO9IC:, the gate i/oxide film thickness (TOX) and p
)! It was necessary to reduce fluctuations in the threshold voltage caused by fluctuations in the gate length (L) of the OS.

Purpose The present invention solves the problems of the prior art and improves nMO
s(7) To provide a complementary insulated gate field effect transistor integrated circuit and a method for manufacturing the same, which reduce fluctuations in threshold voltage caused by fluctuations in gate oxide film thickness (Tax) and gate length (L) of pMO8. Let 1-1 be the target.

According to the present invention, a semiconductor substrate, an insulating material layer formed on the main surface of the semiconductor substrate, and an electrode material layer formed on the main surface of the insulating material layer. , thereby forming p-channel type and n-channel type insulated gate field effect transistor integrated circuits. The length of the electrode material layer in the channel direction is such that the portion associated with the p-channel transistor is longer than the portion associated with the n-channel transistor. .

This integrated circuit is manufactured by the following method. That is, this method consists of a first step of forming a well of one conductivity type on the main surface of the silicon substrate, and a second step of depositing an oxide film on the main surface and a nitride film thereon. process and
The third step is to mask the nitride film and etch the nitride film leaving the region where the transistor will be formed, and then to ionize the region where the p-channel transistor will be formed and the region where the n-channel transistor will be formed. The fourth step is to form a field oxide film by implanting nitride and oxide films in the region where a p-channel transistor will be formed, and then mask the region where a p-channel transistor will be formed and perform etching to form a nitride film and an oxide film in the region where an n-channel transistor will be formed. A fifth step of removing the oxide film, a sixth step of growing the oxide film on the region where the n-channel transistor will be formed, and masking the region where the n-channel transistor will be formed, and removing the oxide film by etching.
a seventh step of removing the nitride film and oxide film on the region where the channel type transistor is to be formed, and a step of growing an oxide film in the region where the p channel type transistor is to be formed and the region where the n channel type transistor is to be formed. Step 8, and a ninth step of depositing a polycrystalline silicon layer on the main surface, and forming an n-channel transistor by masking the region of the polycrystalline silicon layer where the p-channel transistor is to be formed. a tenth step of introducing a first impurity into the region and activating it; an eleventh step of removing the mask and introducing a second impurity into the entire polycrystalline silicon layer; , forming a mask having substantially the same line width corresponding to the gate electrode of the transistor.
a thirteenth step of removing the portion of the polycrystalline silicon layer not covered by the mask by plasma etching, and removing the mask and removing the region of the polycrystalline silicon layer where a p-channel transistor will be formed. A fourteenth impurity is formed by diffusing a third impurity with a high diffusion coefficient into the region where the n-channel transistor is to be formed, and a fourth impurity with a low diffusion coefficient into the region where the n-channel transistor is to be formed. It includes a process.

DESCRIPTION OF EMBODIMENTS Embodiments of an insulated gate field effect transistor integrated circuit according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of an insulated gate field effect transistor integrated circuit according to the present invention, in which a p-channel transistor Q1 and an n-channel transistor Q2 are formed on the main surface of a silicon substrate 250. The p-channel transistor Q1 has two p-type diffusion regions 276b, 276b formed on the substrate 250, and a region between them with a gate oxide film 266 formed on the main surface, for example, of polycrystalline silicon. The n-channel transistor Q2 includes a gate electrode 274b formed of two n-channel transistors formed in a p-well 252 formed on the main surface of the substrate 250.
It includes ten diffusion regions 276a, 276a, and a gate electrode pi 274a made of, for example, a polycrystalline silicon layer formed on the main surface with a gate oxide film 264 interposed in a region between them. A field oxide film 260 serving as an element isolation region is formed between the p-channel transistor Q1 and the n-channel transistor Q2.

The gate oxide film 264 of the n-channel transistor Q2 is formed thicker than the gate oxide film 266 of the p-channel transistor Q1, so that the ratio β1 of the gain coefficient β2 of the n-channel transistor Q2 to that of the transistor Q1 is β1.
R is set to the required value.

The gate electrode g274b of the P-channel transistor Ql is formed longer than the gate electrode 274a of the N-channel transistor Q2, but the diffusion regions 276b, 278
b is formed wider than the diffusion regions 276a, 276a, so that the gate electrode 274a and the gate electrode 274
The effective lengths of the channels formed under b are substantially equal.

An example of a process for manufacturing a complementary IGFET (0MO3) integrated circuit according to the present invention will be described with reference to FIGS. 28 to 4B. In the second step, the p-channel transistor Q
1 and n-channel transistor Q2 have different gate a-oxide film thicknesses, and p-channel transistors Q1 and n-channel transistor Q1 have different thicknesses.
The channel transistors Q2 are manufactured to have different gate lengths.

First, as shown in FIG. 2A, a silicon substrate 250 is prepared, and a p-type well 252 is formed from one main surface thereof. Pad oxidation on this main surface +1!2254. A nitride film 25G is then deposited thereon. The thickness of the oxide film 254 may be, for example, 300 to 2,000 angstroms, and the thickness of the nitride film 256 may be, for example, about 1.000 to 2,000 angstroms.

Next, they are covered with photoresist, which is developed to form a nitride film 25, leaving an area where a transistor will be formed.
4 is plasma etched. The remaining portions are the nitride films 25B-1, 256-2 and photo 1 shown in FIG. 2B.
/ cyst 25B-1, 258-2. Therefore, B+ ions are implanted into the n-channel transistor region and P (phosphorous) ions are implanted into the p-channel transistor region to form a field oxidized film 260 in the elementary f isolation region (FIG. 2c).

Therefore, the region where the p-channel transistor, that is, the thin gate oxide film is to be formed, is covered with a photoresist 262, and the exposed portion is nitrided with 1i25B by plasma etching.
-2 is removed. The mask used for forming the p-type well 252 can be used to form the photoresist 262. Thereafter, the exposed portion of the pad oxide film 254 is removed by etching (FIG. 2D).

Next, the photoresist 262 is removed and the gate oxide film 2 is removed.
84 (Figure 2E).

Next, in the same manner as before, the n-channel transistor, that is, the region where the thick gate oxide film is to be formed, is covered with photoresist, and the exposed portion of the nitride film 25B-1 is removed by plasma etching. To form this photoresist, a mask that is an inversion of the mask pattern used to form the p-type well 252 is used. Thereafter, the exposed portion of the pad oxide film 254 is removed by wet etching.

Therefore, this photoresist was removed and the gate oxide film 2 was removed.
64 and 266, implanted with B+ ions and p
The threshold voltages of the channel FET and n-channel FET are controlled simultaneously (FIG. 2F). In addition, n-channel FE
If it is desired to separately control the formation of the T and P channel FET threshold levels, the ion implantation process may be performed separately for both transistor regions.

In this example, insulating film 264 is formed thicker than insulating film 266, which is controlled by going through two oxidation steps. Regarding the time required for oxidation, the gate oxide film is formed twice so that the ratio of the gate insulating film thickness d2 of the p-channel FET to the thickness dl of the n-channel FET is approximately 2.5. Find the oxidation time.

2 of non-ratio type inverters using this manufacturing process.
The ratio of the gate oxide film thickness of two transistor regions is 2
Assuming that the lengths and widths of the gate electrodes of the two transistors are the same, they are set to be substantially equal to about 2.5, corresponding to the aforementioned gain coefficient ratio βR. Therefore, in the above example, the thickness dl of the oxide film 264 is t,oo
o angstrom, and the thickness d2 of the oxide film 266 is 400 angstroms.
angstrom, the time t required for oxidation can be found from the logarithm direct m300 shown in FIG. Therefore, the oxidation time for the first gate oxide film formation (FIG. 2E) can be determined from this graph as t1 to t2.

A layer of polycrystalline silicon 268 is then deposited on the surface (
Figure 2G). Next, the □ surface of the polycrystalline silicon layer 268 is
The silicon oxide layer 270 is formed by oxidation to a thickness of, for example, about 1000 angstroms. p on the right
Channel MOS) Wet etching is performed while masking the region where the transistor is to be formed. This removes the silicon oxide layer 270 on the surface of the left p-type Y conductor (p well).

Therefore, this is exposed to the atmosphere of the POC 13 to thermally diffuse P (phosphorus) into the polycrystalline silicon layer 268 in the left region (FIG. 2H).

Next, the polycrystalline ingot layer 270 remaining on the main surface is completely removed. Then, P or As ions are implanted into the main surface. This ion implantation is carried out at approximately 50 to 200 K, for example.
With acceleration energy of eV, about 0.5~2!1016C1
-2 concentration (Figure 2I). In this way, P or As is doped into the polycrystalline silicon layer 268 to form the electrode layer 268 with good conductivity, but the region on the left side where the n channel is formed is more doped with P or As than the region where the p channel is formed on the right side. It is characterized by a large amount of doping and activation of them. In the later etching process, the electrode layer 268 in the left region is replaced by the electrode layer 268 in the right region.
This is to perform plasma etching that is closer to isotropy than 68.

Next, as shown in FIG. 2J, a mask 272 for forming polycrystalline silicon gate electrodes 274a and 274b (FIGS. 3A and 3B) of the MOS transistor is formed. This may be made of ordinary photoresist or the like. .

The width of the mask region 272 corresponding to the formed gates 2-4a and 274b does not need to be different between the P-channel MOS transistor and the n-channel MOS transistor, as shown in FIGS. 3A and 3B. The same width is sufficient. In this way, polycrystalline silicon layer 268 is plasma etched. The subsequent steps are normal 0MO
The manufacturing process may be the same as 3.

Referring to FIGS. 3A and 3B, portions of electrodes 274a and 274b are shown enlarged after this plasma etching. As will be seen from now on, the width Ln of the gate electrode 274a forming the n-channel MOS transistor is the width Ln of the gate electrode 274b forming the p-channel MOS transistor. formed narrower than p. This is because the concentration of P doped into the polycrystalline silicon layer 268 is high in the gate electrode 274a and low in the gate electrode 274b, and furthermore, the impurity is not sufficiently activated in the latter, so that the etching of the former is isotropic. This is because the latter etching is performed in an almost anisotropic state.

More specifically, to explain two-dimensionally from the plane in FIGS. 3A and 3B, the same thickness of the polycrystalline silicon layer 268, that is, the depth t in the direction perpendicular to the main plane of the substrate 250, is etched. The gate electrode 27
4a is etched by a length L-Ln, and the gate electrode 2
74b is kneaded by a shorter length L-Lp. After etching is completed, mask 272 is removed.

In subsequent steps, in order to form source/drain regions 276a and 278b of the MOS transistor, As is introduced into region 276a and B into region 278b by ion implantation, and diffused by a subsequent thermal process.

As is well known, the diffusion coefficient of B is higher than that of As, so as shown in FIGS. 4A and 4B, the p+ region 276b due to the diffusion of B becomes the n+ region 2 due to the diffusion of As.
It is formed deeper and wider than 76a. Therefore, the final C
Gate electrodes 274a and 27 in the MOS device
The effective lengths Lne and Lpe of the channels respectively formed under 4b are substantially equal between the p-channel MOS transistor and the n-channel MOS transistor. In other words, in the steps of FIGS. 2H and 2I, the electrode 27 is
The amount of P doping and degree of activation in corresponding regions in polycrystalline silicon layer 268 that define line widths Ln and Lp of lines 4a and 274b, respectively, are controlled.

Furthermore, B+ ions are again introduced into the column to simultaneously control the threshold voltages of the P-channel FET and the n-channel FET, thereby obtaining the integrated circuit shown in FIG. In addition, n-channel F
If it is desired to separately control the formation of the ET and p-channel FET threshold levels, the ion implantation process may be performed separately for both transistor regions.

After this, normal CMOS integrated circuit manufacturing steps are advantageously applied, including oxidation of the polycrystalline silicon layer, interlayer dielectric film (PLT), etc.
According to this embodiment, the MISFET integrated circuit is formed into an n-channel MOS transistor. Gate oxide film thickness (
Since the gate oxidation thickness (TOX) is made thicker than the gate oxidation thickness (TOX) of the p-channel MOS transistor, it takes a long time to oxidize the semiconductor substrate and form the oxide film, making it easy to control the film thickness. It is. Therefore, in an n-channel MOS transistor, the gate oxide film thickness (T
Since the gate oxide film thickness (ax) is thick, the rate of variation in the gate oxide film thickness (ax) is small. On the other hand, in a p-channel MOS transistor, since the gate oxide film thickness (Tox) is thin, the rate of variation in the gate oxide film thickness (Tax) is large. However, since the threshold voltage Vt of a P-channel MOS transistor is less dependent on the gate oxide film thickness than that of an n-channel MOS transistor, this does not pose a particular problem.

Therefore, the gate oxide film thickness (
Since the influence of fluctuations in (TOX) can be reduced, the yield of products can be improved.

Furthermore, by making the length of the gate electrode of the p-channel MOS transistor longer than the length of the gate electrode of the n-channel MOS transistor, the effective lengths Lne and Lpe of the channels are made equal. Therefore, if there is a change in the length L) of the gate electrode when forming the gate electrode by etching, the p-channel MOS
The rate of variation in the gate length (L) of the transistor is smaller than that of an n-channel MOS transistor. In other words, when the same value of variation in gate electrode length (L) occurs in a p-channel MOS transistor and an n-channel MOS transistor, the gate electrode length (L) of the p-channel MOS transistor is longer because the gate electrode length (L) is longer. The fluctuation rate of L) is small. On the other hand, in an n-channel MOS transistor, since the gate electrode length (L) is short, the rate of variation in the gate electrode length (L) is large.

Furthermore, according to the manufacturing method of this embodiment, when the electrodes 274a and 274b are formed by plasma etching, the former is etched in a nearly isotropic state, and the latter is etched in a nearly anisotropic state. . therefore,
In a p-channel MOS transistor, etching is performed in an almost anisotropic state, so the gate electrode length (L
) fluctuation is small. In this way, according to this embodiment, the threshold voltage Vt in the p-channel MOS transistor is
Since the influence of variation in the gate electrode length (L), which is the main cause of variation, can be reduced, the yield of products can be improved.

Further, for example, 0MO9 typically uses separate masks for p-channel transistors and n-channel transistors, which can be used to set separate device structures in both channel type transistor regions. Further, the film thickness can be easily controlled by devising a thermal oxidation process without using an etching process such as plasma etching or wet etching. Therefore, high film thickness controllability is achieved by changing the oxidation time.

Since 0MO3 originally has a non-ratio type structure, the β ratio should be set to be substantially equal to the ratio of charge carrier mobility that determines β of both channel type transistors in order to optimize the operating speed. It is enough. Therefore, about 1.5 to 3.
5. Preferably it is set to about 2 to 3. For example, in NHO2 according to the prior art, the β ratio must be set to about 4 to 6. In comparison, in this embodiment, the amount is only about half, which can be easily realized in terms of the manufacturing process.

Since the gate oxide film thickness in the p-channel transistor region is made thinner, the absolute value of the threshold voltage tends to become smaller, so there is no need to increase the dose of boron ion implantation for controlling the threshold voltage. Therefore, there is no risk of an increase in leakage current leaking to the substrate when the transistor is in a cut-off state.

The gate oxide film in the n-channel transistor region is set to be thicker than that in the p-channel transistor region, but the difference is about 3.5 times at most. Therefore, there is a feature that less enhancement ion implantation is required.

Furthermore, the effective length of each channel formed under the gate electrode in the final CXOS device is
p-channel MOS transistor and n-channel MOS)
The amount of P doped or the degree of activation of impurities in the corresponding region in the polycrystalline silicon layer that defines the width of the gate electrode is controlled so that it is substantially equal between the transistors. This allows the p-channel MOS to be formed.
By using a simple process that minimizes the differences in mask design and manufacturing process between p-channel MOS and n-channel MOS,
It is possible to manufacture a complementary metal oxide film semiconductor device in which there is substantially less difference in element shape and characteristic variations between an OS transistor and an n-channel MOS transistor.

Here, 0MO3 with a p-type well formed on an n-type substrate
Although the embodiments of the structure have been described, the present invention can be advantageously applied to CMO3 structures having other structures, such as structures in which an n-type well is formed on an n-type substrate, and structures formed by epitaxial growth. Needless to say.

Effects According to the present invention, the thickness of the gate oxide film (Tax) of the n-channel MOS transistor is made thicker than the gate oxide film thickness (Tow) of the p-channel MOS transistor. Gate oxide film thickness (To
The influence of fluctuations in w) can be reduced.

Also, since the length of the gate electrode of the p-channel MOS transistor is longer than that of the n-channel MOS transistor, the length of the gate electrode of the p-channel MOS transistor is longer than that of the n-channel MOS transistor.
The influence of variation in gate electrode length (L), which is the main cause of variation in threshold voltage Vt in a transistor, can be reduced.

Therefore, fluctuations in the threshold voltage Vt can be reduced and product yield can be improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing one embodiment of a complementary insulated gate field effect transistor integrated circuit according to the present invention, and FIGS. 28 to 2J are main steps in the manufacturing process of an integrated circuit according to an embodiment of the present invention. 3A, 3B, 4A, and 4B are step-by-step process explanatory cross-sectional views of
FIG. 6 is a partially enlarged cross-sectional view showing steps for the p-channel region and the n-channel region, respectively, in steps after the step shown in FIG. FIG. 5 is a graph used to determine the characteristic parameters of the circuit in the manufacturing process shown in FIGS. 28 to 2F. Explanation of symbols of main parts 264.28Ei, , gate oxide film 268,
, , , polycrystalline silicon layer 270 , , , ,
Polycrystalline silicon oxide layer 272, mask 274a, 274b, gate electrode 278a, 278b, diffusion region Patent applicant: Fuji Photo Film Co., Ltd. Agent Number: Takao Maruyama, Figure 1, Figure 2A, Figure 2B Fig. 2C Fig. 2D Fig. 2E Fig. 2F Fig. 2G Fig. 2H Fig. 2 Construction plan pi or As =-r-Continuation] Ensho January 27, 1986

Claims (1)

[Claims] 1. A semiconductor substrate, an insulating material layer formed on one main surface of the semiconductor substrate, and an electrode material layer formed on the insulating material layer, thereby forming a p-channel In a complementary insulated gate field effect transistor integrated circuit in which a type of insulated gate field effect transistor and an n-channel type insulated gate field effect transistor are formed, The length of the electrode material layer in the channel direction is such that a portion related to a p-channel transistor is formed to be thicker than a portion related to an n-channel transistor. type insulated gate field effect transistor integrated circuit. 2. The integrated circuit according to claim 1, wherein the ratio of the thickness of the portion of the insulating material layer associated with the n-channel transistor to the thickness of the portion associated with the p-channel transistor is equal to or less than that of the corresponding transistor. an integrated circuit characterized in that the integrated circuit substantially corresponds to a charge mobility ratio defining a channel conductivity type of the integrated circuit. 3. In the integrated circuit according to claim 1, the difference in length in the channel direction between the portion of the electrode material layer related to the p-channel transistor and the portion related to the n-channel transistor is An integrated circuit characterized in that the integrated circuit is configured such that a channel having substantially the same effective channel length is formed between a type transistor and an n-channel type transistor. 4. A method for manufacturing a complementary insulated gate field effect transistor integrated circuit, the method comprising: a first step of forming a well of one conductivity type on one main surface of a silicon substrate; and forming an oxide film on the main surface. , and a second step of depositing a nitride film thereon; a third step of masking the nitride film and etching the nitride film leaving a region where a transistor will be formed; A fourth step is to form a field oxide film by implanting ions into the region where the transistor is to be formed and the region where the n-channel transistor is to be formed, and the region where the p-channel transistor is to be formed is masked and etched to form an a fifth step of removing a nitride film and an oxide film on a region where a channel type transistor will be formed; a sixth step of growing an oxide film on a region where an n channel type transistor will be formed; A seventh step of masking the region where the transistor is to be formed and removing the nitride film and oxide film on the region where the p-channel transistor is to be formed by etching; an eighth step of growing an oxide film in a region where a transistor is to be formed; a ninth step of depositing a layer of polycrystalline silicon on the main surface; a tenth step of masking the region to be formed and introducing the first impurity into another region and activating it; and an eleventh step of removing the mask and introducing the second impurity into the entire polycrystalline silicon layer. a twelfth step of forming a mask having substantially the same line width on the surface of the polycrystalline silicon layer corresponding to the gate electrode of the transistor; a thirteenth step of removing the remaining portions by plasma etching, and removing the mask and diffusing a third impurity having a high diffusion coefficient into a region of the polycrystalline silicon layer where a p-channel transistor is to be formed. and a fourteenth step of forming source/drain regions of the transistor by diffusing a fourth impurity having a low diffusion coefficient into the region where the n-channel transistor is to be formed. A method of manufacturing an insulated gate field effect transistor integrated circuit. 5. The method according to claim 4, characterized in that in the tenth step, P is doped as the first impurity in an atmosphere of POCl_3, and the second impurity contains P or As. manufacturing method.