JPH11266011A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain the short channel effect and the reverse short channel effect. SOLUTION: A semiconductor device is featured by its mnanufacturing method having the five steps, i.e., a first step of forming an LDD region 8 by ion implanting a first conductivity-type impurity on a semiconductor substrate 2 with a gate electrode 7 formed thereon through a gate insulating film 3, a second step of forming a first inversion layer 9a on the lower part of the LDD region by ion implanting a second conductivity type impurity using the gate 7 as a mask, a third step of forming a second inversion layer 9b on the side part of the LDD region 8 on the gate electrode 7 side by ion implanting the second conductivity-type impurity using the gate electrode 7 as a mask, a fourth step of forming a sidewall spacer 11 on the sidewall of the gate electrode 7, as well as a fifth step of forming a source/drain region 12 using the gate electrode 7 and the sidewall spacer 11 as masks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device that has been miniaturized, and has an inverse short channel effect (a phenomenon in which the Vth value increases as the gate length becomes shorter in a short channel region) and a short channel effect (Vth decreases, The present invention relates to a semiconductor device having both desired characteristics, ie, a phenomenon that the punch-through breakdown voltage is degraded, and having desired characteristics, and a method for stably manufacturing the semiconductor device.

[0002]

2. Description of the Related Art As a conventional semiconductor device, there is known a MOS transistor including a gate electrode having a sidewall made of an oxide film on a side wall and a source / drain region having an LDD structure. It is also known that a short channel effect is more likely to occur as a semiconductor device is miniaturized. As a countermeasure, reducing the influence of the drain voltage on the channel region and the source region can be mentioned.
Specifically, a method of forming an inversion layer (also referred to as a halo ion implantation layer or a pocket layer) having conductivity opposite to that of the source / drain region between the LDD region and the channel region by an ion implantation method is generally used. It is being adopted into.

A method of manufacturing a conventional semiconductor device (here, a MOS transistor) having the above-described inversion layer will be described. First, on a semiconductor substrate 2 having an element isolation region 1,
Ion implantation for adjusting Vth (for example, ¹¹ B ⁺ , implantation energy: 20 KeV, implantation amount: 10 × 10 ¹² cm)
After performing ^-2 ), perform sufficient pretreatment such as RCA cleaning. Thereafter, oxidation (900 ° C.) is performed to form a gate insulating film 3 of about 100 to 140 °.

Next, using the polysilicon film 4 as a raw material,
Deposit about 1000 to 1500 ° under the condition of iH ₄ gas and 620 ° C. Thereafter, phosphorus is applied to the polysilicon film 4 for 850.
The solid phase diffusion (N ⁺ depot) is performed at about 15 ° C. for about 15 minutes. Since PSG is formed on the surface of the polysilicon film 4 during solid phase diffusion, the PSG is removed by HF clean.

[0005] WSi5 is deposited on the polysilicon film 4 by 360.
Under conditions of ° C., about 1000 to 2000 ° is deposited. WS
A resist is applied on i5, and a resist pattern 6 is formed by a photo method (see FIG. 3A). Using the resist pattern 6 as a mask, the WSi / polysilicon film 4 is dry-etched to form a gate electrode 7 of the transistor.
(And a part of the wiring portion) are formed (see FIG. 3B). As a process after dry etching, wet etching (HF
Clean) for about 2 seconds (1% HF). Further, the entire surface of the semiconductor substrate is oxidized at 900 ° C. for 10 minutes to form a 50 ° protective film (not shown).

Next, low concentration ion implantation is performed, and LDD is performed.
Form a region (in the case of NMOS transistor
³¹ P ⁺ , 30 Kev, 4.0 to 5.0 × 10 ¹³ cm ⁻² ,
Injection angle 0 °, ⁴⁹ B for PMOS transistor
F ₂ ⁺ , 30 KeV, 2.0 to 4.0 × 10 ¹³ cm ⁻² ,
Injection angle 0 °) (see FIG. 3 (c)). Next, as the gate length of the transistor is reduced, an inversion layer 9 is further formed by ion implantation below the LDD region 8 as a measure for suppressing the short channel effect (in the case of an NMOS transistor,
¹¹ B ⁺ , 50 KeV, 6.0 to 8.0 × 10 ¹² cm ⁻² ,
Injection angle 30 ° C to 40 ° C, PMOS. In case of Tr
³¹ P ⁺ , 150 KeV, 1.0 to 1.5 × 10 ¹³ c
m ⁻² , injection angle 30 ° to 40 °) (see FIG. 3D).

Thereafter, an HTO film 10 is deposited (FIG. 3).
(See (e)), and then dry etching is used to
The entire surface of the film 10 is etched back (wet etching may be performed thereafter), thereby forming sidewall spacers 11 on the side surfaces of the gate electrode (FIG. 3).
(F)). After the formation of the sidewall spacer 11, high-concentration ion implantation is performed to form the source / drain region 12 ( ⁷⁵ A in the case of an NMOS transistor).
s ⁺ , 40 KeV, 2.0 to 4.0 × 10 ¹⁵ cm ⁻² , implantation angle 7 °, ⁴⁹ BF ₂ ^{+ for} a PMOS transistor,
30 KeV, 1.0-3.0 × 10 ¹⁵ cm ⁻² , injection angle 7
°) (see FIG. 3 (g)).

FIG. 4 is an enlarged view of the periphery of the gate electrode shown in FIG. Japanese Patent Application Laid-Open No. Hei 8-222645 discloses a method for manufacturing a CMOS transistor. In this publication, an N-type impurity is implanted for forming an LDD region of an N-channel transistor over the entire surface of a semiconductor substrate before a gate electrode is formed. At the time of this implantation, an N-type impurity is also implanted into the P-channel transistor at the same time. This N-type impurity is
Used as a punch-through stopper.

That is, the LDD of the N-channel transistor
It describes a method of simultaneously forming an inversion layer of a P-channel transistor by implanting an N-type impurity for forming a region over the entire surface. Further, conventionally, implantation for forming the channel region and the inversion layer is performed separately even though impurities of the same conductivity type are implanted. A method for simplifying this implantation step is described in Japanese Patent Application Laid-Open No. 9-64361.

That is, after forming the gate electrode, impurities are implanted with relatively high energy. In the channel region and the source / drain region, there is a difference in the implantation depth of the impurity from the surface of the semiconductor substrate depending on the presence or absence of the gate electrode. As a result, the concentration profile after the implantation is divided into two times at individual implantation energies. The distribution is the same as when the injection is performed. Therefore, the channel region and the inversion layer can be formed simultaneously.

The semiconductor device obtained by the method described in JP-A-8-222645 and JP-A-9-64361 has the same structure as that of FIG.

[0012]

As described above, with the miniaturization of transistors, an inversion layer having conductivity opposite to that of the source / drain regions is formed around the LDD region to reduce the short channel effect. It is becoming more common to control.
However, when the miniaturization is further advanced and the inversion layers of the source region and the drain region are too close to each other, an inverse short channel effect occurs. To suppress this, the impurity concentration of the inversion layer may be reduced, but if the impurity concentration of the inversion layer becomes too low, the suppression of the short channel effect becomes insufficient (the punch-through breakdown voltage is deteriorated).

That is, when miniaturization is advanced, the short channel effect is severely generated, and it is considered that the punch-through breakdown voltage is deteriorated. Further, at the same time, an inversion layer existing between the LDD region and the channel region may cause an inverse short channel effect. Therefore, the characteristics of the transistor have become very unstable. Also, JP-A-8-22264
In the case of the method described in Japanese Patent Application Laid-Open No. 5-264, an inversion layer can be formed only on one of an N-channel transistor and a P-channel transistor, and the process can be simplified only by one implantation.

The impurity concentrations of the LDD region of the N-channel transistor and the inversion layer of the P-channel transistor are as follows:
Must be the same. However, when the concentrations of both are optimized, they are not always equal, and it is very difficult to adjust the optimal conditions. In this case, either the transistor characteristics or the simplification of the manufacturing process must be prioritized, resulting in a very unstable process.

Further, in the case of the method described in Japanese Patent Application Laid-Open No. 9-64361, the manufacturing process can be effectively simplified only for an N-channel transistor. In addition, the concentration distribution of the channel region depends on the thickness variation of the gate electrode, and as a result, it is one of the major factors of variation in transistor characteristics such as Vth.

[0016]

The inventor of the present invention divided the inversion layer into two layers and adjusted the amount of impurities as appropriate to suppress both the short-channel effect and the inverse short-channel effect, thereby achieving stable operation. The present inventors have found that a fine semiconductor device having characteristics can be obtained, and have reached the present invention. Thus, according to the present invention, a step of forming an LDD region by ion-implanting a first conductivity type impurity on a semiconductor substrate on which a gate electrode is formed via a gate insulating film; Forming a first inversion layer below the LDD region by ion-implanting a conductive impurity;
Forming a second inversion layer on the side of the LDD region on the gate electrode side by ion-implanting impurities of the second conductivity type using the gate electrode as a mask; and forming a sidewall spacer on a side wall of the gate electrode. Forming source / drain regions by ion implantation using the gate electrode and the sidewall spacer as a mask.

Further, according to the present invention, the gate electrode is formed on the semiconductor substrate via the gate insulating film, the sidewall spacer is formed on the side wall of the gate electrode, and the gate electrode is formed on the semiconductor substrate below the sidewall spacer. A source / drain region formed in a direction away from the semiconductor device, an LDD region and a first inversion layer formed sequentially from the surface of the semiconductor substrate on a side wall of the source / drain region below the sidewall spacer, an LDD region and a first inversion layer below the gate electrode;
There is provided a semiconductor device comprising a second inversion layer formed on a side wall of the inversion layer.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described below in the order of steps. Note that the method for manufacturing a semiconductor device of the present invention can be suitably used for a method for manufacturing an NMOS transistor and a PMOS transistor. First, an LDD region is formed by ion-implanting a first conductivity type impurity on a semiconductor substrate on which a gate electrode is formed via a gate insulating film.

The semiconductor substrate that can be used in the present invention is not particularly limited, but usually a silicon substrate is used. Further, an impurity may be added to the semiconductor substrate in order to impart desired P-type or N-type conductivity. The impurity imparting P-type conductivity includes boron and the like, and the impurity imparting N-type conductivity includes phosphorus and arsenic. Note that an impurity may be ion-implanted into a region of the semiconductor substrate where the semiconductor device is to be formed in order to adjust the Vth value to a desired value. Further, a P-type or N-type well may be formed in advance on the semiconductor substrate.

When the semiconductor substrate is a silicon substrate, the gate insulating film is usually made of a silicon oxide film, a silicon nitride film or a laminated film thereof. As a method for forming the gate insulating film, any known method such as a thermal oxidation method and a CVD method can be used. Next, a gate electrode is formed on the gate insulating film. As a material constituting the gate electrode,
Polysilicon, metal (eg, copper, aluminum, etc.),
Silicide (for example, WSi, TiSi, or the like) is given. Here, the gate electrode may be made of a laminated film of the above-mentioned material (for example, polysilicon and WSi). The method for forming the gate electrode is not particularly limited, and any known method can be used. For example, there is a method in which a material for forming a gate electrode is deposited on a gate insulating film and then etched by using a resist mask.

Further, an LDD region is formed by ion-implanting impurities of the first conductivity type into the semiconductor substrate using the gate electrode as a mask. Here, the first conductivity type indicates either P-type or N-type. The second conductivity type described below is N when the first conductivity type is P-type.
The type is shown, and the N type is shown as P type. In addition, for example, the ion implantation of impurities is performed at an implantation angle of 0 °, and when manufacturing an NMOS transistor, ³¹ P ⁺ , an implantation energy of 30 to 35 keV, and an implantation amount of 4.0 to 5.0 × 10 ¹³ c.
m ^-2 , ⁴⁹ BF when manufacturing PMOS transistors
₂ ⁺ , implantation energy 30-35 keV and implantation dose 2.
It can be performed under the condition of 0 to 4.0 × 10 ¹³ cm ⁻² .

Next, a second inversion impurity is ion-implanted using the gate electrode as a mask to form a first inversion layer below the LDD region. The impurity ion implantation is performed, for example, at an implantation angle of 0 °, and when manufacturing an NMOS transistor, ¹¹ B ⁺ and an implantation energy of 55 to 60 keV.
In the case of manufacturing a PMOS transistor with an implantation amount of 6.0 to 8.0 × 10 ¹² cm ⁻² , ³¹ P ⁺ , an implantation energy of 150 to 155 keV, and an implantation amount of 1.0 to 1.5 × 10
It can be performed under the condition of ¹³ cm ^-2 .

Next, the second conductive layer is formed using the gate electrode as a mask.
Ion implantation of the gate type
Forming a second inversion layer on the side of the LDD region and the first inversion layer;
You. Impurity ion implantation is performed, for example, by setting the implantation angle to 30 to 4
0 ° and when manufacturing NMOS transistors,¹¹
B⁺2. implantation energy 55-60 keV and implantation amount 3.
0 to 4.0 × 10¹²cm^-2Manufactures PMOS transistors
To build³¹P⁺, Injection energy 150-155
KeV and injection amount 5.0 to 7.5 × 10¹²cm ^-2Condition
Can be done below.

As described above, in the present invention, the inversion layer is formed by the first layer.
And ion implantation for forming them is performed twice by changing conditions such as implantation amount and implantation angle. That is, the first inversion layer exists below the LDD region, while the second inversion layer exists between the LDD region and the channel region, and the first inversion layer has a higher impurity concentration than the second inversion layer. doing. In the present invention, the first inversion layer contributes to the suppression of the short channel effect and the improvement of the punch-through breakdown voltage, and the second inversion layer contributes to the suppression of the inverse short channel effect on the short channel side.

Next, a sidewall spacer is formed on the side wall of the gate electrode. As a material forming the sidewall spacer, for example, a silicon oxide film (HTO)
Film) and a silicon nitride film. The method for forming the sidewall spacer is not particularly limited, and any known method can be used. For example, a material forming a sidewall spacer is deposited on the entire surface of a semiconductor substrate by a CVD method or the like, and then formed by an etching method combining anisotropic etching such as dry etching and isotropic etching such as wet etching. Can be.

Thereafter, the gate electrode and the sidewalls
Saw by ion implantation using pacer as a mask
And a drain / drain region. Impurities
For the ON injection, for example, the injection angle is set to 0 ° and the NMOS transistor is turned on.
When manufacturing transistors, ⁷⁵As⁺, Injection energy
40-45 keV and injection amount 2.0-4.0 × 10^Fifteenc
m^-2, When manufacturing a PMOS transistor,⁴⁹BF
_Two ⁺, Implantation energy 30-35 keV and implantation amount 1.
0-3.0 × 10^Fifteencm^-2Can be done under the conditions
You.

Through the above steps, the gate electrode formed on the semiconductor substrate via the gate insulating film, the side wall spacer formed on the side wall of the gate electrode, and the semiconductor substrate below the side wall spacer in a direction away from the gate electrode. The formed source / drain region, the LDD region and the first inversion layer formed sequentially from the surface of the semiconductor substrate on the side wall of the source / drain region below the sidewall spacer, and the LDD region and the first inversion layer below the gate electrode. A semiconductor device comprising the second inversion layer formed on the side wall can be manufactured.

In the semiconductor device of the present invention, when the inversion layers on the source region side and the drain region side are too close to each other and the concentration of the inversion layers is high, there is a concern about the inverse short channel effect. By forming the low-concentration second inversion layer on the LDD region below the gate electrode and on the side wall of the first inversion layer, and by forming the second inversion layer near the channel region, the reverse short channel effect can be suppressed.

By forming the high concentration first inversion layer below the LDD region, the short channel effect as in the related art can be sufficiently suppressed (the punch-through breakdown voltage is secured).
It has the advantage that. That is, according to the semiconductor device of the present invention, fluctuations (reverse short-channel effect, short-channel effect) of the characteristics of the semiconductor device, which are a concern when miniaturization advances, can be suppressed at the same time, and a semiconductor device with stable characteristics can be obtained. be able to.

[0030]

An embodiment will be described below with reference to FIGS. 1 (a) to 1 (h). First, an impurity for adjusting a Vth value was injected into a semiconductor substrate 2 provided with an element isolation region 1 and then oxidized to form a gate insulating film 3 of about 100 to 140 °.
Then, the polysilicon film 4 is formed on the gate insulating film 3 by Si.
Deposition was performed at about 1000 to 1500 ° with H ₄ gas.
Next, solid phase diffusion of phosphorus into the polysilicon film 4 (N ⁺ deposition)
(850 ° C., about 15 minutes). Thereafter, wet etching (HF clean) was performed to remove PSG attached to the polysilicon film 4 during solid phase diffusion. Furthermore, WSi5
Was deposited on the polysilicon film 4 to a thickness of 1000 to 2000 °. Thereafter, a resist is applied on WSi5,
A resist pattern 6 was formed by a photo method (see FIG. 1).
Next, the WSi5 / polysilicon film 4 is dry-etched using the resist pattern 6 as a mask to form a gate electrode 7.
Was formed (see FIG. 1B). Furthermore, after etching,
HF clean processing was performed for about 2 seconds. Further, the entire surface of the semiconductor substrate was oxidized at 900 ° C. for 10 minutes to form a 50 ° protective film (not shown).

Next, using the gate electrode 7 as a mask, low-concentration ion implantation is performed to form an LDD region 8 (NM).
³¹ P ⁺ , 30 Kev, 4.0 for OS transistor
5.0 × 10 ¹³ cm ⁻² , implantation angle 0 °, ⁴⁹ BF ₂ ⁺ , 30 KeV, 2.0-4.
0 × 10 ¹³ cm ⁻² , injection angle 0 °) (see FIG. 1C).

Next, as a measure for suppressing the short channel effect,
A high concentration first inversion layer 9a is formed below the LDD region 8 by an ion implantation method at a implantation angle of 0 ° and a large implantation amount (N
5. In the case of a MOS transistor, ¹¹ B ⁺ , 55 KeV,
0 to 8.0 × 10 ¹² cm ⁻² , ³¹ P ⁺ , 150 KeV, 1.0 to 1.5 × 10 ¹³ c for a PMOS transistor
m- ² ) (see FIG. 1 (d)). Note that the concentration of the first inversion layer 9a is suitably about 0.5 to 1.0 × 10 ¹⁸ cm ⁻³ .

Further, a low-concentration second inversion layer 9b is formed between the LDD region 8 and the channel region A by an ion implantation method at an implantation angle of 30 ° and a small amount ( ¹¹ B ^{+ in} the case of an NMOS transistor, 55 KeV, 3.0-4.0 × 10
¹² cm ^-2 , ³¹ P ^{+ for} PMOS transistor, 15
0 KeV, 5.0-7.5 × 10 ¹² cm ⁻² ) (FIG. 1)
(E)). The concentration of the second inversion layer 9b is 0.1 to
About 0.5 × 10 ¹⁸ cm ⁻³ was appropriate. Also, the second
Since the impurity for forming the inversion layer 9b was implanted at an implantation angle of 30 °, it was implanted near the center of the gate electrode 7 (near the channel region).

By the above steps, the first inversion layer 9a and the second inversion layer 9a
The inversion layer 9b has a gradual two-stage concentration profile toward the channel region A. Therefore, the reverse short channel effect, which is concerned when the inversion layers on the source region side and the drain region side are too close to each other due to further miniaturization, was suppressed, and a sufficient punch-through breakdown voltage could be secured. Next, in order to form the side wall spacer 11 on the side wall of the gate electrode 7, 2400-2
A 700 ° HTO film 10 was deposited (see FIG. 1 (f)).

Next, the entire surface of the HTO film 10 is dry-etched.
Gate electrode by etching and wet etching
7 side wall spacer 1 made of HTO
1 was formed (see FIG. 1 (g)). After this, the high concentration
On implantation is performed to form source / drain regions 12
As a result, a semiconductor device could be formed (NM
In case of OS transistor ⁷⁵As⁺, 40 KeV, 2.
0 to 4.0 × 10^Fifteencm^-2, Injection angle 7 °, PMOS tiger
For transistors⁴⁹BF_Two, 30 KeV, 1.0-3.
0x10^Fifteencm^-2, Injection angle 7 °) (see FIG. 1 (h)).

FIG. 2 is an enlarged view of the periphery of the gate electrode shown in FIG.

[0037]

According to the present invention, the short channel effect and the reverse short channel effect can be suppressed by dividing the inversion layer into two. In particular, when the inversion layers on the source region side and the drain region side are too close to each other and the impurity concentration of the inversion layer is high, there is a concern about the reverse short channel effect. However, by making the concentration of the inversion layer (second inversion layer) near the channel region low, the reverse short channel effect can be suppressed.

Further, by making the first inversion layer formed below the LDD region to have a high concentration, the short channel effect (deterioration of the punch-through breakdown voltage) can be suppressed. In other words, the reverse short channel effect can be suppressed by the low-concentration second inversion layer, and the short-channel effect can be suppressed by the high-concentration first inversion layer. Therefore, even if the semiconductor device is further miniaturized, it is stable. A semiconductor device having the characteristics described above can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is an enlarged view of a main part of the semiconductor device according to the first embodiment.

FIG. 3 is a schematic cross-sectional view of a manufacturing process of a conventional semiconductor device.

FIG. 4 is an enlarged view of a main part of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 element isolation region 2 semiconductor substrate 3 gate insulating film 4 polysilicon film 5 WSi 6 resist pattern 7 gate electrode 8 LDD region 9 inversion layer 9 a first inversion layer 9 b second inversion layer 10 HTO film 11 sidewall spacer 12 source / drain Area A Channel area

Claims (7)

[Claims] A step of forming an LDD region by ion-implanting an impurity of a first conductivity type on a semiconductor substrate on which a gate electrode is formed via a gate insulating film; and a step of forming an LDD region using the gate electrode as a mask. Forming a first inversion layer below the LDD region by ion-implanting a second impurity; and ion-implanting a second conductivity type impurity using the gate electrode as a mask to form a first inversion layer on the side of the LDD region on the gate electrode side. Forming a two-inversion layer, forming a sidewall spacer on the side wall of the gate electrode, and forming source / drain regions by ion implantation using the gate electrode and the sidewall spacer as a mask. A method for manufacturing a semiconductor device. 2. The method according to claim 1, wherein the first conductivity type is N-type, the second conductivity type is P-type,
Whether the obtained semiconductor device is an NMOS transistor,
2. The method according to claim 1, wherein the first conductivity type is P-type, the second conductivity type is N-type, and the obtained semiconductor device is a PMOS transistor. 3. The method according to claim 1, wherein the first inversion layer is used as a punch-through stopper. 4. The method according to claim 1, wherein the first inversion layer is formed by implanting a second conductivity type impurity into the semiconductor substrate in a direction perpendicular to the semiconductor substrate. 5. The method according to claim 1, wherein the second inversion layer is formed by injecting a second conductivity type impurity into the semiconductor substrate from an oblique direction. 6. The method according to claim 1, wherein the second inversion layer is formed by ion implantation with a smaller implantation amount than the first inversion layer. 7. A gate electrode formed on a semiconductor substrate via a gate insulating film, a sidewall spacer formed on a side wall of the gate electrode, and a semiconductor substrate below the sidewall spacer formed in a direction away from the gate electrode. LDD regions and first inversion layers formed sequentially from the surface of the semiconductor substrate on the side walls of the source / drain regions below the source / drain regions and the sidewall spacers, and are formed on the side walls of the LDD regions and the first inversion layers below the gate electrode. And a second inversion layer formed.