JP2000133615A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an increase in a leakage current in a transistor, a variation of the threshold voltage of the transistor and the like without impairing the uniformity of the film thickness of a block oxide film, by a method wherein prior to an impurity implantation, the block oxide film is formed while being heated. SOLUTION: A block oxide film 26 is formed on the whole surface of a wafer while being heated, and thereafter impurities are implanted in a source/ drain 24 and gates 23A and 23B. After that, a Ti silicide film is formed by the same way as a conventional way. In such manner, by implanting the impurities in the source/drain 24 and the gates 23A and 23B after the film 26 is formed, the impurities implanted in the gates 23A and 23B do not experience a thermal history at the time of the formation of the film 26. Owing to this, as the penetration through the film 26 due to a thermal diffusion of the impurities is not generated, a variation of the threshold voltage of a transistor formed on the wafer is little. Moreover, as the uniformity of the film thickness of the film 26 is never impaired, damage to the film 26, which can be generated in the manufacturing process of a semiconductor integrated circuit device, is little.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device having a process of implanting impurities into a substrate during a manufacturing process, and more particularly to a method of suppressing a short-channel effect and forming a threshold voltage of a transistor to be manufactured. The present invention relates to a method for manufacturing a semiconductor integrated circuit device capable of manufacturing a highly reliable semiconductor integrated circuit device with less variation in Vth and damage that may occur during a manufacturing process.

[0002]

2. Description of the Related Art In semiconductor integrated circuits, miniaturization of elements has been progressing for high speed and high integration. Also, fine CM
In OS (complementary metal oxide semiconductor), especially PMOSFET (p-channel MOS field effect)
In order to suppress the short channel effect of the transistor, a dual gate structure using a surface channel PMOSFET is widely used. The short channel effect is an increase in the leakage current of the transistor, a change in the threshold voltage, and the like.

In a semiconductor device, a salicide block process for providing a salicide portion and a non-salicide portion in order to reduce the resistance of a source / drain diffusion layer and a polysilicon gate is disclosed in Japanese Unexamined Patent Publication No. Hei 5-3173. Widely used in

FIGS. 1 to 5 show a dual gate structure of Ti.
Only the PMOS process portion of the conventional CMOS semiconductor integrated circuit manufacturing process in the salicide block is shown.

First, in FIG. 1, a channel region is formed by element isolation by a usual method. In the figure, the elements are separated by LOCOS5. After that, a gate electrode is formed, a low concentration impurity is added, and a sidewall 7 is formed. The substrate 1 has a low concentration of P ⁻ , as indicated by reference numeral 11.
LDD is formed. Reference numeral 3A denotes a portion formed of poly-Si (polysilicon) to be used as a gate electrode.

Next, as shown in FIG. 2, after forming a gate electrode, high-concentration impurities are implanted into the source / drain / gate. In the case of PMOS, for example, BF ₂ is 25
Inject KeV, about 3el5cm- ² . Then, as shown by oblique lines rising to the right in the figure, high-concentration P ⁺ gates (reference numerals 23A and 23B) and P ⁺ source / drain (reference numeral 24) are formed. Thereafter, RTA (rapid thermal anneal) is performed for activation. In addition,
In FIG. 2, the arrow indicated by the symbol A indicates boron implantation.

Next, as shown in FIG. 3, the HTO-CV
D (high temperature oxide-chemical vapor depositi
on) An oxide film 26 is formed on the entire surface of the wafer. And FIG.
As described above, the block oxide film 27 is formed only on the portion that does not salicide by lithography and etching.

Thereafter, as shown in FIG. 5, after pre-cleaning, Ti is deposited on the entire surface, and 600 to 80 in an inert atmosphere.
Anneal at 0 ° C. to selectively etch unreacted Ti. As a result, as indicated by reference numerals 33 and 34, Ti
Salicide (TiSi ₂ ) is formed.

According to such a series of methods, silicidation can be performed in a self-aligned manner only at a portion where salicidation is desired.

[0010]

However, in the above-described salicide block process having the dual gate structure, the P ^{+ is} reduced due to the thermal history (800 ° C. in the above example) when forming the block oxide film (HTO-CVD). Boron is thermally diffused from the gate to the channel, forming a PMOSFET (p-
The threshold voltage Vth of the channel MOS field effect transistor varies. The thermal diffusion is also called boron penetration.

On the other hand, a low-temperature oxide film (L
T0-CVD (low temperature oxide-chemical vapor
When deposition)) is used, penetration of boron can be suppressed. However, since uniformity of film thickness cannot be obtained,
There is a problem in that the amount of over-etching increases during the etching when forming the block oxide film, and the reliability of the gate oxide film of the transistor formed in the oxide film etching portion (salicide formation portion) is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. The present invention suppresses the short-channel effect, changes the threshold voltage Vth of a transistor to be formed, and
It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device which can manufacture a highly reliable semiconductor integrated circuit device with little damage that can occur during a manufacturing process.

[0013]

According to the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device having a process of implanting an impurity into a substrate in a manufacturing process, wherein a block oxide film is formed before the impurity implantation. This problem has been solved by performing the formation of the block oxide film while heating.

In the method of manufacturing a semiconductor integrated circuit device, the film may be formed by HTO-CVD to a thickness of about 300 angstroms while heating to about 800 ° C.
Is formed, the short channel effect is suppressed and the threshold voltage Vt of the transistor to be formed is reduced.
It is possible to obtain a well-balanced block oxide film with respect to the suppression of the fluctuation of h and the suppression of damage that may occur in the manufacturing process.

Hereinafter, the operation of the present invention will be briefly described.

FIG. 6 is a graph showing the relationship between the heating temperature when forming a block oxide film and the threshold voltage Vth of the transistor.

As shown in the graph, when the temperature during film formation exceeds about 700 ° C., the threshold voltage Vth changes, and as the temperature increases, the threshold voltage Vth changes.

In the present invention, impurities are implanted into the source / drain / gate after forming the block oxide film.
By doing so, the boron injected into the gate electrode becomes
It does not experience the thermal history when forming the block oxide film as described above. Therefore, boron does not penetrate.
In addition, since a high-temperature oxide film (HTO-CVD) can be used, the thickness of the oxide film is uniform, and a gate oxide film defect due to over-etching of the block oxide film does not occur.

FIG. 7 is a graph showing the relationship between the thickness of the block oxide film and the spread of the impurity when the impurity is diffused through the block oxide film.

In this graph, the characteristics after the ion implantation are shown by dashed lines. Further, the solid line shows the characteristics after the ion implantation and the heat treatment.

In this graph, it is assumed that a block oxide film is formed before boron is implanted into the gate.
Further, when boron ions are implanted into the substrate or the gate from above the formed block oxide film, the acceleration energy is adjusted so that the implantation depth (average range Rp) of boron is substantially the same. In this case, the relationship between the thickness of the block oxide film and the increase in the spread (ΔRp) of the implanted impurities is shown. When the film thickness increases, the spread of impurities increases due to collision and scattering by the block oxide film.

After ion implantation, to activate impurities,
Heat treatment is essential. In the case of high-concentration impurity implantation, enhanced diffusion occurs. In particular, in a region where the acceleration energy is small, the concentration gradient is large, and the spread due to thermal diffusion of the impurities becomes dominant. Such a large spread due to thermal diffusion
This is also shown by the solid line in FIG.

The block oxide film is removed by about 100 to 200 angstroms by pre-cleaning after Ti deposition. If an oxide film of about 100 Å or more exists on the Si substrate, the silicidation reaction of Ti can be suppressed. In a short channel transistor, it is desirable that the spread of the source / drain region is small. From these facts, it is considered that, for example, about 300 angstroms is optimal, as indicated by reference numeral L3 in FIG. 1 to 5
In the conventional example described above, the value is about 600 angstroms, as indicated by reference numeral L4.

In the dashed-dotted line graph of FIG. 7, the horizontal axis indicating the spread of the impurity is a value roughly calculated by 2ΔRp on one side, that is, 4ΔRp on both sides, centering on the average range Rp in the calculation formula.

As described above, according to the present invention, the short channel effect is suppressed, the fluctuation of the threshold voltage Vth of the transistor to be formed, and the damage that may occur during the manufacturing process are reduced.
A highly reliable semiconductor integrated circuit device can be manufactured.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1, 8, 9, 4, and 5 show the process steps in this order. In the manufacturing process of the semiconductor integrated circuit according to the embodiment to which the present invention is applied, the PMOS is used.
The process part is shown.

In this embodiment, the steps up to the formation of the gate electrode are performed by the above-described conventional process. The process up to the process shown in FIG.

After that, in the present embodiment, the processes of FIGS. 8 and 9 are performed in place of the conventional processes of FIGS. 2 and 3 described above. After that, the processes of FIGS. 4 and 5 are performed as in the related art.

That is, as shown in FIG. 8, a 300 Å HTO-CVD oxide film 26 is formed as a block oxide film on the entire surface of the wafer while heating to 800 ° C. Thereafter, as shown by an arrow A in FIG. 9, impurities are implanted into the source / drain / gate. In PMOS, BF ₂
Is implanted at about 35 KeV and 3 el5 cm ⁻² . In FIG. 9, for activation, RT of N ₂ at 900 ° C.
Perform A.

After that, as in the conventional case, as shown in FIG. 4, a block oxide film is formed by lithography and etching only on portions that are not to be salicidized. After that, as shown in FIG.
Is deposited on the entire surface, and by annealing and selective etching,
Form Ti salicide.

As described above, in the present embodiment, after the block oxide film is formed, the impurity is implanted into the source / drain / gate. Does not experience thermal history during film formation. For this reason, penetration does not occur due to thermal diffusion of boron. Therefore, a transistor with good characteristics can be obtained even with a short channel.

The high-temperature oxide film (HTO-CVD)
Since the film thickness uniformity is good, a gate oxide film defect due to over-etching of the block oxide film does not occur. 30
Since implantation is performed after forming an oxide film of about 0 Å, damage to a substrate or the like is small.

When the present invention is applied, the present invention can be realized without using a special process as in the above-described series of processes of the present embodiment. Therefore, not only is the application of the present invention easy, but also a highly reliable semiconductor integrated circuit is easily manufactured.

Further, by applying the present invention, it is possible to establish a salicide block process having a good dual gate structure, which is resistant to the short channel effect and has high reliability of the gate oxide film. Therefore, a semiconductor integrated circuit device with high reliability can be manufactured, in which the short-channel effect is suppressed, the variation of the threshold voltage Vth of the transistor to be manufactured, and the damage that may occur during the manufacturing process are small.

[0036]

According to the present invention, the short channel effect is suppressed and the threshold voltage Vth
And a highly reliable semiconductor integrated circuit device with less fluctuation and damage that may occur during the manufacturing process can be manufactured.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view showing a portion of a PMOS process in a conventional semiconductor integrated circuit manufacturing process in a dual-gate Ti salicide block.

FIG. 2 is a second sectional view showing a process following the above sectional view;

FIG. 3 is a third sectional view showing a process following the above sectional view;

FIG. 4 is a fourth sectional view showing a process following the above sectional view;

FIG. 5 is a fifth sectional view showing a process following the above sectional view;

FIG. 6 is a graph showing a relationship between a heating temperature when forming a block oxide film and a threshold voltage Vth of a transistor.

FIG. 7 is a graph showing the relationship between the thickness of a block oxide film and the spread of impurities when impurities are diffused through the block oxide film.

FIG. 8 is a first sectional view of a main part in a manufacturing process of a semiconductor integrated circuit according to an embodiment to which the present invention is applied;

FIG. 9 is a sectional view of a process following the above sectional view.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate 5 ... LOCOS 7 ... Side wall 3A, 3B ... Poly Si 11 ... P ^- LDD 23A, 23B ... P ⁺ gate 24 ... P ⁺ source / drain 26 ... HTO-CVD oxide film 27 ... Block oxide film 33, 34 ... Ti Salicide

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a process of injecting impurities into a substrate in a manufacturing process, wherein a film of a block oxide film is formed before the impurity is implanted and a film of the block oxide film is formed. A method for manufacturing a semiconductor integrated circuit device, wherein the method is performed while heating. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the film is formed by forming an HTO-CVD block oxide film to a thickness of about 300 Å while heating to about 800 ° C. A method for manufacturing a semiconductor integrated circuit device.