JPS62125071U - - Google Patents
Info
- Publication number
- JPS62125071U JPS62125071U JP43187U JP43187U JPS62125071U JP S62125071 U JPS62125071 U JP S62125071U JP 43187 U JP43187 U JP 43187U JP 43187 U JP43187 U JP 43187U JP S62125071 U JPS62125071 U JP S62125071U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- predetermined threshold
- noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図は本考案雑音消去回路の一実施例の等価
回路図、第２図ａ，ｂおよびｃは第１図に示す実
施例のそれぞれ入力端子３、回路内部点○イおよ
び出力端子１９におけるタイムチヤートである。
１…信号源、２…バイアス電圧源、３…入力端
子、４…エミツタ・ホロア用トランジスタ、５…
抵抗、６，７…比較器用トランジスタ、８…定電
流源、９…基準電圧源、１０…負荷抵抗、１１…
トランジスタ、１２…抵抗、１３，１４…抵抗、
１５…トランジスタ、１６…トランジスタ、１７
…電圧源、１８…電源、１９…出力端子、２０…
浮遊容量、２１…入力信号、２２…クランプ回路
なしの場合の回路内部点○イにおける雑音波形、
２３…クランプ回路なしの場合の出力端子１９に
おける雑音波形、２４…クランプ回路を設けた場
合の回路内部点○イにおける雑音波形、２５…ク
ランプ回路を設けた場合の出力端子１９における
雑音波形、○イ…回路内部点、ＶＡ…同期信号レ
ベル、ＶＢ…バイアス電圧、ＶＲ…電圧源９の電
圧、ＶＮ…雑音電圧、ＶＯ…雑音発生時の回路内
部点○イの電圧、ＶＢＥ…トランジスタのベース
・エミツタ間順方向電圧、ＶＣ…回路内部点○イ
の定常電圧。
FIG. 1 is an equivalent circuit diagram of one embodiment of the noise canceling circuit of the present invention, and FIGS. It is a time chart. DESCRIPTION OF SYMBOLS 1... Signal source, 2... Bias voltage source, 3... Input terminal, 4... Emitter follower transistor, 5...
Resistor, 6, 7... Comparator transistor, 8... Constant current source, 9... Reference voltage source, 10... Load resistance, 11...
Transistor, 12...Resistor, 13, 14...Resistor,
15...Transistor, 16...Transistor, 17
...voltage source, 18...power supply, 19...output terminal, 20...
Stray capacitance, 21... Input signal, 22... Noise waveform at point ○a inside the circuit when there is no clamp circuit,
23...Noise waveform at the output terminal 19 when there is no clamp circuit, 24...Noise waveform at the circuit internal point ○a when a clamp circuit is provided, 25...Noise waveform at the output terminal 19 when a clamp circuit is provided, ○ A...Circuit internal point, VA...Synchronizing signal level, VB...Bias voltage, VR...Voltage of voltage source 9, VN...Noise voltage, VO...Voltage at circuit internal point ○A when noise occurs, VBE...Transistor base Forward voltage between emitters, VC... Steady voltage at point ○a inside the circuit.
Claims (1)
検出する回路と、信号出力回路を有し、前記検出
回路の出力が所定しきい値に満たない場合には前
記信号出力回力は入力信号と等価な信号を出力し
、かつ前記検出回路の出力が所定しきい値を越え
る場合には前記信号出力回路は所定の直流電圧を
出力するか、あるいは前記入力信号にこれと逆相
の雑音消去信号を加え合せた信号を出力する雑音
消去回路において、前記検出回路の出力が所定し
きい値に満たない場合に、前記検出回路の出力端
に前記所定しきい値に満たないがこれに近い一定
電圧にクランプするトランジスタを接続し、前記
信号出力回路の出力端にかかる信号出力回路の出
力電圧のうち雑音以外の信号のとりうる最大値よ
り大きいがこれに近い一定電圧にクランプするク
ランプ回路を接続することにより雑音消去動作の
動作速度の向上を計つたことを特徴とする雑音消
去回路。 It has a circuit for detecting noise of a predetermined level or higher contained in an input signal, and a signal output circuit, and when the output of the detection circuit is less than a predetermined threshold, the signal output power is equivalent to the input signal. When outputting a signal and the output of the detection circuit exceeds a predetermined threshold, the signal output circuit outputs a predetermined DC voltage or adds a noise canceling signal having the opposite phase to the input signal. In a noise canceling circuit that outputs a combined signal, when the output of the detection circuit is less than a predetermined threshold, the output terminal of the detection circuit is clamped to a constant voltage that is less than but close to the predetermined threshold. By connecting a transistor to the output terminal of the signal output circuit, and connecting a clamp circuit that clamps the output voltage of the signal output circuit applied to the output terminal of the signal output circuit to a constant voltage that is larger than, but close to, the maximum value that a signal other than noise can take. A noise canceling circuit characterized by improving the operating speed of noise canceling operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987000431U JPS6345096Y2 (en) | 1987-01-05 | 1987-01-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987000431U JPS6345096Y2 (en) | 1987-01-05 | 1987-01-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62125071U true JPS62125071U (en) | 1987-08-08 |
| JPS6345096Y2 JPS6345096Y2 (en) | 1988-11-22 |
Family
ID=30777400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987000431U Expired JPS6345096Y2 (en) | 1987-01-05 | 1987-01-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6345096Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5722464A (en) * | 1980-07-14 | 1982-02-05 | Sugino Mach:Kk | High pressure fluid sealing apparatus |
-
1987
- 1987-01-05 JP JP1987000431U patent/JPS6345096Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5722464A (en) * | 1980-07-14 | 1982-02-05 | Sugino Mach:Kk | High pressure fluid sealing apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6345096Y2 (en) | 1988-11-22 |