JPS62119631A - High speed arithmetic unit - Google Patents

Abstract

PURPOSE:To attain high speed operation by using a data in two internal registers so as to execute a repetitive operation. CONSTITUTION:A data in an internal register A section 1 is read at an A address 8, the data passes through a latch section 3A and is sent to a data source selection section 4A. The data source selection section 4A selects a sent data, transfers it to an ALU section 5, a data in an internal register B section 2 is read by a B address 9, the data passes through a latch section 3B and is sent to a data source selection section 4B. The sent data is selected and sent to the ALU section 5, the sent data is used for operation, and the result of operation selects only the internal register B section 2 only at a changeover section 13 receiving a microinstruction 12 and a write enable 14 and the result is written only in the internal register B section 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed arithmetic device that uses data in two internal registers to perform repetitive arithmetic operations at high speed.

[Conventional technology]

Figure 2 shows, for example, [Vivolar microprocessor]
Logic and Interface (Bipolar
Microprocessor l, logic an
d Interface), 1, and Lanced Micro Davises Inc.
ro De-Vices, 1nc) Published in 1983.

FIG. 5 is a block diagram of the 32-bit microprocessor shown in Section 5-5.

In the figure, 1 is the (first) internal register A section that stores 32-bit data, 2 is the (second) internal register 8 section that stores 32-bit data, and 3A and 3B are the internal registers. 4A and 4B are data source selection units that select external input data and output data of the launch units 3A and 3B; 5 is an ALTJ ( 'l logic unit 1) part, 6 is a shifter part that shifts the calculation result, 7 is the calculation result output data line, 8 is the A address, 9
is the B address, 10 is the internal register A section 1゜8 section 2
11 is a clock.

Next, the operation will be explained.

First, when A address 8 is set from A address 5 to B address 8, data in internal register A section 1 is read out. The read data is sent to the data source selection section 4A through the launch section 3A. The data source selection section 4A selects the sent data and sends it to the ALU section 5. Next, when the B address 9 is set, the data in the internal register 8 section 2 is read out. Subsequently, the read data passes through the launch section 3B and is sent to the data source selection section 4B.

The data source selection section 4B selects the sent data and sends it to the ALU section 5.

Next, the ALU unit 5 calculates the two data sent. The calculated result passes through the shifter part 6 and is stored in the internal register A at the B address 8 generated by the address generator 9.
section 1 and internal register 8 is written to a register in section 2.

[Problem that the invention seeks to solve]

Since the conventional arithmetic unit is configured as described above, it executes arithmetic operations using the data in the first and second two internal registers A and 8, and stores the results in the two internal registers A at address B. , because the data is written to part B, when a repeated operation is executed, the A address specified in part A of one internal register must be switched to the B address within one cycle, and therefore it takes 71゛ to switch. This method requires delay time and has problems such as the inability to perform repetitive operations at high speed.

This invention was made to solve the above-mentioned problems. It executes an operation on the data read from two internal registers A section and B section, and stores the operation result in one internal register A section at the B address. It is an object of the present invention to provide a high-speed arithmetic device that can write only to the other 8 parts of internal registers while preventing writing to the internal registers.

[Means for solving problems]

A high-speed arithmetic device according to the present invention is configured to execute repetitive arithmetic operations at high speed using data in two internal registers A and B, and the first and second two internal registers are An operation is executed using the data in sections A and B, and the operation result is written only to section 8 of the internal register by specifying the B address, and when the operation is executed repeatedly, the data in section A of the internal register is used. Therefore, a delay time for determining the A address within one cycle is not required.

[Effect]

The high-speed arithmetic device in this invention is a microinstrument I.
The write address switching operation is executed by the
The data read from the internal register A part and the internal register 8 part are operated, and the result of the calculation is written only to the internal register 8 part by specifying the B address.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In the figure, the same parts as in Figure 2 are designated by the same reference numerals.
In the figure, 12 is a microinstruction, 13
Reference numeral 14 indicates a write enable for writing to only the internal register 8 section 2 what is to be written to the internal register A section 1 and the internal register 8 section 2 in accordance with the designation of the B address 9.

Next, the operation will be explained.

First, data in internal register A part 1 is read at A address 8. The read data passes through the launch section 3A,
The data is sent to the data source selection section 4A.

The data source selection section 4A selects the sent data and transfers it to the ALU section 5. Next, the data in the internal register 8 section 2 is read out at the B address 9.

Then, the read data passes through the launch section 3B and is sent to the data source selection section 4B. The data source selection section 4B selects the sent data and sends it to the ALU section 5. The ALU units 5 perform calculations using the data sent to each other. The result of the calculation is sent to the switching unit 13 into which the microinstruction 12 and write enable 14 are input.
By selecting only the internal register 8 section 2 in , the data is written only to the internal register 8 section 2.

〔Effect of the invention〕

As described above, according to the present invention, an arithmetic device is configured by adding a switching section that can write the result of an operation using a microinstruction into only one of the two internal registers A and B, internal register B. Therefore, when performing repeated operations using data in internal register A and internal register B, there is no delay time for determining the address within one cycle of one internal register A. , which has the effect of allowing repeated operations to be executed at high speed.

[Brief explanation of drawings]

FIG. 1 shows a program 1 of a high-speed arithmetic device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a conventional arithmetic device. In the figure, ■ is the internal register A section, 2 is the internal register 8 section, 3A and 3B are the launch section, 4A and 4B are the data source selection section, 5 is the ALU (arithmetic operation unit) section,
10 is an address generation section, 12 is a microinstruction, and 13 is a switching section. Procedural amendment (voluntary) Audience

Claims (1)

[Claims] In an arithmetic device that executes continuous operations by an arithmetic logic unit using data stored in first and second internal register sections, the first and second internal registers A;
A switching unit is provided for an address generation unit that specifies one of the internal registers B, and a switching unit is provided that allows the arithmetic operation result in the arithmetic operation unit unit to be written only to the internal register B unit using a 1-bit microinstruction, and the internal register A unit A high-speed arithmetic device characterized in that arithmetic processing is repeatedly performed using the data in the internal register B section.