JPS62118640A - Synthesizer power save circuit - Google Patents

Abstract

PURPOSE:To minimize the power consumption of a synthesizer at standby by using a power save control circuit so as to interrupt the input of both frequency dividers at the standby, interrupting the power supply of a prescaler counter and inhibiting its input. CONSTITUTION:A reference frequency inhibiting circuit 25 is provided to the input of a reference frequency divider 21 constituting a synthesizer control circuit 2, an input signal inhibition circuit 27 is provided to the input of a programmable frequency divider 24, phase comparison changeover circuits 26, 28 are provided to the input of a phase comparator 22, a power switch 8 and an input inhibition circuit 9 are provided to the input of a prescaler counter 6 and a power saving phase comparator 29 is provided between the changeover circuits 26, 28 and the prescaler counter input inhibition circuit 9 respectively, and they are controlled by a power save control circuit 20. The power save control circuit 20 interrupts the input to both the frequency dividers at the standby and interrupts the power supply of the prescaler counter and inhibits the input, then no current flows to the prescaler counter 8 and the power consumption of the synthesizer is minimized.

Description

[Detailed Description of the Invention] [Summary] This is a synthesizer power saving circuit that minimizes the power consumption of the synthesizer during standby mode.

[Industrial application field]

The present invention relates to a synthesizer power saving circuit.

Generally, a synthesizer is a device that generates signals at a large number of accurate frequencies over a wide frequency range based on the output of an oscillator by using techniques such as frequency multiplication and division by two, and mixed two-phase synchronization.

It is widely used in the field of communication equipment as a local oscillator in mobile radios with multi-channel switching functions and television receivers with electronic tuning functions.

Methods for realizing this include a method of performing frequency synthesis in a feedforward format using frequency multiplication/dividing by 2 and mixing, and a method of using a feedback type PLL (phase locked loop). As LSI technology progresses and it becomes easier to realize high-speed variable frequency dividers, the latter method is widely used, and the present invention is also applied to PLL-type synthesizers.

The present invention particularly relates to a power saving circuit for a synthesizer used as a local oscillator common to a transmitting section and a receiving section of a mobile phone.

[Conventional technology]

As shown in FIG. 4, a conventional synthesizer includes a reference oscillator l°, a synthesizer control circuit 2'', and a loop filter 3.
', a voltage controlled oscillator 4', a buffer 5', and a prescaler counter 6', and the synthesizer control circuit 2' further includes a reference frequency divider 21' and a phase comparator 2.
2'', a charge pump 23'', and a programmable frequency divider 24''.

In the above configuration, the prescaler counter 6'' plays a role of taking on a part of the frequency dividing function since the programmable frequency divider 24'' has a limit in its frequency dividing function.

If the prescaler counter 6° is fixed, the reference frequency may become low, so it is of a two-modular type that can perform two variable continuous frequency divisions. By alternately switching this, a predetermined center frequency, for example 30 (k
Hz).

[Problem that the invention seeks to solve]

However, the input of the prescaler counter 6' is 8.
Since the frequency of 00 (MHz) must be divided, E CL (Emitter Couple Lo
gic). However, since ECL is a circuit that operates with active elements, the synthesizer control circuit 2
The power consumption is extremely large at 30 [ugly^] compared to the power consumption of 5 to 10 (n+A).

For example, in the case of a car phone, the average standby time is 8 hours, but the talk time is 0.5 hours. This causes increased power consumption.

[Means for solving problems]

An object of the present invention is to solve the above problems and to minimize power consumption of a synthesizer during standby.

As shown in FIG. 1, this means includes a reference frequency prohibition circuit 25 on the input side of the reference frequency divider 210 constituting the synthesizer control circuit 2, an input signal prohibition circuit 27 on the input side of the programmable frequency divider 24, Phase comparison switching circuits 26 and 28 are provided on the input side of the phase comparator 220, and a power switch 8 and an input prohibition circuit 9 are provided on the input side of the prescaler counter 6.
A power saving phase comparator 29. are provided respectively, and these are to be controlled by the power save control circuit 20.

[For production]

According to the present invention, during standby, the power save control circuit 20
As a result, the inputs of both frequency dividers are cut off, the power supply of the prescaler counter is cut off, and its input is also prohibited, so that no current flows through the prescaler counter 6, and therefore, the power consumption of the synthesizer is also minimized.

〔Example〕

Hereinafter, the present invention will be explained by way of examples with reference to the accompanying drawings.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

The device shown in FIG. 2 includes a synthesizer control circuit 2 operated by a reference oscillator 1, a loop filter 3, a voltage controlled oscillator 4, a buffer 5, and a prescaler counter input inhibit circuit 9.
and a prescaler counter 6 are connected in a loop, and a power switch 8 is inserted between the power supply stabilizing circuit 7 and the prescaler counter 6.

Further, the synthesizer control circuit 2 includes a reference frequency divider 21
Inhibition circuits 25 and 27 are provided on the input side of the programmable frequency divider 24, respectively, and phase comparison switching circuits 26 and 28 are provided on the input side of the phase comparator 22, respectively.

On the other hand, a power saving phase comparison section 29 is provided between the phase comparison switching circuits 26 and 28 and the prescaler counter manual power inhibition circuit 9.

This power-saving phase comparator 29 is designed to avoid the phase difference between the reference frequency of the phase comparator 22 and the frequency to be compared when restarting the prescaler counter 6 during standby. be. The comparator 29 includes a power saving phase comparator 291, a lead/lag determining circuit 292, a polarity inversion circuit 293, and a power saving charge pump 294.

The power save control circuit 20 is a circuit that receives a call or standby signal and controls each of the above components.

Hereinafter, the operation of the circuit shown in FIG. 2 having the above configuration will be explained based on FIG. 3.

When the signal input to the power save control circuit 20 is in the talking state, the control circuit 20 closes the switch of the prohibition circuit 2527 and the power switch 8, and also closes the switch of the switching circuit 26,
Switch No. 28 as shown by the normal solid line.

Therefore, the power saving phase comparator 29 does not work at all and performs normal PLL operation (Fig. 3(A)(B)(C)
)(D)).

At time t=t1, when the standby state is entered (Fig. 3 (A)
), the power save control circuit 20 is a dual prohibition circuit 25 j2
7 is opened, and the power switch 8 is opened at t=t2.
Open ((Figure 3 (B) (C)).

When the switch 8 is opened, the inhibit circuit 9 also stops working, so the operation of the prescaler counter 6 is completely stopped.

Next, when restarting the prescaler counter 6, t
At =t3, the power save control circuit 20 turns on the power switch 8 (FIG. 3(C)).

When the switch 8 is turned on, the prescaler counter 6 starts counting from t=t3 and starts the frequency dividing function. At t=t4 after the start of counting, the power save control circuit 20 closes the switch of the prohibition circuit 25j27 (FIG. 3(B)) and also switches the switching circuits 26 and 28 to the power save phase comparison mode as shown by the broken line. 29 (FIG. 3(D)).

As a result, the power saving phase comparator 29102, the manually powered phase is advanced/delayed judgment circuit 292, and the polarity inversion circuit 293
The output of the power saving charge pump 294 (Fig. 3 (E
)(F)) is manually applied to the inverting input terminal of the input inhibiting circuit 9, and the lead or lag is removed.

When the phases match, at t=t5, switching circuit 2
6, 28 as shown in the solid line (Fig. 3 (D)
), by opening the switches of the inhibition circuits 25 and 27 at t=ta (FIG. 3(B)), and by opening the power switch 8 at t=ty (FIG. 3(C)),
The operation of the prescaler counter 6 is stopped again.

〔Effect of the invention〕

As described above, according to the present invention, during standby, the power save control circuit 20 cuts off the human power of both frequency dividers, and also cuts off the power to the prescaler counter and prohibits its input. No current flows through it, so the power consumption of the synthesizer is also minimized.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of the present invention, and FIG. 4 is an explanatory diagram of the prior art. 1... Reference oscillator, 2... Synthesizer control circuit, 3... Loop filter, 4... Voltage controlled oscillator, 5°1 buffer, 6... Prescaler counter, 7... Power supply stabilization circuit , 8... Prescaler counter power switch, 9...
Prescaler counter input prohibition circuit, 20... Power save control circuit, 21... Reference frequency divider, 22... Phase comparator, 23... Charge pump, 24... Programmable frequency divider, 25 ... Reference frequency prohibition circuit, 26 ... Phase comparison switching circuit, 27 ... Programmable frequency divider input signal prohibition circuit, 2
8... Phase comparison switching circuit, 29... Phase comparator for power saving, 291... Phase comparator for power saving, 292... Lead/lag judgment circuit, 293... Polarity inversion circuit, 294.・Charge pump for power saving.

Claims (1)

[Claims] A synthesizer power saver in which a synthesizer control circuit consisting of a reference oscillator, reference frequency divider, phase comparator, charge pump, and programmable frequency divider is connected in a loop with a loop filter, voltage controlled oscillator, buffer, and prescaler counter. The circuit includes a reference frequency prohibition circuit on the input side of the reference frequency divider, an input signal prohibition circuit on the input side of the programmable frequency divider, a phase comparison switching circuit on the input side of the phase comparator, and the prescaler. A power switch and a prescaler counter input prohibition circuit are provided on the input side of the counter, and a power saving phase comparison section is provided between the phase comparison switching circuit and the prescaler counter input prohibition circuit, and these are controlled by a power save control circuit, A synthesizer power save circuit characterized by intermittent operation.