JPH02291161A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enhance a purity of an output signal of a PLL synthesizer circuit by a method wherein a PLL control part and a voltage control oscillator are installed on a chip substrate so as to be separated in positions which are not faced in parallel and an isolation region is formed around the voltage control oscillator. CONSTITUTION:A PLL synthesizer circuit of a BiCMOS constitution is formed in a rectangular chip 1; a PLL operation part 2 constituted of a CMOS logic circuit is formed in one corner part; a prescaler 3 of an ECL constitution by a bipolar transistor is formed so as to be adjacent to one side of the PLL operation part 2. A phase comparator 4 of a CMOS constitution and a charging pump 5 of a bipolar constitution are formed so as to be adjacent to the other side of the PLL operation part 2. A VCO(voltage control oscillator) 6 of a bipolar constitution is formed in a diagonal position of the PLL operation part 2 inside the chip 1; an LPF(low-pass filter) 7 constituted as an external circuit is connected between the VCO 6 and the charging pump 5. A P-type layer is formed as an isolation region 8 around the VCO 6.

Description

[Detailed description of the invention] This relates to semiconductor integrated circuits housed in .

2. Description of the Related Art In recent years, electronic circuits of communication devices such as car telephones have been increasingly integrated into ICs in order to achieve miniaturization and lower power consumption. In such communication equipment, even the tuning circuit, which is behind the curve in terms of IC, is required to be smaller and consume less power.

[Conventional technology 1 Conventionally, a PLL that forms part of a tuned circuit of a car phone, etc.
The synthesizer circuit consists of a PLL control section that processes digital signals using a CMOS logic circuit that is advantageous for low power consumption and high integration, and a voltage-controlled oscillator (hereinafter referred to as CO) and a brisscaler that are configured using bi-directional circuits that are advantageous for high-speed operation. It has been proposed that the circuit be made up of circuits using Bora transistors and housed in a single chip using a Bi CMOS structure to achieve miniaturization and low power consumption.

[Problems to be Solved by the Invention] However, in the PLL synthesizer circuit as described above, the PLL synthesizer circuit that processes digital signals is difficult to solve. Since the CO, which is made up of a control section and an analog circuit, is placed in close contact with each other within one chip, digital noise generated from the I)LL control section mixes into the output signal of the CO. That is,
For example, the PLL control section is 'T''f' I- of 5■
A large number of CMOS's turn on and off depending on the level and output digital signals, and the CO operates analogously using voltage signals between 0 and 5V. If the circuit wiring constituting the PLL control section and the circuit wiring composing the VCO are patterned adjacent to each other in parallel, a capacitance component will occur between the two wirings, and due to the mutual induction effect due to the capacitance component, V
The digital signal in the P I-L7 control section mixes into the CO as noise.

On the other hand, in the Bi CMOS elliptical chip as mentioned above, N
Each element is formed on the N-type epitaxial layer, and a power supply voltage is applied to the N-type epitaxial layer to reach the Vcc level. Further, in the vCO formed by a large number of bibolar 1 transistors, an isolation region is formed at the boundary between each transistor, dividing an N-type epitaxial layer by a P-type layer. Then, when the power supply @JEVcc fluctuates in a pulse-like manner based on the on/off operation of many CMOS in the control section of P L1, the pulse component is transmitted to the N-type epitaxial layer in the CO region, and its Due to the capacitive coupling between the N-type epitaxial layer and the P-type isolation region, noise is transmitted to each transistor, and the noise is mixed into the output of the VCO.

As mentioned above, if noise is mixed into the output signal of the ■CO through the capacitance component generated between the circuit wiring and the power supply, for example, the output signal of the VCO will be PL, L. ．． When the operating frequency of the control unit is 5KHz, the peak noise P at a frequency of 800MHz±5KHz as shown in Figure 5.
occurs and the signal purity decreases.6 And, such peak noise P remains 5K even after FM demodulation. There is a problem in that it is output as a Hz noise signal and interferes with the audio signal.

The object of the present invention is to provide a structure in which P]. ．．
The object of the present invention is to improve the output signal purity of a concave PLL synthesizer in which an i control section and a CO are integrated into one chip.

"Means for Solving the Problems" FIG. 1 is a diagram explaining the principle of this invention. That is, Pl. outputs a digital signal. ．． ．． an L control section 12, a voltage controlled oscillator 6 to which an analog voltage value formed based on the output signal of the PLI control section 12 is input and outputs a signal having a frequency based on the analog voltage value; A prescaler 3 that frequency-divides the output signal of PLL 6 and outputs it to the PLL control section 12 is housed in the same chip 1.
It constitutes the main part of the LL synthesizer circuit. On the chip 1 substrate, the PLL control section 12 and the voltage controlled oscillator 6 are provided in parallel and separated from each other in positions that do not face each other, and a separation region 8 is formed around the voltage controlled oscillator 6.

"Function" P L I, control unit 1 due to the fact that the circuit wiring of P L I., control unit 12 and electric control oscillator 6 are adjacent in parallel.
2 (》) is prevented from entering the voltage controlled oscillator 6, and the separation region 8 prevents noise from entering the voltage controlled oscillator 6 from the PLL and control section 12 through the bulk layer of the chip 1. .

[Example] Hereinafter, an example that embodies the present invention will be described with reference to FIGS. 2 to 4.

As shown in FIG. 2, the rectangular chip 1 has )li
A CMOS PLL synthesizer circuit is formed, and a PLL operation section 2 consisting of a CMOS logic circuit is formed at one corner of the PLL synthesizer circuit. ．． , one rescaler 3 having a configuration is formed. F) LL A phase comparator 4 having a CMOS configuration and a charge pump 5 having a bipolar configuration are also formed adjacent to the other side of the L calculation unit 2.

In the chip 1, a bibolar elliptical VCO 6 is formed at a diagonal position of the P L,L calculation unit 2, and the VCO 6
An external device 7 is connected between the charge pump 5 and the charge pump 5. A P-type layer is formed around the VCO 6 as an isolation region 8 . As shown in FIG. 3, the isolation region 8 is formed to a depth that penetrates an N-type buried layer 10 formed under the N-type epitaxial layer 9.

The electrical configuration of the above-mentioned PLL synthesizer circuit will be explained with reference to FIG. 4. A clock signal CK, frequency data DA and strobe signal STB are input from an external circuit to the PLL and arithmetic unit 2, and frequency data DA is input. When the strobe signal STB is input in this state, the frequency data is calculated based on the clock signal CK.
written to.

Then, the PLL calculation unit 2 divides the frequency data DA based on the reference frequency of the crystal oscillator 11 and generates the setting signal f.
output r to the phase comparator 4.

Also, P.L. 1. The output signal of the grease scaler 3 is inputted to the calculation section 2, and the PLL calculation section 2 divides the frequency of the output signal of the grease scaler 3 and outputs it to the phase comparator 4 as a feedback signal fp.

The phase comparator 4 generates a pulse signal φr according to the frequency and phase difference between the two signals based on the setting signal fr and the return signal fD.
, φp to the charge pump 5, and the charge pump 5
outputs an output signal to the LPF 7 according to the frequency and phase difference of the pulse signal φ', φρ. The output signal is a DC signal containing a pulse component, and the DC component fluctuates with the frequency of the pulse signals φ' and φp, and the pulse component fluctuates with the phase difference between the pulse signals φr and φD.

■, P F 7 smoothes the output signal of the charge pump 5 and removes the pulse component, and outputs the output signal to the VCO 6;
The VCO 6 outputs an output signal with a frequency corresponding to the voltage value of the output signal of the LPF 7. Then, the output signal of the VCO 6 is frequency-divided by the Briscaler 3 and sent to the PLL,
The signal is fed back to the calculation unit 2, further frequency-divided by the PLL calculation unit 2, and outputted to the phase comparator 4 as the feedback signal fρ.

Now, in the PLI-synthesizer circuit configured as described above, the PLL operation section 2 of CMOS configuration, the phase comparator 4, and the VCO 6 configured of an analog circuit using bibolar transistors are located apart. That is,
Since the PLL calculation unit 2 and the VCO 6 are formed diagonally on the chip 1, the circuit wiring forming the PLL calculation unit 2 and the circuit wiring forming the VCO 6 are adjacent to each other in parallel. Wiring ceases to exist. Further, a charge pump 5 is interposed between the phase comparator 4 and the VCO 6, so that they are not adjacent to each other.

Therefore, F) LI, calculation unit 2 and phase comparator 4 and ■
Since the generation of a capacitance component between the circuit wiring and the CO 6 is prevented, noise based on the digital operation of the PLL, the arithmetic unit 2 and the phase comparator 4 is prevented from being mixed into the VCO 6.

Further, VCO 6 is surrounded by M head area 8, and VCO 6 is surrounded by M head area 8.
Capacitive coupling between the CO6 internal circuit and the external N-type epitaxial layer 9 is completely cut off. Therefore, noise based on power fluctuations of the PLL calculation section 2 or the phase comparator 4 is not transmitted to the VCO 6 via the N-type epitaxial layer.

As a result, noise based on the digital operation of the PLL calculation section 2 and the phase comparator 4 is prevented from being mixed into the output of the VCO 6, so that the purity of the output signal of the VCO 6 can be improved. [Effects of the Invention] As described in detail above, the present invention is a P I-L control unit and a CO integrated into one chip by Bi CMOS elliptical formation.
It exhibits an excellent effect of improving the output signal purity of the I=L synthesizer circuit.

In the figure, 1 is a chip, 3 is Brisquera, 6 is a voltage controlled oscillator; 8 is the minute-resistant area, 12 is a PLL control section.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of this invention, and Fig. 2 is a diagram illustrating the principle of this invention. Circuit layout diagram of the synthesizer circuit, Figure 3 shows ■CO that constitutes the PLL synthesizer circuit.
A cross-sectional view showing the surrounding separation area, FIG. l=Block diagram of synthesizer circuit, FIG. 5 is a frequency characteristic diagram of the conventional ■CO. Figure 3: Cross section showing the separation region of CO Figure 4: Block diagram of PLL shift synthesizer circuit Figure 5: Conventional vCO Frequency characteristic diagram MHz MHz MHz

Claims (1)

[Claims] 1. A PLL control section (12) that outputs a digital signal;
a voltage controlled oscillator (6) to which an analog voltage value formed based on the output signal of the PLL control section (12) is input and outputs a signal having a frequency based on the analog voltage value; and the voltage controlled oscillator (6). This is a semiconductor integrated circuit in which a prescaler (3) that frequency-divides an output signal and outputs it to a PLL control section (12) is housed in the same chip (1).
) The PLL control unit (12) and the voltage controlled oscillator (6) are provided at positions separated from each other in parallel on the substrate,
A semiconductor integrated circuit characterized in that an isolation region (8) is formed around a voltage controlled oscillator (6).