JPH0645983A - Cordless phone circuit - Google Patents

Abstract

PURPOSE:To reduce a power consumption by interrupting a pre-scaler control signal in an H level, and stopping the supply of currents to a pre-scaler circuit by a gate circuit while a receiving operation is stopped by an intermittent receiving operation. CONSTITUTION:In a slave device, at the time of a waiting state, the pre-scaler control signal is switched to an H level in each period of a reference oscillation frequency while the oscillation of a VCO circuit 1 is operated, supplied through an AND circuit 7 to a pre-scaler circuit PSC 2, and an PLL operation is executed by repeatedly switching a frequency rate. And also, while the oscillation of the VCO circuit 1 is stopped, an intermittent receiving operation signal from a CPU 6 is turned to an L level, the output level of the AND circuit 7 is also turned to the L level, and the currents can be prevented from flowing into the PSC circuit 2. Thus, the power consumption can be reduced at the time of waiting while the receiving operation is stopped in the intermittent receiving operation, and the consumption of a battery can be reduced.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION The present invention relates to pulse swallows.
The present invention relates to a cordless phone circuit that includes a receiving circuit using a PLL [Phase Locked Loop] circuit of a swallow method and that intermittently operates the receiving circuit during standby.

2. Description of the Related Art A PLL circuit divides an oscillation signal of a VCO circuit (voltage controlled oscillator) by a programmable frequency divider, and compares the divided signal with a reference oscillation signal in phase.
By feeding back the result to the VCO circuit again, an arbitrary oscillation frequency can be obtained stepwise based on the reference oscillation frequency. However, this PL
When the L circuit is used as the local oscillation circuit of the cordless phone, the oscillation frequency of the VCO circuit is high, so it is not realistic to use a high-speed and expensive programmable frequency divider that follows the oscillation frequency. This problem can be avoided by using a fixed frequency division method in which the oscillation frequency of this VCO circuit is once lowered to an appropriate frequency by a high-speed prescaler circuit whose frequency division ratio is fixed and then input to a programmable frequency divider. However, in this fixed frequency division method, if the setting of the frequency division ratio of the programmable frequency divider is changed by one step, the total frequency division ratio changes by the frequency division ratio of the prescaler circuit, so the reference oscillation frequency is set to this prescaler circuit. The frequency has to be lowered by the frequency division ratio of ∘, which causes the period of phase comparison to be lengthened, and noise due to fluctuations in the oscillation frequency of the VCO circuit is reduced to the voice frequency band of the cordless phone. Therefore, a pulse swallow type PLL circuit has been conventionally used as a local oscillation circuit of a cordless phone. FIG. 4 shows a conventional pulse swallow type PLL circuit used in a local oscillation circuit of a receiving circuit of a cordless phone. In this PLL circuit, the oscillation signal of the VCO circuit 1 is input to the frequency division phase comparison circuit 3 via the prescaler circuit 2. Prescaler circuit 2 is VC
This is a frequency dividing circuit that divides the oscillation signal of the O circuit 1 and sends it to the oscillation signal input terminal PIR of the frequency dividing phase comparing circuit 3, whereby the oscillation frequency of the VCO circuit 1 is programmable by the frequency dividing phase comparing circuit 3. The frequency can be low enough that the instrument can follow. However, this prescaler circuit 2
Unlike the prescaler circuit of the fixed frequency division system, the prescaler control signal from the prescaler control signal output terminal PCR of the frequency division phase comparison circuit 3 can switch the frequency division ratio in two stages. The frequency division phase comparison circuit 3
A PLL IC composed of a programmable frequency divider and a phase comparator, which divides a signal from the prescaler circuit 2 by a frequency division ratio set in the programmable frequency divider, and a reference oscillation signal by the phase comparator. The phase difference signal is output from the phase difference signal output terminal PDR as a phase difference signal. However, when a frequency division ratio of a certain value is set, this programmable frequency divider counts the quotient and the remainder [modulo] when this value is divided by the specified radix, and the remainder counting ends. Sometimes, the prescaler control signal output from the prescaler control signal output terminal PCR is changed to switch the frequency division ratio of the prescaler circuit 2. Therefore, the total division ratio of the prescaler circuit 2 and the programmable frequency divider can be arbitrarily changed step by step, so that it is necessary to lower the reference oscillation frequency as in the fixed frequency division method. Disappear. Note that this reference oscillation frequency is the frequency division phase comparison circuit 3
It is obtained by dividing the oscillation frequency of the crystal oscillator 4 externally attached to the. The phase difference signal output from the phase difference signal output terminal PDR of the frequency division phase comparison circuit 3 is fed back to the VCO circuit 1 via the low pass filter 5. Then, the VCO circuit 1 can accurately oscillate at a stepwise arbitrary frequency for each reference oscillation frequency by controlling the oscillation frequency based on the phase difference signal. Therefore, in the receiving circuit of the cordless phone circuit, by mixing the oscillation signal of the VCO circuit 1 with the reception signal as the local oscillation signal of the PLL circuit, the signal of any channel can be converted into the intermediate frequency signal. . In addition, a cordless phone slave unit driven by a battery does not constantly operate the reception circuit in order to reduce the consumption of the battery during standby, as shown in FIG. 3, for example, a reception operation is performed for 60 msec. 15 after having done
Intermittent operation such as stopping the receiving operation for 00 msec is performed. Therefore, as shown in FIG. 4, the CPU 6 that controls the cordless phone slave unit.
Sends an intermittent reception operation signal that is intermittently at H level as shown in FIG. 3 to the VCO circuit 1 of the PLL circuit, and causes the VCO circuit 1 to oscillate only when the intermittent reception operation signal is at H level. I am making it. The frequency division / phase comparison circuit 3 divides the oscillation frequency of the crystal oscillator 4 and outputs a clock signal from the clock output terminal CLK to the outside. Then, the CPU 6 receives the supply of the clock signal from the clock output terminal CLK to generate the intermittent reception operation signal and performs other control operations, and shares the crystal oscillator 4 with the PLL circuit.

However, the above-mentioned CPU
In order to generate an intermittent reception operation signal and to perform other control, 6 needs to operate even when the slave unit is on standby. Then, the frequency division phase comparison circuit 3 also needs to operate during this standby in order to divide the oscillation signal of the crystal oscillator 4 and supply the clock signal to the CPU 6. However, the PLL
As shown in FIG. 5, the prescaler control signal output terminal PCR of the frequency division phase comparison circuit 3 constituted by a general purpose IC generally supplies an H level from the power supply VCC through the pull-up resistor R1. When the frequency division phase comparison circuit 3 is operated during standby, the internal programmable frequency divider is not preset while the reception operation is stopped by the intermittent reception operation, and therefore the H level is continuously output. Also in the prescaler circuit 2 which inputs the prescaler control signal from the prescaler control signal output terminal PCR, the input terminal is grounded via the internal impedance R2, so that the reception operation is stopped by the intermittent reception operation. , H-level prescaler control signal continues to flow current. Therefore, conventionally, in a receiver circuit of a cordless phone slave unit, a pulse swallow type PLL is used.
Since the prescaler control signal of the circuit is at the H level even while the reception operation is stopped during standby, there has been a problem that the power consumption is increased due to the unnecessary current continuously flowing in the prescaler circuit 2.

In order to solve the above-mentioned problems, the present invention provides a pulse swallow type PLL circuit using a prescaler circuit for switching a frequency division ratio in multiple stages by a prescaler control signal from a programmable frequency divider. Prepare,
A control circuit that operates by a clock signal generated from the same oscillator as the reference oscillation signal of the PLL circuit issues an intermittent reception operation signal that becomes intermittently active to the voltage controlled oscillator of the PLL circuit during standby to perform an intermittent reception operation. In the cordless phone circuit, the output of the prescaler control signal of the programmable frequency divider is connected to the prescaler circuit through a gate circuit that passes an H level signal only when the intermittent reception operation signal issued by the control circuit is activated. It is characterized by that. The present invention is characterized in that the gate circuit is configured by an AND circuit that passes the H level of the prescaler control signal only when the intermittent reception operation signal is at the H level. The present invention is characterized in that the gate circuit is configured by an analog switch that electrically connects the output of the prescaler control signal and the prescaler circuit only when the intermittent reception operation signal is active.

In the standby mode, while the reception operation is being performed by the intermittent reception operation, the L level is initially set for each cycle of the reference oscillation frequency.
The prescaler control signal, which was at the level, is switched to the H level midway. During this period, since the intermittent reception operation signal is active, the prescaler control signal passes through the gate circuit and is sent to the prescaler circuit, and the frequency division ratio can be switched to perform the pulse swallow PLL operation. . Also, while the reception operation is stopped by the intermittent reception operation, even if the prescaler control signal is at the H level, the intermittent reception operation signal is inactive, so it is blocked by the gate circuit and this prescaler at the H level is interrupted. The control signal is never sent to the prescaler circuit.
As a result, according to the present invention, while the reception operation is stopped by the intermittent reception operation, even if the prescaler control signal is at the H level, no unnecessary current flows through the prescaler circuit. The power consumption during standby can be further reduced. As the gate circuit, an AND circuit can be used when the intermittent reception operation signal is active at H level, and a gate circuit other than a logic gate such as an analog switch can be used. .

Embodiments of the present invention will be described in detail below with reference to the drawings. 1 and 2 show an embodiment of the present invention. FIG. 1 is a block diagram showing a PLL circuit used in a receiver circuit of a cordless phone handset, and FIG. 2 is a frequency division in the PLL circuit of FIG. FIG. 6 is a block diagram showing an operation of a phase comparison circuit. Incidentally, the same numbers are added to the constituent members having the same functions as those of the conventional example shown in FIG. In this embodiment, a pulse swallow type PLL circuit used for a local oscillation circuit in a receiver circuit of a cordless phone slave unit will be described. The PLL circuit of the present embodiment is composed of a VCO circuit 1, a prescaler circuit 2, a frequency division phase comparison circuit 3 and a low pass filter 5. The VCO circuit 1 is an oscillator whose oscillation frequency can be controlled by voltage.
The oscillation signal of the VCO circuit 1 is input to the prescaler circuit 2. Prescaler circuit 2 is VC
This is a high-speed frequency divider capable of dividing a high-frequency signal of 400 MHz or more oscillated by the O circuit 1, and the frequency division ratio can be switched between two levels by the prescaler control signal. That is, here, the division ratio is 1/65 when the prescaler control signal is at the L level, and the division ratio is 1/64 when it is at the H level. The signal divided by the prescaler circuit 2 is input to the oscillation signal input terminal PIR of the divided phase comparison circuit 3.
Further, the prescaler control signal is sent from the prescaler control signal output terminal PCR of the frequency division phase comparison circuit 3 to the prescaler circuit 2 through one input of the AND circuit 7. As shown in FIG. 2, the frequency division phase comparison circuit 3 is a PLL IC including a programmable frequency divider 3a and a phase comparator 3b, and a signal from the prescaler circuit 2 is set in the programmable frequency divider 3a. The frequency is divided by the frequency division ratio, the phase is compared with the reference oscillation signal by the phase comparator 3b, and the comparison result is output from the phase difference signal output terminal PDR as a phase difference signal. However, the programmable frequency divider 3a is configured such that the prescaler control signal output terminal PC is first used when presetting the count value indicating the frequency division ratio.
When the prescaler control signal output from R is set to the L level and a dividing ratio of 28681/1 is set, for example, the 28681 is divided by the radix 64 to obtain a quotient of 4
48 and the remaining 9 are counted at the same time. At the end of counting the remainder 9, the prescaler control signal is changed to the H level, and the frequency division ratio of the prescaler circuit 2 is switched from 1/65 to 1/64. Therefore, V
The oscillation signal of the CO circuit 1 is first divided into 1/65 by the prescaler circuit 2 and counted 9 times by the programmable frequency divider 3a, and then divided into 1/64 by the prescaler circuit 2. Since the programmable frequency divider 3a counts 439 (= 448−9) times, when the prescaler circuit 2 and the programmable frequency divider 3a are combined, 9 × 65 + (448−9) × 64 = 28681 is calculated. , The oscillation signal of the VCO circuit 1 is divided into 28,681 times. By the way, the reception frequency of the first channel of the cordless phone handset is 380.2125.
Since the (first) intermediate frequency is 21.7 MHz, the local oscillation frequency at the time of receiving the first channel is
The difference is 358.5125 MHz. Since each channel interval is 12.5 kHz, the frequency division ratio of the PLL circuit when this is used as the reference oscillation frequency is 408.1125 × 1000 ÷ 12.5 = 28681, which must be 1/28681. I have to. Further, if the programmable frequency divider 3a counts the signal divided by 1/65 by the prescaler circuit 2 ten times and then switches the prescaler control signal, 10 × 65 + (448-9) × 64 = 32650 From the calculation of, the oscillation signal of the VCO circuit 1 is divided by 32650, which is a division ratio for dividing the local oscillation frequency at the time of receiving the second channel to the reference oscillation frequency. . That is, this pulse swallow type PLL
In the circuit, by dividing the oscillation frequency of the VCO circuit 1 by 1/65 or 1/64 by the prescaler circuit 2,
It can be input to the programmable frequency divider 3a of the frequency division phase comparison circuit 3 at a low frequency of about 10 MHz, and the reference oscillation frequency is set to 12.5 kHz, which is higher than the voice frequency band of the cordless phone. It is understood that the local oscillation frequency can be changed. The reference oscillation frequency to be compared by the phase comparator 3b is the crystal oscillator (10.625) externally attached to the frequency division phase comparison circuit 3.
MHZ) 4 oscillation frequency is fixed to 1/850 with fixed frequency divider 3c
It is obtained by dividing the frequency into (12.5 MHz / 10.625 MHz). Further, the frequency division phase comparison circuit 3 divides the oscillation frequency of the crystal oscillator 4 into ⅕ by a frequency divider (not shown) to obtain 2.125 MHz (10.625 /
The clock signal of 5) is obtained and output from the clock output terminal CLK for external use. The phase difference signal output from the phase difference signal output terminal PDR of the frequency division phase comparison circuit 3 is fed back to the VCO circuit 1 via the low pass filter 5 as shown in FIG. . Then, the VCO circuit 1 can accurately oscillate at an arbitrary stepwise frequency for each reference oscillation frequency by controlling the oscillation frequency based on the phase difference signal. Therefore, in the receiving circuit of this embodiment, this V
By mixing the oscillation signal of the CO circuit 1 with the reception signal as the local oscillation signal of the PLL circuit, it becomes possible to convert the signal of an arbitrary channel into an intermediate frequency signal. Further, the CPU 6 which controls the cordless phone handset shown in the present embodiment intermittently sets the H level as shown in FIG.
The intermittent reception operation signal that becomes the level is sent to the VCO circuit 1 of the PLL circuit, and the VCO circuit 1 is made to perform the oscillation operation only when this intermittent reception operation signal is at the H level.
The intermittent reception operation signal is also sent to the other input of the AND circuit 7. This CPU
The clock signal 6 is supplied with the clock signal output from the clock output terminal CLK of the frequency division phase comparison circuit 3, thereby generating an intermittent reception operation signal and performing other control operations. The operation of the PLL circuit having the above configuration will be described. When the CPU 6 outputs an intermittent reception operation signal which becomes an H level intermittently as shown in FIG. 3 during standby,
The VCO circuit 1 of the PLL circuit oscillates for 60 msec when the intermittent reception operation signal becomes H level, and stops the oscillation during 1500 msec when the intermittent reception operation signal becomes L level. Therefore, in the cordless phone handset, the battery consumption can be reduced during the standby period by the reception circuit performing the intermittent reception operation. During this standby, while the VCO circuit 1 is oscillating, the prescaler control signal, which was initially at the L level, switches to the H level halfway every cycle of the reference oscillation frequency of 12.5 kHz. During this period, the intermittent reception operation signal also becomes H level, so that the prescaler control signal passes through the AND circuit 7 as it is and is sent to the prescaler circuit 2. Therefore, the prescaler circuit 2 repeatedly switches the frequency division ratio, whereby the PLL operation by the pulse swallow method can be executed. Further, while the VCO circuit 1 stops oscillating, the frequency division phase comparison circuit 3 operates to supply a clock signal to the CPU 6, but the programmable frequency divider 3a is not preset, so the prescaler control signal is supplied. The output terminal PCR continues to output H level.
However, during this period, the intermittent reception operation signal is at the L level, so the output of the AND circuit 7 is always at the L level, and the L level is input to the prescaler circuit 2. As a result, according to the present embodiment, the prescaler control signal output terminal PCR is provided while the reception operation is stopped by the intermittent reception operation.
, The H level is output, the AND circuit 7 outputs the L level, so that no current flows unnecessarily into the prescaler circuit 2 and the power consumption during standby can be further reduced. . In this embodiment, the prescaler control signal output terminal PCR of the frequency division phase comparison circuit 3 is used.
Although the prescaler circuit 2 and the prescaler circuit 2 are connected via the gate circuit by the AND circuit 7, it is also possible to use other logic gate circuits or analog switches that can cut off the H level of the prescaler control signal output terminal PCR. it can.

As is apparent from the above description, according to the present invention, the power consumption can be further reduced while the reception operation is stopped by the intermittent reception operation, so that the standby time of the battery-powered cordless phone can be reduced. This has the effect of allowing extension.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention and showing a PLL circuit used in a receiving circuit of a cordless phone handset.

FIG. 2 is a block diagram showing an operation of a frequency division phase comparison circuit in the PLL circuit of FIG. 1, showing an embodiment of the present invention.

FIG. 3 is a time chart showing an intermittent reception operation signal output by a CPU.

FIG. 4 is a block diagram showing a conventional example and showing a PLL circuit used in a receiving circuit of a cordless phone slave unit.

5 is a circuit diagram showing a connection example between a prescaler control signal output terminal PCR and a prescaler circuit of a frequency division phase comparison circuit in the PLL circuit of FIG. 4, showing a conventional example.

[Explanation of symbols]

 1 VCO circuit 2 Prescaler circuit 3 Frequency division phase comparison circuit 3a Programmable frequency divider 4 Crystal oscillator 6 CPU 7 AND circuit

Claims (3)

[Claims] 1. A pulse swallow type PLL circuit using a prescaler circuit for switching a frequency division ratio in multiple stages by a prescaler control signal from a programmable frequency divider, and is generated from the same oscillator as a reference oscillation signal of this PLL circuit. In a cordless phone circuit that causes a control circuit that operates by a clock signal to perform an intermittent reception operation by issuing an intermittent reception operation signal that is intermittently active to the voltage controlled oscillator of the PLL circuit during standby, the prescaler control signal of the programmable frequency divider Output
A cordless phone circuit characterized by being connected to a prescaler circuit through a gate circuit that passes an H level signal only when an intermittent reception operation signal issued by a control circuit becomes active. 2. An AND which allows the H level of the prescaler control signal to pass only when the intermittent reception operation signal is at the H level
The cordless phone circuit according to claim 1, wherein the circuit is a gate circuit. 3. The gate circuit is configured by an analog switch that electrically connects the output of the prescaler control signal and the prescaler circuit only when the intermittent reception operation signal is active. Cordless phone circuit.