JPH02148914A - Pll frequency synthesizer - Google Patents

Abstract

PURPOSE:To attain stable high speed operation by placing a delay circuit to pre-stage of a power terminal of a voltage controlled oscillator and a PLL frequency synthesizer IC and raising power supply after that of a reference signal generator. CONSTITUTION:A reference signal generator 11 sends a reference signal to a PLL frequency synthesizer IC 12 and a voltage controlled oscillator 13 receives a control signal from the PLL frequency synthesizer IC 12 via a low pass filter 14. When power supply is given to a power terminal 16, the power voltage of a reference signal generator having a bad start characteristic rises immediately but a delay circuit 15 is provided to the voltage controlled oscillator 13 and the PLL frequency synthesizer IC 12 and the power supply is given via the circuit 15, and the circuits are started after the reference signal generator 11 is made stable. Thus, the entire system is transited quickly into the stable state.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a PLL frequency synthesizer device capable of intermittent operation used in mobile communication and other communication information equipment.

(Prior Art) FIG. 5 shows the configuration of a conventional frequency synthesizer device. In FIG. 5, 51 is a reference signal generator, 52 is a PLL frequency synthesizer IC, 53 is a voltage controlled oscillator, 54 is a low pass filter, 55 is a power supply terminal, and 56 is an output terminal of the voltage controlled oscillator.

Next, the operation of the above conventional example will be explained. In FIG. 5, a reference signal generator 51 and a voltage controlled oscillator.

The signal from 53 is frequency-divided by a predetermined ratio by PLL frequency synthesizer IC 52, and the phases of the respective frequency-divided output signals are compared. If the phases and their periods do not match, a control voltage is applied from the PLL frequency synthesizer IC 52 to the voltage controlled oscillator 53 via the low-pass filter 54.

As a result, the output signal frequency of the voltage controlled oscillator is controlled to a point where the phase and period of the frequency-divided signals of the reference signal generator 51 and the voltage controlled oscillator 53 match. Furthermore, by selecting the frequency division ratio, a signal of a desired frequency can be obtained. Note that the PLL frequency synthesizer IC may be provided with a prescaler IC for dividing the signal into an appropriate frequency as necessary. At this time, when the signal from the voltage controlled oscillator 53 is not needed, it is input from the power supply terminal.
It is possible to reduce the average current consumption of the device by performing a repeated operation of turning off g and turning it on when necessary, that is, intermittent operation.

(Problem to be Solved by the Invention) However, in the above-mentioned conventional PLL frequency synthesizer device, although the start of operation in response to the rise of the power supply varies depending on each part, it is necessary to control the entire power supply at once at high speed. There was a problem in that it was difficult to obtain stable operation with respect to the operation. In other words, because other operations start before the operations of each part are activated sufficiently, the entire system falls into an unstable state and the time required to obtain a signal of the desired frequency increases significantly, resulting in a sleep mode. This reduced the time required for startup and provided sufficient time for startup.

On the other hand, in order to reduce power consumption in mobile communications,
It is necessary to insert a stabilizing circuit with a large startup time constant into the power supply circuit in order to reduce the startup characteristics of the oscillation circuit and to improve the frequency accuracy and purity of the signal. For the above-mentioned reasons, these power supplies are sometimes turned on even when in a sleep mode during intermittent operation, which poses a problem of increased power consumption. The present invention is intended to solve these conventional problems, and aims to provide an excellent PLL frequency synthesizer device that can reduce power consumption through stable, high-speed operation.

(Means for Solving the Problems) In order to achieve the above object, the present invention is as shown below.

(1) Voltage controlled oscillator and PLL frequency synthesizer IC
A delay circuit is placed in front of the power supply terminal of the device so that the power supply is turned on later than the reference signal generator.

(2) Voltage controlled oscillator and PLL frequency synthesizer IC
A switch is placed in front of the power supply terminal of the reference signal generator so that the power is turned on later than the reference signal generator, and the power is turned off earlier than the reference signal generator.

(3) A delay circuit is placed in front of the power supply terminal of the PLL frequency synthesizer IC so that the power supply is turned on later than the voltage controlled oscillator and the reference signal generator.

(4) Place a switch in front of the power supply terminal of the PLL frequency synthesizer IC, turn on the power later than the voltage controlled oscillator and reference signal generator, and shut off the power earlier than the voltage controlled oscillator and reference signal generator. do it like this.

(Function) The above configuration of the present invention has the following effects.

(1) Voltage controlled oscillator and PLL frequency synthesizer IC
By starting up the power supply of the reference signal generator earlier than the power supply of the reference signal generator, it is possible to start up the voltage controlled oscillator and the PLL frequency synthesizer IC after the operation of the reference signal generator, which has poor start-up characteristics, has stabilized.

(2) By controlling the switch, the voltage controlled oscillator and PLL
By starting up the power supply of the reference signal generator earlier than the power supply of the frequency synthesizer IC and shutting it off earlier, the voltage-controlled oscillator and PLL frequency synthesizer IC can be started after the operation of the reference signal generator, which has poor startup characteristics, has stabilized. In addition, by shutting off one power supply of the voltage controlled oscillator and PLL frequency synthesizer IC, which continue to operate even when the power supply voltage drops, before the reference signal generator, the system can enter sleep mode in a stable state. can be done.

(3) By starting up the power supply of the voltage controlled oscillator and reference signal generator earlier than the power supply of the PLL frequency synthesizer IC, the voltage controlled oscillator with poor startup characteristics can be made to operate stably together with the reference signal generator, and then the PLL frequency The synthesizer IC can be activated.

(4) Due to switch control, the voltage controlled oscillator and reference signal generator power supplies start up earlier and are shut down earlier than the power supply of the PLL frequency synthesizer IC, so the voltage controlled oscillator with poor startup characteristics is used together with the reference signal generator. The PLL frequency synthesizer IC can be started after stable operation, and the PLL frequency synthesizer IC can continue to operate even when the power supply voltage drops.In order to cut off the power supply of the PLL frequency synthesizer IC before the power supply of the voltage controlled oscillator. It is possible to shift to hibernation mode while maintaining a stable state.

(Embodiment) FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, reference numeral 11 is a reference signal generator which sends a reference signal to the PLL frequency synthesizer IC 12. 1
3 is a voltage controlled oscillator and PLL frequency synthesizer I
A control signal from C12 is received via a low-pass filter 14. 15 is a delay circuit, 16 is a power supply terminal, 17
is the output terminal of the signal from the voltage controlled oscillator.

Next, the operation of the above embodiment will be explained. In the above embodiment, when power is applied to the power supply terminal 16, the power supply voltage of the reference signal generator with poor startup characteristics immediately rises;
Voltage controlled oscillator 13 and PLL frequency synthesizer IC!
2, the power is turned on via the delay circuit 15, and the reference signal generator 11 is adjusted to start up after it has entered stable operation. As described above, the above embodiment has the advantage that the entire system can be brought to a stable state more quickly than when all the power sources are turned on at the same time. Further, according to the embodiment described above, intermittent operation can be controlled at high speed, so that the average value of current consumption of the device can be reduced.

FIG. 2 shows the configuration of another embodiment of the present invention.

In FIG. 1, the delay circuit 15 inserted into the power supply circuit of the voltage controlled oscillator 13 and the PLL frequency synthesizer IC 12 is opened and closed by a control signal applied to the switch control terminal 28 across the switch 25. In this embodiment, in addition to being able to start the voltage controlled oscillator 13 and the PLL frequency synthesizer IC 12 after the operation of the reference signal generator 11, which has poor starting characteristics, has stabilized,
In this case, if the voltage controlled oscillator 13 and PLL frequency synthesizer IC 12 continue to operate even when the power supply voltage decreases, these power supplies are connected to the reference signal generator 1.
By shutting off the power supply with the switch 25 earlier than the power supply of the first power supply, the entire system can shift to the sleep mode while remaining in a stable state.

FIG. 3 shows the configuration of still another embodiment of the present invention. In FIG. 3, the power supply that has passed through the delay circuit 15 is connected only to the PLL frequency synthesizer IC 12, so in addition to the reference signal generator 11, which has poor startup characteristics, the operation of the voltage controlled oscillator 13 is further stabilized in this case. The PLL frequency synthesizer IC can then be activated.

FIG. 4 shows the configuration of still another embodiment of the present invention. In the embodiment shown in FIG. 4, the delay circuit 15 in FIG. 3 opens and closes the switch 25 by a control signal applied to a switch control terminal 28 instead of the switch 25. In this embodiment, after the operations of the reference signal generator 11 and the voltage controlled oscillator 13, which have poor startup characteristics, have stabilized, the PLL frequency synthesizer I
In addition to being able to start up the PLL frequency synthesizer IC12, in this case, if the PLL frequency synthesizer IC12 continues to operate even when the power supply voltage decreases, the PLL frequency synthesizer IC12 can be activated.
The power supply of the frequency synthesizer I'C12 is switched to the switch 2 earlier than the power supply of the reference signal generator 11 and the voltage controlled oscillator 13.
By shutting off the switch 5, the entire system can shift to the rest mode while remaining in a stable state.

(Effects of the Invention) As is clear from the above-mentioned embodiments, the present invention sets the timing of turning on and turning off the power according to the startup characteristics of each circuit of the PLL frequency synthesizer device with respect to the rise of the power supply, and the timing of turning on and cutting off the power is set in accordance with the startup characteristics of each circuit of the PLL frequency synthesizer device. It has the advantage of being able to switch stably and quickly.

Furthermore, since it is possible to switch between intermittent operations at high speed, the time in pause mode can be extended.
This has the effect of lowering the average value of current consumption of the device.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention, FIG.
3 and 4 are schematic block diagrams of other embodiments of the present invention, and FIG. 5 is a schematic block diagram of a conventional example. 11, 51... Reference signal generator, 12.52...P
LL frequency synthesizer, 13.53... Voltage controlled oscillator, 14.54... Low pass filter, 15...
・Delay circuit, 16.55...Power supply terminal, 17.56・
...Output terminal, 28...Switch control terminal. Figure 3 Figure 4 Figure 2 OSC... Minato Jun signal light earthenware PLL IC... Tosaki Synthesis ICVC for PLL
O,,, give up the electric power LFP...Low pass filter DELAY...Circuit circuit SW...Switch old switch source 7...Shikakama 3 28 - Switch I Sokubo 3rd 5 OSC...Stalk error 3 to 1 reward PLL IC... PLL control pest & synth? Guina'ICvco-t *s・co<'69 f-3;k
BLPF...υ-pass fill

Claims (4)

[Claims] (1) In a PLL frequency synthesizer device that is composed of a voltage controlled oscillator, a reference signal generator, and a PLL frequency synthesizer IC, and in which all of the above can operate intermittently, the timing at which the power supply of the reference signal generator starts up is the same as that of the voltage controlled oscillator. A PLL frequency synthesizer device characterized in that the timing is earlier than the power-on timing of a PLL frequency synthesizer IC. (2) The power supply rise timing of the reference signal generator is earlier than the power supply rise timing of the voltage controlled oscillator and PLL frequency synthesizer IC, and the power supply fall timing of the reference signal generator is earlier than the power supply rise timing of the voltage controlled oscillator and PLL frequency synthesizer IC. 2. The PLL frequency synthesizer device according to claim 1, wherein the PLL frequency synthesizer device is slower than the fall of the power supply. (3) The PLL frequency synthesizer device according to claim 1, wherein the timing at which the power supplies of the voltage controlled oscillator and the reference signal generator rise is earlier than the timing at which the power supplies of the PLL frequency synthesizer IC rise. (4) The power supply rise timing of the voltage controlled oscillator and reference signal generator is earlier than the power supply rise timing of the PLL frequency synthesizer IC, and the power supply fall timing of the voltage control oscillator and reference signal generator is earlier than that of the PLL frequency synthesizer IC. 2. The PLL frequency synthesizer device according to claim 1, wherein the PLL frequency synthesizer device is slower than the fall of power of the IC.