JPH0532929B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a frequency synthesizer switching method, and particularly relates to a frequency synthesizer switching method for selectively switching one of a plurality of PLL type frequency synthesizers into an operating state. This relates to a method of switching synthesizers.

[Conventional technology]

For example, in a multi-band receiver, each band is provided with a receiving section and a PLL-type frequency synthesizer. Frequency control data (divided data) is output to the frequency synthesizer on the corresponding band side, and a local oscillation signal with a frequency corresponding to the frequency control data is output to the receiver to tune the band in use. ing.

As shown in FIG. 6, the PLL frequency synthesizer divides the frequency of an oscillation signal generated by a VCO (voltage controlled oscillator) 10 using a frequency dividing circuit 12.
The phase difference between the output of 2 and the reference signal is detected by a phase comparator (frequency/phase comparison type) 14, and the phase difference detection signal outputted by this phase comparator 14 is detected by the LPF 1.
6 for integration, and the output of the LPF 16 is input to the VCO 10 as a control voltage.

The power supply voltage of VCO10 and LPF16 is +15V, and the power supply voltage of frequency divider 12 and phase comparator 14 is +5V.
It is.

The frequency dividing circuit 12 is composed of a prescaler 18 and a programmable divider 20. When frequency division data related to a certain receiving frequency is set in the programmable divider 20 by a microcomputer, the oscillation signal of the VCO 10 is transmitted to the prescaler 1.
The frequency is divided by 8 to a constant frequency division ratio, and the programmable divider 20 further divides only the divided data.

The phase comparator 14 detects the frequency difference and phase difference between the frequency-divided signal inputted from the frequency dividing circuit 12 and the reference signal, and outputs a phase difference detection signal (the phase difference detection signal is high impedance, "L"). Level = almost
Among the three states: 0V, "H" level = approximately +5V,
).

FIG. 7 is a time chart illustrating the operation of the phase comparator 14, and shows as an example a case where a phase difference detection signal is output in accordance with the relationship between the falling edges of the frequency divided signal and the reference signal. As shown in Figure 7 1,
When the frequency divided signal is ahead of the reference signal in phase, the phase difference detection signal is at "H" level from the falling edge of the frequency dividing signal to the falling edge of the reference signal, and is high impedance during the other periods. becomes.

Conversely, when the frequency-divided signal is delayed in phase from the reference signal, the phase difference detection signal is at "L" level from the fall of the reference signal to the fall of the frequency-divided signal, becomes high impedance.

When the phases of the frequency-divided signal and the reference signal match, the phase difference detection signal remains in a high impedance state.

When the frequency of the frequency-divided signal is higher than the reference signal, the phase difference detection signal becomes as shown in FIG. 72, and remains at the "H" level for most of the period.

Conversely, when the frequency of the divided signal is smaller than the reference signal, the phase difference detection signal becomes as shown in FIG. 7,
It is "L" for most of the period.

The phase difference detection signal is output to the LPF 16 and integrated.

This LPF 16 is of an active type as shown in FIG. 6, and the collector side of the transistor Tr is connected to + _Vcc (+15V) via a resistor R1, and the emitter side of the transistor Tr is connected to ground.

The output side of the phase comparator 14 is connected to the base of the transistor Tr via a resistor R2, and a feedback circuit consisting of a capacitor C and a resistor R3 is provided between the collector side and the base side of the transistor Tr.

A control voltage is output from the collector side of the transistor Tr to the VCO 10.

The phase difference detection signal output by the phase comparator 14 is
It is integrated by LPF16, but the phase detection signal is “L”
When the ratio of the phase difference detection signal to the "H" level is high, the output level of the LPF 16 increases, and when the ratio of the phase difference detection signal to the "H" level is high, the output level of the LPF 16 decreases.

When the frequency of the divided signal becomes higher than the reference signal and the phase of the divided signal begins to advance, the output level of the LPF 16 decreases further, the oscillation frequency of the VCO 10 decreases, and the frequency of the divided signal approaches the frequency of the reference signal. .

Conversely, when the frequency of the frequency-divided signal becomes lower than the reference signal and the phase of the frequency-divided signal begins to lag, the LPF16
The output level of the VCO 10 increases, the oscillation frequency of the VCO 10 rises, and the frequency of the divided signal approaches the frequency of the reference signal.

As a result, the frequency synthesizer sets the frequency division ratio of the prescaler 18 to n, and the programmable divider 2
If the frequency division ratio of 0 is m and the frequency of the reference signal is f ₀ , then the VCO 10 will output an oscillation signal with a frequency m·n times f ₀ as the local oscillation signal.
By varying the division ratio data output from the microcomputer and changing m, the frequency of the local oscillator signal can be changed in units of nf ₀ .
Electronic tuning that covers an entire band becomes possible.

By the way, if the VCO of a frequency synthesizer in a band other than the band in use is oscillating, the oscillation signal may loop around to the frequency synthesizer in the band in use, causing malfunction.

For this reason, in a multi-band receiver, power on/off circuits 22 and 24 are attached to the frequency synthesizer.
These power on/off circuits 22, 24 are controlled by a microcomputer, and when the frequency synthesizer is used, the power on/off circuits 22, 24 are controlled to be turned on, and power is supplied to each circuit to bring it into operation. On the other hand, when the frequency synthesizer is not used, the power on/off circuits 22 and 24 are controlled to be off, the power supply to each circuit is stopped, and the oscillation of the VCO 10 is stopped.

[Problem to be solved by the invention]

However, in the conventional method described above, when the power supply to the frequency synthesizer is stopped, the charge stored in the capacitor C of the LPF 16 due to the PLL operation immediately before the power is turned off is discharged to the ground, and as a result, the LPF 16 The output voltage will be 0V.

Then, when power is supplied next and PLL operation starts, the capacitor C of the LPF 16 gradually rises from 0V due to the current flowing from +V _cc through the path with a large time constant of resistor R1, capacitors C, R3, and R2. It takes a long time for the PLL to lock onto a given frequency.

For example, if you want to scan multiple frequency data registered in the channel memory one after another using channel scan mode, and the frequency data for two bands is stored alternately, the frequency synthesizer for each band is It had to be turned on and off alternately, and if the lockup time after supplying power and frequency data to the frequency synthesizer was long, the scan speed would become slow.

In view of the problems of the prior art, an object of the present invention is to provide a frequency synthesizer switching method that can shorten the lockup time of the frequency synthesizer that is about to be used when switching and using a plurality of frequency synthesizers. purpose.

[Means to solve the problem]

In the frequency synthesizer switching method according to the present invention, one of the plurality of PLL frequency synthesizers is selectively switched to an operating state,
In each frequency synthesizer, the low-pass filter is an active filter in which a feedback circuit including a capacitor is connected between the input and output of the amplifier element, and the time constant of the discharge path (charging path) of the capacitor is the same as that of the charging path (discharging path). In a method for switching a frequency synthesizer configured to be smaller than the time constant, the frequency synthesizer that is in an inactive state at the time of switching stops the oscillation of the VCO, and
Charging (discharging) the active filter capacitor
The frequency synthesizer that is in the state and in the operating state is
It is characterized by causing the VCO to oscillate and releasing the charging (discharging) state of the capacitor to perform normal PLL operation.

〔Example〕

Next, one embodiment of the present invention will be described based on FIG.

FIG. 1 is a circuit diagram showing a multi-band receiver for 144 MHz and 430 MHz according to the present invention.

The first frequency synthesizer 30 is for the 144 MHz band, and is configured in the same manner as shown in FIG. 6, including a VCO 32, a prescaler 34, a programmable divider 36, a phase comparator 38, and an active LPF 40.

Prescaler 34 and programmable divider 3
6 constitutes a frequency dividing circuit 42.

The second frequency synthesizer 50 is for the 430 MHz band and is configured in the same manner as shown in FIG. 6, including a VCO 52, a prescaler 54, a programmable divider 56, a phase comparator 58, and an active LPF 60.

Prescaler 54 and programmable divider 5
6 constitutes a frequency dividing circuit 62.

The frequency dividing circuit 42 and the phase comparator 38 are, for example,
It can be configured using a PLL IC such as M54959P (manufactured by Mitsubishi), and the frequency divider circuit 62 and phase comparator 58 are also similar.

The phase comparators 38 and 58 are of the frequency/phase comparison type, and perform frequency/phase comparison operations as shown in FIG.

The output of the VCO 32 of the first frequency synthesizer 30 is output as a local signal to the first receiving section 44 for the 144 MHz band.

In addition, the VCO of the second frequency synthesizer 50
The output of 52 is sent to the second receiving section 64 for the 430MHz band.
is output as a local oscillator signal.

Frequency divider circuit 42 of first frequency synthesizer 30
and a frequency divider circuit 62 of the second frequency synthesizer 50
The positive side power input terminal and the ground side power input terminal are connected to +V _cc ′ (+5V) and ground.
Always, regardless of frequency synthesizer switching.
+5V power is supplied.

In addition, the LPF of the first frequency synthesizer 30
40 and the LPF 6 of the second frequency synthesizer 50
The positive side power input terminal and ground side power input terminal of 0 are connected to +V _cc (+15V) and ground.
Always, regardless of frequency synthesizer switching.
+15V power is supplied.

On the other hand, the VCO of the first frequency synthesizer 30
32 and the VCO 5 of the second frequency synthesizer 50
The positive side power input terminal of No. 2 is connected to +V _cc , and the ground side power input terminal is connected to the power on/off circuit 70.

This power on/off circuit 70 has two switches 72 and 74 that perform opposite switch operations in accordance with a band switching signal input from a microcomputer 76, which will be described later. One side of is connected to ground.

The other side of the switch 72 is connected to the ground side power input terminal of the VCO 32, and the other side of the switch 74 is connected to the ground side power input terminal of the VCO 52.

When the band switching signal is "H", the switch 72 is closed and the switch 74 is opened, power is supplied to the VCO 32 on the first frequency synthesizer 30 side, and the VCO 32 on the first frequency synthesizer 30 side is in an oscillation state, and the second frequency synthesizer 50 is in an oscillation state.
The power to the VCO 52 is turned off and oscillation stops.

Conversely, when the band switching signal is "L", the switch 72 is opened and the switch 74 is closed, power is supplied to the VCO 52 on the second frequency synthesizer 50 side, and the VCO 52 on the second frequency synthesizer 50 side is in an oscillation state, and the first frequency synthesizer 3
The power to the VCO 32 of 0 is turned off and oscillation stops.

A reference signal of frequency f ₀ is input to the phase comparators 38 and 58 of the first and second frequency synthesizers 30 and 50, respectively.

The first receiving section 44 and the second receiving section 64 are
Each receives radio waves with a frequency corresponding to the frequency of the local oscillator signal, and demodulates the audio signal.

The output sides of the first receiving section 44 and the second receiving section 64 are connected to an amplifier (not shown) via a switching circuit 78, and one of the audio signals selected by the switching operation of the switching circuit 78 is connected to the output side of the first receiving section 44 and the second receiving section 64. is amplified and output to the speaker.

The switching circuit 78 outputs the audio signal input from the first receiving section 44 to the amplifier side when the band switching signal is "H" according to the band switching signal input from the outside, and outputs the audio signal input from the first receiving section 44 to the amplifier side when the band switching signal is "L". At this time, the audio signal input from the second receiving section 64 is output to the amplifier side.

The programmable dividers 36, 56 of the first and second frequency synthesizers 30, 50 are connected to the microcomputer 76, and each has a frequency of 144M
Frequency data for the Hz band and 430MHz band is input.

Further, the power on/off circuit 70 and the switching circuit 78 are also connected to the microcomputer 76, and a band switching signal is input thereto.

An operation unit 80 is connected to the microcomputer 76, and when the user performs a preset reception operation, a memory scan mode setting operation, etc., a signal corresponding to the operation is input to the microcomputer 76.

The microcomputer 76 includes a CPU, ROM,
It consists of a RAM connected to a bus, and executes various control operations such as preset reception control and memory scan control according to user operations according to a predetermined program stored in the ROM.

The RAM of the microcomputer 76 is provided with frequency memory areas for channels 1 to 10, and can store channel data for 10 channels.

The RAM also stores channel data CH currently being received.

Each channel data C ₁ to C ₁₀ stored in the frequency memory area is band data CB ₁ to CB ₁₀ representing the type of band (0: 144MHz band, 1:
430MHz band) and reception frequency data CF ₁ to CF ₁₀
Consists of.

The RAM also includes a first frequency synthesizer 3.
Extremely large frequency division data R such that the output of the phase comparator 38 of the second frequency synthesizer 50 becomes the "L" level and the output of the phase comparator 58 of the second frequency synthesizer 50 becomes the "L" level. Extremely large frequency division data S with the maximum ratio is stored.

The first receiving section 44 and the second receiving section 64 include
First and second station detection circuits 46 and 66 are connected to each other, and output a station detection signal to the microcomputer 76 when the intermediate frequency signal exceeds a predetermined level.

When the microcomputer 76 receives a station detection signal during memory scan control, it interrupts the memory scan control and enters a preset reception state.

Note that the prescaler 34 of the first frequency synthesizer 30 (the same is true for the prescaler 54 of the second frequency synthesizer 50) generally has an input input composed of an ECL (emitter-coupled logic circuit) differential amplifier, as shown in FIG. It is composed of a circuit 84 and a digital frequency divider 86 connected to the input circuit 84, and the output signal of the VCO 32 is connected to one input terminal F _IN of the input circuit 84 via a coupling capacitor C _IN . The other input terminal F _ref is connected to ground via a capacitor C _ref .

Inside the input circuit 84, a bias circuit 88 applies the same bias to the input terminals F _IN and F _ref .

In order to ensure high-speed operation, the transistors Tr1 and Tr2 of the input circuit 84 operate symmetrically in a non-saturation region in response to alternating current changes in the oscillation signal output from the VCO 32, and output "H" level or "L" level from the collector side. The level is output, and one or both of the collector sides of the transistor Tr1 and the transistor Tr2 are input to the digital frequency divider 86.

As an example of the digital frequency divider 86 that uses one signal output from the input circuit 84,
There is a frequency divider circuit described in Japanese Patent Publication No. 37136, etc., and an example of using two signals output from the input circuit 84 is a frequency divider circuit described in Japanese Patent Publication No. 52-35988,
There is a frequency dividing circuit described in Japanese Patent Publication No. 60-36137. Each of the frequency dividing circuits is internally fed back in order to obtain a predetermined frequency division ratio.

By the way, when the VCO 32 has stopped its oscillation operation and the prescaler 34 is in a no-input state with power being supplied, the input terminals F _IN and _ref are at the same level, and the collector outputs of transistors Tr1 and Tr2 are originally It is often the case that the nozzle is not determined to be at the "H" or "L" level, but is in the middle of an uncertain level, and approaches the "H" level or approaches the "L" level. Sometimes, due to relatively large noise, "H" level or "L" level
(Since the circuit is configured to operate in a non-saturation region, the difference between the "H" level and "L" level of the input circuit output is inherently small and is susceptible to noise.) If not, also
Return to intermediate level.

As described in the above-mentioned Japanese Patent Publication No. 2-37136, the input level of the digital frequency divider 86 fluctuates in the uncertain region, which causes malfunction of the digital frequency divider 86, and the input level of the digital frequency divider 86 is caused to malfunction through the feedback system. It behaves like a ring-connected ring oscillation circuit, and has the property of producing abnormal oscillation output.

This is common to prescaler 34 that has a high upper limit frequency of operation, such as PLLIC (M54959P manufactured by Mitsubishi Electric) whose upper limit frequency is 500MHz.
When measured with the built-in prescaler,
Causes abnormal oscillation at a high frequency of about 530MHz.

The above is based on the second frequency synthesizer 50
The same holds true for the prescaler 54.

In this embodiment, such characteristics of the prescalers 34 and 54 are used inversely.

Next, the operation of the above embodiment will be explained with reference to the flowchart of FIG.

In addition, each band data of channels 1, 3, 5, and 7 in the frequency memory area provided in RAM
CB ₁ , CB ₃ , CB ₅ , CB ₇ are all in the 0 144MHz band, and other channel data CB ₂ , CB ₄ , CB ₆ ,
It is assumed that CB ₈ , CB ₉ , and CB ₁₀ are all in the 1 430 MHz band.

It is assumed that preset reception was performed based on the channel data of 10 channels immediately before the previous power switch-off (CH=10 at this time).

When the power switch is turned on, the microcomputer 76 performs a predetermined initial setting process and reproduces the reception state when the power was turned off last time (step 100).

Here, the microcomputer 76 selects CH=
10, so band data related to 10 channels
Referring to CB _CH = CB ₁₀ = 1, an "L" level band switching signal is output to the power on/off circuit 70 and switching circuit 78, and 10
Read the reception frequency data CF ₁₀ related to the channel, and use the frequency division data calculated based on CF ₁₀ as the second
is output to the programmable divider 56 of the frequency synthesizer 50 to set the frequency division ratio _k10 .

At this time, frequency division data R is output to the programmable divider 36 of the first frequency synthesizer 30 to set the frequency division ratio r.

The power on/off circuit 70 connects the VCO 52 side to the ground according to the band switching signal, so that +15V power is supplied.

The VCO 52 receives power and starts oscillating, and the second frequency synthesizer 50 performs a PLL operation, and when the division ratio of the prescaler 54 is h, the frequency f ₀ of the reference signal is h·k ₁₀ A local oscillation signal with twice the frequency is output from the VCO 52 to the second receiving section 64.

The second receiving section 64 tunes to the reception frequency related to CF ₁₀ based on the local oscillation signal input from the VCO 52, and if there is a receiving station, reproduces and outputs the audio signal.

The switching circuit 78 selects the audio signal input from the second receiving section 64 according to the band switching signal and outputs it to the amplifier, so that if there is a receiving station, the voice of the other station can be heard from the speaker.

On the other hand, the power on/off circuit 70 disconnects the VCO 32 from the ground according to the band switching signal and stops the power supply.

Therefore, the VCO 32 is in a state where oscillation is stopped.

At this time, since power is supplied to the frequency divider circuit 42 and the LPF 40, the prescaler 34, which is in a non-input state, self-oscillates at a certain frequency as described above (this level is small and the second frequency synthesizer 50 side ), the frequency is divided by the frequency division ratio r by the programmable divider 36, and then input to the phase comparator 38.

However, because the frequency division ratio r is too large, the frequency of the frequency-divided signal input to the phase comparator 38 becomes too low compared to the reference signal, and the phase difference detection signal output from the phase comparator 38 becomes "L" level. (See Figure 7, Figure 3).

Therefore, the transistor Tr of the LPF 40 is almost in an off state, and the capacitor C is charged to approximately +15V.

In this state, when there is no partner station related to the receiving frequency of channel 10 and the user performs a memory scan mode setting operation to search for another partner station, the memory scan mode ON signal input from the operation unit 80 is activated. microcomputer 76 performs memory scan control (YES in step 102).
judgment).

In this memory scan control, the microcomputer 76 first increments CH (step 104), and in this case it exceeds 10, so CH=
1 (YES in step 106, 108).

Next, the microcomputer 76 selects CH=1.
Therefore, band data related to one channel CB ₁ =
0 and outputs an "H" level band switching signal to the power on/off circuit 70 and switching circuit 78, reads received frequency data CF ₁ for one channel from the frequency memory area, and calculates based on CF ₁ . The frequency division data is output to the programmable divider 36 of the first frequency synthesizer 30 to set the frequency division ratio _p1 .

At this time, the frequency division data S is output to the programmable divider 56 of the second frequency synthesizer 50 to set the frequency division ratio s (step 110,
112).

The power on/off circuit 70 connects the VCO 32 side to the ground according to the band switching signal, so that +15V power is supplied.

The VCO 32 receives power and starts oscillating, and the first frequency synthesizer 30 starts PLL operation.

Approximately +15V is applied to VCO32 from LPF40 in advance.
Since a high control voltage is applied, it initially oscillates at a high frequency.

This oscillation signal is frequency-divided by a prescaler 34 to a frequency division ratio q, and is further divided by a programmable divider 3
The frequency is divided by 6 to a frequency division ratio p ₁ and input to the phase comparator 38 .

Since the frequency of the frequency-divided signal is much higher than that of the reference signal, initially the phase difference detection signal output from the phase comparator 38 has a very high proportion of being at the "H" level (see FIG. 7, 2).

Therefore, the transistor Tr of the LPF 40 is almost turned on, and the charge stored in the capacitor C is rapidly discharged, so that the control voltage rapidly decreases from +15V.

As the control voltage decreases, the oscillation frequency of the VCO 32 also rapidly decreases, and the frequency of the frequency-divided signal rapidly approaches the frequency of the reference signal.

When the frequency of the divided signal enters the phase comparison range of the PLL, the proportion of the phase difference detection signal output from the phase comparator 38 being at the "H" level gradually decreases, and the proportion of the phase difference detection signal outputting from the phase comparator 38 being at the "L" level gradually decreases. When the frequency of the divided signal finally matches the reference signal, the discharge of the capacitor C stops and the control voltage becomes a constant value.

At this time, the VCO 32 sends an oscillation signal with a frequency q·p ₁ times the frequency f ₀ of the reference signal to the first receiving unit 44.
Output to.

On the other hand, the power on/off circuit 70 disconnects the VCO 52 from the ground according to the band switching signal, thereby stopping the power supply.

Therefore, the VCO 52 is in a state where oscillation is stopped.

At this time, since power is supplied to the frequency divider circuit 62 and the LPF 60, the prescaler 54, which is in a non-input state, self-oscillates at a certain frequency as described above (this level is small and the first frequency synthesizer 30 side ), the frequency is divided by the frequency division ratio s by the programmable divider 56, and then input to the phase comparator 58.

However, because the frequency division ratio S is too large, the frequency of the frequency-divided signal input to the phase comparator 58 becomes too low compared to the reference signal, and the phase difference detection signal output from the phase comparator 58 becomes "L" level. (See Figure 7, Figure 3).

Therefore, the transistor Tr of the LPF 60 is almost turned off, and the capacitor C is charged to approximately +15V.

The first receiving unit 44 tunes to the reception frequency related to CF ₁ based on the local oscillation signal input from the VCO 32, and if there is a receiving station, outputs a high level intermediate frequency signal to the first station detection circuit 46. (At this time, the audio signal is output to the switching circuit 78).

Here, it is assumed that there is no partner station related to the reception frequency of one channel, and the first station detection circuit 46 does not output a station detection signal.

After the process in step 112, the microcomputer 76 sets a timer and waits until a predetermined lockup time τ has elapsed (steps 114 and 76).
116).

After setting the timer, when τ has elapsed, the microcomputer 76 checks the input from the first station detection circuit 46 and determines whether there is a partner station (step 118).

In this case, no station is detected, so the microcomputer 76 returns to step 104 and again
Increment CH to 2, read band data CB ₂ of channel 2, and since this is "1", output a band switching signal of "L" level, and receive frequency data of channel 2.
Read CF ₂ and calculate the corresponding frequency division data,
The result is output to the programmable divider 56, and the frequency division data R is output to the programmable divider 36 (steps 106, 110, 120).

Therefore, now the second frequency synthesizer 50
performs PLL operation, but at this time, capacitor C is first rapidly discharged in the same way as described above.
The oscillation frequency of the VCO 52 rapidly decreases, and the frequency of the divided signal rapidly approaches the frequency of the reference signal, so it is quickly locked up and finally, if the division ratio at the programmable divider 56 is _k2 , then f A local oscillator signal with a frequency h·k _twice that of ₀ is output to the second receiving section 64.

Therefore, the second receiving section 64 is tuned to the receiving frequency indicated by the 2-channel receiving frequency data CF ₂ .

On the other hand, on the first frequency synthesizer 30 side, the oscillation of the VCO 32 stops in the same manner as described above, and the capacitor C is charged to approximately +15V.

When the second receiving section 64 cannot catch the other station, the second station detection circuit 66 does not output a station detection signal.

After the processing in step 120, the microcomputer 76 checks the input from the second station detection circuit 66 after a lockup time τ (steps 114 to 118), but since no station is detected here, The microcomputer 76 returns to step 104 again, increments CH to 3, reads the band data CB ₃ of the 3rd channel, and since this is "0", outputs a band switching signal of "H" level, and also outputs the band switching signal of the 3rd channel. The reception frequency data CF ₃ is read out, corresponding frequency division data is calculated and output to the programmable divider 36, and frequency division data R is output to the programmable divider 56 (steps 106, 110, 112).

Therefore, this time the first frequency synthesizer 30
performs PLL operation, but at this time, capacitor C is first rapidly discharged in the same way as described above.
The oscillation frequency of the VCO 32 rapidly decreases, and the frequency of the divided signal rapidly approaches the frequency of the reference signal, so it is quickly locked up and finally, if the frequency division ratio at the programmable divider 36 is _p3 , f A local oscillator signal with a frequency q·p _three times that of ₀ is output to the first receiving section 44.

Therefore, the first receiving section 44 is tuned to the reception frequency indicated by the reception frequency data CF ₃ of the three channels.

On the other hand, on the second frequency synthesizer 50 side, the oscillation of the VCO 52 stops in the same manner as described above, and the capacitor C is charged to approximately +15V.

If the first receiving unit 44 catches the other party's station at the receiving frequency related to channel data of three channels, it outputs the audio signal to the switching circuit 78 and outputs the high-level intermediate frequency signal to the first receiving unit.
The signal is output to the station detection circuit 46.

This first station detection circuit 46 outputs a station detection signal to the microcomputer 76.

The microcomputer 76 waits for a predetermined lockup time τ after the processing in step 112, checks the input from the first station detection circuit 46, and determines whether or not a station has been detected (step 112).
114-118).

Since the station has been detected here, the microcomputer 76 stops memory scan control and
The preset receiving state for three channels is entered (step 122).

Since the switching circuit 78 is switched to the first receiving section 44 side, the audio signal of the other station is sent to the amplifier, amplified, and further output to the speaker for acoustic reproduction.

According to this embodiment, for example, the frequency synthesizer 50 is in use and is performing PLL operation at 430 MHz.
When outputting the local oscillation signal for the band to the second receiving section 64, the unused frequency synthesizer 30
While only powering down the VCO 32 to stop unnecessary oscillations, power is continued to be supplied to the frequency dividing circuit 42, phase comparator 38, and LPF 40, and
By giving divided data S with an extremely large frequency division ratio to the programmable divider 36, the oscillation output of the prescaler 34, which self-oscillates when there is no input, is divided by a large frequency division ratio and then input to the phase comparator 38. , the ratio of the phase difference detection signal output from the phase comparator 38 being at the "L" level is maximum,
The transistor Tr of the LPF 40 is almost turned off, and the capacitor C is charged to approximately +15V.

Therefore, after that, in order to switch the frequency synthesizer to be used to the 30 side, when power is supplied to the VCO 32 and certain frequency division data for reception is given to the programmable divider 36 to start the PLL operation, first , the oscillation frequency of the VCO 32 becomes extremely high and the frequency of the divided signal becomes much higher than the frequency of the reference signal, so the proportion of the phase difference detection signal output from the phase comparator 38 being at the "H" level increases. At the maximum, the transistor Tr of the LPF 40 is almost turned on and the capacitor C is rapidly discharged, so the oscillation frequency of the VCO 32 rapidly decreases and the frequency of the divided signal rapidly approaches the frequency of the reference signal. Therefore, it must be quickly locked up.

For this reason, the steps in the flowchart in Figure 2
The lockup time τ in 116 can be reduced,
High-speed memory scanning becomes possible.

In the above embodiment, the programmable divider is set with frequency division data that allows the capacitor C of the LPF of the unused frequency synthesizer to be in a charged state. However, if the circuit configuration of the LPF is different, When the time constant in the discharging direction of the capacitor is large and the time constant in the charging direction is small,
Frequency division data that can discharge the capacitor of the frequency synthesizer on the unused side may be set in the programmable divider.

In addition, in the above embodiment, the prescaler's self-oscillation output when there is no input is used for the frequency synthesizer on the unused side, and frequency division data is provided such that the capacitor is charged to approximately +15V by the output of the phase comparator. Unlike this, instead of setting frequency division data, a circuit to control the operation of the LPF is added, and the LPF on the unused side is set to a programmable divider.
Alternatively, the capacitor may be charged.

FIG. 4 shows the frequency synthesizer 30 in FIG.
A frequency synthesizer 30 configured almost similarly to
This is a circuit diagram showing A, the difference is LPF4
A control transistor Tr2 is connected in series between the emitter side of the 0A transistor Tr1 and the ground.

A resistor R4 is connected to the base of this transistor Tr2.
A band switching signal is input from the microcomputer via the .

The other components are the frequency synthesizer 3 in Figure 1.
It is configured exactly the same as 0.

In the frequency synthesizer 30A of FIG. 4, when the frequency synthesizer 30A of FIG.
(The power supply to 32 is stopped).

At this time, the frequency division data for the programmable divider 36 is not changed.

Then, the transistor Tr2 is turned off and the discharge path of the capacitor C is cut off, so that the capacitor C is charged to approximately +15V.

Next, when the frequency synthesizer 30A is put into use, an "H" level band switching signal is applied from the microcomputer to the base of the transistor Tr2, and when changing the frequency division ratio of the programmable divider 36, new frequency division data is input. When set (at this time, power is supplied to the VCO 32), the transistor Tr2 is turned on and a discharge path for the capacitor C is formed.

Therefore, at first, the VCO 32 oscillates at a high frequency, and the frequency of the frequency-divided signal becomes much higher than the reference signal, and the phase difference detection signal output from the phase comparator 38 has a maximum proportion of "L" level, and the transistor Tr1 is also almost turned on, the capacitor C is rapidly discharged, and the oscillation frequency of the VCO 32 is rapidly reduced.

As a result, the frequency synthesizer 30A quickly enters the lock state, and the programmable divider 30A quickly enters the lock state.
Assuming that the frequency division ratio of 6 is p, a local oscillation signal having a frequency q·p times f ₀ is output from the VCO 32 to the first receiving section.

According to the example in Fig. 4, a control transistor is added to the LPF of the frequency synthesizer,
By simply outputting a band switching signal when switching bands, the capacitor of the unused LPF can be charged, and when the capacitor is started to be used, the capacitor can be rapidly discharged to quickly return to the locked state. It can be migrated.

Further, as shown in FIG. 5, the phase comparator 38 and
A switch 82 is provided between the LPFs 40, and when the frequency synthesizer 30B is used, the switch 82 is switched to the output side of the phase comparator 38 according to the "H" level band switching signal, and when the frequency synthesizer 30B is not used, the switch 82 is switched to the output side of the phase comparator 38. The capacitor C may be charged by switching the switch 82 to the ground side in accordance with the band switching signal at the "L" level.

Although each of the above-described embodiments has been described using a multi-band receiver as an example, the present invention is not limited thereto, and may be applied to a multi-band transmitter or a multi-band transceiver.

〔Effect of the invention〕

According to this invention, when switching the frequency synthesizer, the frequency synthesizer to be in an inactive state is
At the same time as stopping the oscillation of the VCO, the capacitor of the active filter is placed in a charging (discharging) state.
The frequency synthesizer to be put into operation mode oscillates the VCO, releases the charging (discharging) state of the capacitor, and performs normal PLL operation.
It is possible to shorten the time required to lock up the device after it is put into operation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a multi-band receiver according to an embodiment of the present invention, FIG. 2 is a specific configuration diagram of the prescaler in FIG. 1, and FIG. 3 shows the operation of the microcomputer in FIG. FIG. 4 is a partially omitted circuit diagram of another embodiment of the present invention, FIG. 5 is a partially omitted circuit diagram of yet another embodiment of the present invention, and FIG. 6 is a conventional circuit diagram. Circuit diagram showing the frequency synthesizer part of the multi-band receiver, No. 7
The figure is a time chart showing the operation of the phase comparator. Explanation of main symbols, 30, 30A, 30B, 5
0: Frequency synthesizer, 32, 52: VCO,
34, 54: Prescaler, 36, 56: Programmable divider, 38, 58: Phase comparator,
40, 40A, 60: LPF, 70: Power on/
Off-circuit, 76: Microcomputer.

Claims (1)

[Claims] 1. One of a plurality of PLL-type frequency synthesizers is selectively switched to an operating state, and each frequency synthesizer has a low-pass filter that includes a capacitor between the input and output of an amplification element. In the switching method of a frequency synthesizer, which is an active filter connected to a feedback circuit, and in which the specific number of capacitor discharging paths (charging paths) is smaller than the time constant of the charging path (discharging path), when switching, The frequency synthesizer that is set to the active state stops the oscillation of the VCO and the capacitor of the active filter is placed in the charging (discharging) state. A method for switching a frequency synthesizer, characterized in that: the frequency synthesizer is configured to perform normal PLL operation.