JPS62117409A - Latch circuit - Google Patents

Abstract

PURPOSE:To prevent malfunctions of a latch circuit, by controlling the electric potential at an output terminal so that the potential does not exceed the threshold voltage of the 3rd gate circuit when a control signal changes to the half of the supply voltage. CONSTITUTION:The enable and disable conditions of the 1st and 2nd gate circuits G1 and G2 are controlled by a control signal phi and, when the circuits G1 and G2 are respectively in the enable and disable conditions, a latch circuit is set to a condition where the latch circuit reads signals from an input terminal A. When the circuit G2 is in the enable condition, the latch circuit holds signals. When the signal phi is unstable, both the circuits G1 and G2 are set in the enable conditions. The signal which appears at an output terminal B when the circuits G1 and G2 are unstable is determined by the ratio between the output impedances Y1 and Y2 of the circuits G1 and G2. Therefore, the output of the 3rd gate circuit G3 never inverts when the output impedance Y1 and Y2 are set to Y1>Y2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a latch circuit used in semiconductor integrated circuits and the like.

[Conventional technology]

FIG. 3 shows a general conventional latch circuit. In the figure, A is the input terminal of the latch circuit, B is the output terminal of the latch circuit, φ is a control signal, and G1 is enabled and disabled controlled by the signal φ. G2 is a second gate circuit whose disable/enable is controlled by the signal φ, and G3 is a third gate circuit.

FIG. 2 shows that the control signal φ becomes unstable in the latch circuit shown in FIG. Second gate circuit G1.
An equivalent circuit is shown when both G2 are enabled, and in the figure, Y3 is the output impedance of the first gate circuit G1, and Y4 is the output impedance of the second gate circuit G2.

Next, the operation will be explained.

When the first gate circuit G1 is enabled by the control signal φ, the second gate circuit G2 is disabled, and a signal based on the signal input from the input terminal A appears at the output terminal B.

Then, the control signal φ is inverted and the first gate circuit G
1 is in the disabled state, the second gate circuit G2 is in the enabled state, and the signal that appeared at the output terminal B before the control 1-roll signal φ was inverted is latched.

(Problem to be solved by the invention) Since the conventional latch circuit is configured as described above,
When noise enters the control signal φ of the latch circuit shown in FIG. 3 and its potential becomes unstable, the first gate circuit G1 and the second gate circuit G2 are enabled. At this time, the signal appearing at the output terminal B is the output impedance Y3 of the first gate circuit G1 and the second gate 1.
It is determined by the ratio of the output impedance Y4 of the 8'' path G2.

In addition, in such a conventional latch circuit, the output impedance Y3 of the first gate circuit G1 is low in order to shorten the propagation delay time of the signal from the input terminal A to the output terminal B, and the chimp size is made small. Therefore, the size of the transistors constituting the second gate circuit G2 is reduced, and the output impedance Y4 of the second gate circuit G2 is increased. Therefore, control 1 - roll signal φ
In the equivalent circuit (Figure 2) when is 1/2Vce, Y
Since 3<Yl and the threshold voltage of the third gate circuit G3 is normally 1/2VCC, the first
The signal read by the gate circuit G1 and the second gate circuit G
If the signals held by G3 are different, the potential of the output terminal B exceeds the threshold voltage of the third gate circuit G3,
The output of the circuit G3 is inverted.

As shown in Figure 2 (al), when Vcc enters the input terminal A while OV is latched, the potential of the output terminal becomes Y3 < Yl, which is lower than the threshold voltage 1/2 Vcc of the third gate circuit G3. II of the above circuit G3
The I force is inverted and the potential of the output terminal B becomes Vcc.

On the other hand, when 0■ enters input terminal A while Vcc is latched as shown in Figure 2 [bl], output terminal Y3<Y
In l, the threshold voltage of the circuit G3 is 1/2Vcc.
Then, the output of the circuit G3 is inverted and the potential of the output terminal B becomes OV.

Therefore, if noise enters the control signal in the latched state, the latch circuit reads the input signal As, which is not normally read, as shown in FIG.
The output of the gate circuit is inverted and the signal As is output to the output terminal B.
It was easy to cause a malfunction in which an output signal '+Bs based on the output signal '+Bs' appeared.

[Means for solving problems]

In the latch circuit according to the present invention, the control signal is “H”.
When the voltage changes from "or" to "L" to 1/2Vcc, the output impedance Y1 of the first gate circuit that reads data and the output impedance Y2 of the second gate circuit that holds data are such that Yl>Y2. It is.

[Effect]

In this invention, when the control signal changes from "H" or "L" to 1/2Vcc, the output impedance Y1 of the first gate circuit and the output impedance Y2 of the second gate circuit are set such that Yl > Y2. Therefore, the potential of the output terminal determined by these ratios does not exceed the threshold voltage of the third gate circuit even when noise of up to 1/2 VCC is added to the control signal in the latched state. The output of is not inverted and the contents of the latch are held.

〔Example〕 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an equivalent circuit of a latch circuit according to an embodiment of the present invention, that is, the control signal φ of the latch circuit shown in FIG. 3 becomes unstable and the first . Second gate circuit G1. G2
shows the equivalent circuit when both are enabled,
(1 in the figure), Yl is the output impedance of the first gate circuit G1, Y2 is the output impedance of the second gate circuit G2, and these impedances are Yl > Y2 when the control signal φ is 1 / 2 Vcc. It is designed to be.

Next, the operation will be explained.

1st. The enable/disable state of the second gate circuit @GI, G2 is controlled by the control signal φ, and when the first gate circuit G1 is enabled and the second gate circuit G2 is disabled, the latch circuit is connected to the input terminal The signal from G1 is read from the circuit G1.
When G2 is disabled and the circuit G2 is enabled, the latch circuit holds the signal. but,
When the control signal φ is unstable, the circuit G1.
Both G2 are enabled. At this time, it appears at the output terminal B (No. 8 is determined by the output impedance yi of the circuits G1 and G2 and the division ratio of Y2. φ-1/
2Vcc, if Yl > Y2, the potential of the output terminal B is the threshold voltage Vc of the third gate circuit G3 (
-1/2Vcg), the output of the circuit G3 is not inverted.

That is, the output of the second gate circuit G2 is “I pin #Vcc”.
, when the output of the first gate circuit G1 is 0 to ``summer'', the signal appearing at the output terminal B becomes y1+y2 (see FIG. 1 (bl)).

On the other hand, the output of G2 is “L”-OV, and the output of Gl is H″-V
When cc, the signal at the terminal becomes Yl +Y2 (see FIG. 1 (al)).

In this way, in this embodiment, as shown in FIG.
2Vcc noise enters the control signal φ and the first.
Both the second gate circuits Gl and G2 are enabled,
Even when the input signal As is read, the potential of the output signal Bs appearing at the output terminal B does not exceed the threshold voltage Vc=]/2Vcct- of the third gate circuit, so that the latched state can be maintained.

In the above embodiment, the control signal φ is φ−”H.
Although the circuit that enters the latched state at `` is shown, this may be a circuit that enters the latched state when the control signal φ is φ-''L''.

In addition, in such a latch circuit, it is necessary to consider the propagation delay time from the input terminal to the output terminal when setting the output impedance of the gate circuit that reads the signal. It is sufficient to focus only on the ratio of the output impedances of the gate circuits, and the absolute value of each impedance can be set freely, so there is no problem.

〔Effect of the invention〕

According to the present invention, as shown in FIG. I try not to exceed it, so the maximum is 1.
This has the effect of providing a noise-resistant latch circuit that does not cause malfunction even if /2Vcc noise enters the control signal.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of a latch circuit according to an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of a conventional latch circuit, Fig. 3 is a block diagram showing a general latch circuit, and Fig. 4 is an equivalent circuit diagram of a conventional latch circuit. A timing diagram of control signals and input and output signals of the latch circuit of the invention. FIG. 5 is a timing diagram of control signals and input and output signals of the conventional latch circuit. A is the input terminal of the latch circuit, B is the output terminal of the latch circuit, φ is the control signal, As is the input signal, Bs is the output signal, Gl, G2 are the first . The second gate circuit, G3 is the third gate circuit, and Yl, Y2 are the first gate circuit of this embodiment. The output impedance of the second gate circuit (1, G2).

Claims (1)

[Claims] (1) A first gate circuit whose enable/disable state is controlled by a control signal and reads data; AND-tie the output of the first gate circuit with the output of the first gate circuit; the enable/disable state is controlled by the control signal; a second gate circuit whose state is controlled and which holds data; its input and output are respectively the outputs of the first gate circuit;
In the latch circuit having a third gate circuit connected to the input of the second gate circuit, when the potential of the control signal changes from "H" or "L" to 1/2 of the power supply voltage Vcc, A latch circuit characterized in that an output impedance Y_1 of the first gate circuit and an output impedance Y_2 of the second gate circuit satisfy Y_1>Y_2.