JPH0738573B2 - Latch circuit - Google Patents

Description

The present invention relates to a latch circuit.

[Conventional technology]

FIG. 3 shows a general conventional latch circuit. In the figure, A is an input terminal of the latch circuit, B is an output terminal of the latch circuit, φ is a control signal, and G ₁ is enabled or disabled by the signal φ. A controlled first gate circuit, G ₂ is a _second gate circuit whose enable / disable is controlled by the signal φ, and G 3 is a power supply potential V _CC of 1
It is a third gate circuit having a threshold value of / 2.

FIG. 2 shows an equivalent circuit when the control signal φ becomes unstable and both the first and second gate circuits G ₁ and G ₂ are enabled in the latch circuit shown in FIG. Y ₃ is the output impedance of the first gate circuit G ₁ , Y ₄
Is the output impedance of the second gate circuit G ₂ , that is, the impedance between V _CC and the output or GND and the output, which is determined by the potential of the control signal φ. First gate circuit G1 and second gate circuit in FIG.
G2 can be shown in FIGS. 6 (a) and 6 (b), respectively.

Next, the operation will be described.

When the first gate circuit G ₁ is enabled by the control signal φ, the second gate circuit G ₂ is disabled and a signal based on the signal input from the input terminal A appears at the output terminal B. Next, when the control signal φ is inverted and the first gate circuit G ₁ is in the disabled state, the second gate circuit G ₂ is in the enabled state, and the signal which appears at the output terminal B before the control signal φ is inverted. Is latched.

[Problems to be solved by the invention]

Since the conventional latch circuit is configured as described above,
When φ noise enters the control signal of the latch circuit shown in FIG. 3 and the potential becomes unstable, the first gate circuit G ₁ and the second gate circuit G ₂ are enabled. Signal appearing at the output terminal B at this time is determined by the ratio of the first output impedance Y ₃ of the gate circuit G ₁ and the second output impedance Y ₄ of the gate circuit G _2.

Further, in such a conventional latch circuit, in order to reduce the propagation delay time of the signal from the input terminal A to the output terminal B, the first
It has become the output impedance Y ₃ of the gate circuit G ₁ of the low and has reduced the size of the transistors constituting the second gate circuit G ₂ to reduce the chip size, the second gate circuit G ₂ The output impedance Y ₄ is high. Therefore, in the equivalent circuit (Fig. 2) when the control signal φ is 1/2 Vcc, Y ₃ <Y ₄ and
The threshold voltage of the third gate circuit G ₃ is normally 1/2 Vcc
Therefore, if the signal read by the first gate circuit G ₁ and the signal held by the _second gate circuit G ₂ are different,
The potential of the output terminal B exceeds the threshold voltage of the third gate circuit G ₃ , and the output of the circuit G ₃ is inverted.

That is, when Vcc enters the input terminal A while 0V is latched as shown in FIG. 2 (a), the potential of the output terminal B becomes When Y ₃ <Y ₄ , this potential becomes higher than the threshold voltage 1/2 Vcc of the third gate circuit G ₃ , the output of the circuit G ₃ is inverted, and the potential of the output terminal B becomes Vcc.

On the other hand, as shown in FIG. 2 (b), when 0V enters the input terminal A while Vcc is latched, the potential of the output terminal B becomes When Y ₃ <Y ₄ , the threshold voltage of the circuit G ₃ becomes lower than 1/2 Vcc, the output of the circuit G ₃ is inverted, and the potential of the output terminal B becomes
It becomes 0V.

Therefore, when noise is included in the control signal in the latched state, the latch circuit reads the input signal As which is not normally read as shown in FIG. 5, and the output of the third gate circuit is inverted and output to the output terminal B. The malfunction that the output signal Bs based on the signal As appears is likely to occur.

[Means for solving problems]

In the latch circuit according to the present invention, the control signal is "H".
Or when it is 1 / 2Vcc from "L", the output impedance Y ₂ of the second gate circuit which outputs impedance Y ₁ and data retention of the first gate circuit to read data Y _1> Y ₂
It is designed to be

[Action]

In the present invention, the control signal "H" or "L"
From 1 to 1/2 Vcc, the output impedance Y ₁ of the first gate circuit and the output impedance Y ₂ of the second gate circuit
The Since was set to be Y _1> Y _2, the potential of the output terminal that is determined by these ratios, even when the maximum 1 / 2Vcc noise enters the control signals on the latched state, the threshold voltage of the third gate circuit , The output of the third gate circuit is not inverted and the content of the latch is retained.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an equivalent circuit of a latch circuit according to an embodiment of the present invention, that is, the control signal φ of the latch circuit shown in FIG. 3 becomes unstable, and the first and second gate circuits G ₁ and G ₂ are both An equivalent circuit in the enabled state is shown. In the figure, Y ₁ is the output impedance of the first gate circuit G ₁ , Y ₂ is the output impedance of the second gate circuit G ₂ , and these impedances are controlled. Signal φ is 1 /
Has become such that the Y _1> Y ₂ when the 2Vcc.

Next, the operation will be described.

The first and second gate circuits G ₁ and G ₂ are enabled / disabled by the control signal φ,
When the gate circuit G ₁ is enabled and the second gate circuit G ₂ is disabled, the latch circuit is in a state of reading the signal from the input terminal A, the circuit G ₁ is disabled, and the circuit G ₂ is enabled. In the state, the latch circuit is in a state of holding a signal. However, when the control signal φ is unstable, both the circuits G ₁ and G ₂ are enabled. The signal appearing at the output terminal B at this time is determined by the division ratio of the output impedances Y ₁ and Y ₂ of the circuits G ₁ and G ₂ . When φ = 1/2 Vcc and Y ₁ > Y ₂ , the potential of the output terminal B is the threshold voltage Vc of the _third gate circuit G _3.
(= 1/2 Vcc) is not exceeded, and the output of the circuit G ₃ is not inverted.

That is, when the output of the second gate circuit G ₂ is “H” ≈Vcc and the output of the first gate circuit G ₁ is “L” ≈0V, the signal appearing at the output terminal B is (See FIG. 1 (b)).

On the other hand, when the output of G ₂ is “L” ≈ 0V and the output of G ₁ is “H” ≈ Vcc,
The signal at this terminal is (See FIG. 1 (a)).

Thus, in this embodiment, as shown in FIG.
The noise of cc enters the control signal φ and both the first and second gate circuits G ₁ and G ₂ are enabled, and even if the input signal As is read, the potential of the output signal Bs appearing at the output terminal B is the third gate. Since the threshold voltage Vc of the circuit does not exceed 1/2 Vcc, the latched state can be maintained. As a matter of course, when φ> 1 / 2V _CC , Y1> Y2,
When <1/2 V _CC , the relationship between Y1 and Y2 is Y1 at a certain φ potential.
And Y2's relationship is reversed. That is, Y2> Y1. The potential here is the first gate circuit G1 and the second gate circuit
Determined by the transistor capability ratio of G2.

In the above embodiment, the control signal φ is φ = “H”
Although the circuit in which the control signal φ is in the latched state is shown in FIG. 4, it may be a circuit in which the control signal φ is in the latched state when φ = “L”.

The output impedance is set, for example, in FIG.
It is determined by the transistor capacities of the first gate circuits P1 to P4 and the second gate circuits N1 to N4. In the present invention, φ = 1 /
When 2V _CC , the transistors P1 and P2 of the first gate circuit G1
Alternatively, each transistor size may be set so that the output impedance determined by the transistors P3, P4 or N3, N4 of the second gate circuit G2 is lower than the output impedance determined by the transistors N1, N2. However, since the transistor size setting differs for each wafer process, the setting should be made according to each process.

Further, in such a latch circuit, it is necessary to consider the propagation delay time from the input terminal to the output terminal in setting the output impedance of the gate circuit for reading the signal. However, in the present invention, the gate circuit and the gate for holding the signal are set. It suffices to focus only on the ratio of the output impedance of the circuit, and there is no problem because the absolute value of each impedance can be set freely.

〔The invention's effect〕

As described above, according to the present invention, when the control signal changes from "H" or "L" to 1/2 of the power supply voltage Vcc,
Since the potential of the output terminal does not exceed the threshold voltage of the third gate circuit, there is an effect that a noise-resistant latch circuit that does not malfunction even if noise of maximum 1/2 Vcc enters the control signal is obtained. .

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a latch circuit according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a conventional latch circuit, FIG. 3 is a block diagram showing a general latch circuit, and FIG. Timing diagram of the control signal and input / output signal of the latch circuit of the invention, FIG. 5 is a timing diagram of the control signal and input / output signal of the conventional latch circuit, and FIG. 6 is a configuration of the first and second gate circuits. It is a figure. A is an input terminal of the latch circuit, B is an output terminal of the latch circuit, φ is a control signal, As is an input signal, Bs is an output signal, G ₁ and G ₂ are first and second gate circuits, and G ₃ is a second gate circuit. 3 gate circuits, Y ₁ and Y ₂ are output impedances of the first and second gate circuits G ₁ and G ₂ of this embodiment, and Y ₃ and Y ₄ are first and first latch circuits of the conventional latch circuit.
It is the output impedance of the second gate circuits G ₁ and G ₂ .

Claims (1)

[Claims] 1. A first gate circuit which has a power supply potential V _CC and a ground potential GND, whose enable / disable state is controlled by a control signal, and which reads data from a data input terminal, and a power supply potential V _CC and ground. A data output terminal having a potential GND and a second gate circuit that holds data and whose disable and enable states are controlled by the control signal, and the outputs of the first and second gate circuits are commonly connected And a third gate circuit in which the output of the first gate circuit and the input of the second gate circuit are connected to the input and the output, respectively, and the threshold voltage is 1/2 of the power supply potential V _CC. When the potential of the control signal changes from the potential for making the latch state to half of the power supply potential V _CC , the potential of the control signal φ of the first gate circuit becomes Therefore, the power supply potential V _CC determined between the output or the ground potential GND and the output Y ₁ and the power supply potential V determined by the potential of the control signal φ of the second gate circuit.
A latch circuit characterized in that an impedance Y ₂ between _CC and an output or between a ground potential GND and an output is Y ₁ > Y ₂ so that an input potential of the third gate circuit becomes equal to or lower than its threshold voltage.