JPH0554660A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent malfunction by comprising the storage device of a logic circuit whose rising time of an output signal is short when a rising input signal is received by a delay circuit and whose falling time of the output signal is long when a falling input signal is received by the delay circuit. CONSTITUTION:When the input signal A rises from an L level to a H level, the output node (b) of an inverter gate INV1 falls from H to L because the capability of a transistor N1 is high. By receiving the signal from the node (b), the output node (c) of the inverter gate INV2 continuously rises from L to H because the capability of the transistor 2 is high. The output node (d) of the inverter gate G1 continuously falls from H to L by receiving the signal from the node (c) because of the lack of a loading condenser. Then, when the signal A falls from H to L, the node (b) gradually rises from L to H by receiving the load from C1 because the capability of the transistor P1 is low. The node (c) gradually falls from H to L by receiving the load from C2 because the capability of the transistor N2 is low, and the node (d) continuously rises from L to H.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a circuit for generating a pulse when an input signal changes.

[0002]

2. Description of the Related Art In a semiconductor memory device, a pulse generated when an input signal is switched is used for promoting discharge of a word line, short-circuiting a bit line pair, charge-up, etc. Therefore, a circuit for generating such a pulse is incorporated. There is something. Figure 4
A conventional example of a pulse generation circuit according to the present invention is shown. D2 in Figure 4
Is a delay circuit, G1 is an inverter gate, G2 is a NOR gate, D2 is a Pch transistor of P41 and P42, Nch transistor of N41 and N42, and C.
It is composed of capacitors C1 and C2. P41 and N4
Inverter gate INV41 composed of 1 and P4
The inverter gate INV42 composed of N2 and N42 has almost the same output signal rising and falling capabilities. A is an input signal and O is an output signal. The input signal A is applied to the input terminal of the inverter gate INV41, the output node b of the inverter gate INV41 is applied to the input terminal of the inverter gate INV42, and the output node c of the inverter gate INV42 is applied to the input terminal of the inverter gate G1. Added to. One node of the capacitor C1 is connected to the node b and the other is connected to the power supply potential, and one node of the capacitor C2 is connected to the node c and the other is connected to the ground potential.

The operation in the circuit of FIG. 4 will be described with reference to FIG. When the input signal A rises from the L (low) level to the H (high) level, the output node b of the inverter gate INV41 gradually rises from the H level to the L level due to the load of the capacitor C1 as shown in FIG. Go down. Upon receiving the signal of the node b, the inverter gate INV42
The output node c of is slowly raised from the L level to the H level due to the load of the capacitor C2. Since the output node d of the inverter gate G1 has no load capacitor, it receives the signal from the node c and quickly falls from the H level to the L level. At this time, the output O of the NOR gate G2 remains L level and does not change. Next, when the input signal A falls from the H level to the L level, the node b gently rises from the L level to the H level. Receiving the signal from node b, node c gently falls from H level to L level. In response to this signal from node c, node d rapidly rises from L level to H level. The output signal O rises from L level to H level when the input signal A falls from H level to L level, and falls from H level to L level again when the node d rises from L level to H level. In this way, when the input signal A falls, the output signal O becomes D shown in FIG.
Of the pulse width of which the pulse rises from L level to H level and falls from H level to L level.

[0004]

As described above, the circuit of FIG. 4 produces a pulse O having a constant pulse width D at the fall of the input signal. In the normal case, the input signal A has a short pulse due to noise. When it enters, the difference between the time when the input signal A rises from the L level to the H level and the time when the input signal A falls from the H level to the L level as shown in FIG. 6 is necessary for the node b to fall sufficiently from the H level to the L level. Within a certain time, or within a time required for the node c to rise sufficiently from the L level to the H level, a pulse having a pulse width shorter than the pulse width D is generated in the output signal O. The time required for acceleration of word line discharge, short-circuiting of bit line pairs, charge-up, etc. is adjusted by the pulse width D of the output signal O. Therefore, when a pulse shorter than the pulse width D is received, We cannot secure the necessary time,
The normality of the memory cell operation cannot be guaranteed.

The present invention aims to improve such points and provide a circuit for generating a pulse having a pulse width of a predetermined value or more when an input signal changes.

[0006]

In a semiconductor memory device of the present invention, a NOR gate to which an input signal is applied to one input terminal, a delay circuit to which the input signal is applied to the input terminal, and an output signal of the delay circuit are provided. Has an inverter gate applied to the input terminal, and a circuit configured to apply an output signal of the inverter gate to the other input terminal of the NOR gate to generate a pulse signal when the input signal falls from the NOR gate. In the semiconductor memory device, the delay circuit is configured by a logic circuit that has a short rise time of its output signal when it receives a rising input signal and a long fall time of its output signal when it receives a falling input signal. It is characterized by being

[0007]

According to this circuit, even when a short pulse due to noise is input to the input signal, a pulse having a pulse width larger than a predetermined pulse width can be generated, and a memory malfunction can be prevented.

[0008]

FIG. 1 shows an embodiment of the present invention. The same parts as those in FIG. 4 are denoted by the same reference numerals. D1 is a delay circuit according to the present invention, and D1 is Pc having a smaller gate channel width.
h transistor P1 and Nc having a large gate channel width
Inverter gate IN composed of h transistor N1
V1, a Pch transistor P2 having a large gate channel width, an inverter gate INV2 composed of an Nch transistor N2 having a small gate channel width, and capacitors C1 and C2. The input signal A is applied to the input terminal of the inverter gate INV1, and the output node b of the inverter gate INV1 is applied to the input terminal of the inverter gate INV2.
The output node c of V2 is applied to the input terminal of the inverter gate G1. One node of the capacitor C1 is a node b
The other end is connected to the power supply potential, one node of the capacitor C2 is connected to the node c, and the other is connected to the ground potential.
The operation in the circuit of FIG. 1 will be described with reference to FIG. Input signal A is L
When the level rises from the H level to the H level, the output node b of the inverter gate INV1 rapidly falls from the H level to the L level due to the high capacity of the Nch transistor N1 although the load of the capacitor C1 is present as shown in FIG. When the signal of the node b is received, the inverter gate I
The output node c of NV2 has a load on the capacitor C2, but since the capacity of the Pch transistor P2 is high, it quickly rises from the L level to the H level. Inverter gate G
Since the output node d of No. 1 has no load capacitor, it quickly falls from H level to L level upon receiving the signal of the node c. At this time, the output O of the NOR gate G2 remains L level and does not change. Next, when the input signal A falls from the H level to the L level, the node b receives the load of C1 and slowly rises from the L level to the H level because the capacity of the Pch transistor P1 is low. In response to this signal from node b, node c has a low capacity of Nch transistor N2, and therefore receives a load of C2 and slowly falls from H level to L level. In response to this signal from node c, node d
Quickly rises from L level to H level. The output signal O rises from L level to H level when the input signal A falls from H level to L level, and falls from H level to L level again when the node d rises from L level to H level. In this way, when the input signal A falls, the output signal O changes to D shown in FIG.
Of the pulse width of which the pulse rises from L level to H level and falls from H level to L level.

A case where a pulse having a short pulse width enters the input signal A due to noise as shown in FIG. 3 will be described. As described above, the node b promptly falls with respect to the rising of the input signal A, the node c rapidly rises, and the node d also quickly falls. Input signal A
When is dropped, node b rises slowly, node c slowly falls, and node d rises quickly. Therefore, the output signal O of the NOR gate G2 generated by the fall of the input signal A and the rise of the node d can generate a pulse having a pulse width D in the normal state as shown in FIG.

Although the pulse generated at the falling edge of the input signal A has been described in the above embodiments, in order to generate the pulse at the rising edge, the input signal A and the inverter gate INV1 are generated as shown in FIG. It suffices to use a circuit in which an inverter gate G3 is inserted between the input ends of.

In order to generate a pulse at both the rising edge and the falling edge of the input signal A, the input signal A is supplied to the circuit of FIG. Connect to the input end of the circuit and output each signal to N
A similar pulse can be obtained by connecting each input terminal of the OR gate G4 and inverting its output by the inverter gate G5.

In the present invention, the NOR gate is used for G2 to obtain the pulse rising to the H level, but the falling pulse can be obtained by replacing G2 with the NAND gate.

[0013]

As described above, according to the present invention, it is possible to provide a pulse generation circuit which generates a pulse having a pulse width equal to that generated when a normal input signal is generated even when the input signal contains noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of FIG. 1 when an input signal A is normal.

FIG. 3 is a waveform diagram for explaining the operation of FIG. 1 when an input signal A is abnormal.

FIG. 4 is a circuit diagram showing a conventional example.

5 is a waveform diagram for explaining the operation of FIG. 4 when the input signal A is normal.

6 is a waveform diagram for explaining the operation of FIG. 4 when the input signal A is normal.

FIG. 7 is a circuit diagram showing an application example of the present invention.

FIG. 8 is a circuit diagram showing an application example of the present invention.

[Explanation of symbols]

D1 ... delay circuit of the present invention D2 ... conventional delay circuit G1, G3, G5 ... inverter gates G2, G4 ... NOR gate P1 ... Pch transistor (small W) N1 ··· Nch transistor (W size) P2 ··· Pch transistor (W size) N2 ··· Nch transistor (W size) INV1 ··· Inverter gate composed of P1 and N1 INV2 ··· ··· Inverter gate composed of P2 and N2 INV41 ···· Inverter gate composed of P41 and N41 INV42 ··· Inverter gate composed of P42 and N42 C1, C2 ··· Capacitors P41, P42 ... Pch transistors N41, N42 ... Nch transistor A ... Input signal O ... Output signals

Claims (1)

[Claims] 1. An N input signal applied to one input terminal.
An OR gate, a delay circuit to which the input signal is applied to the input terminal, an inverter gate to which the output signal of the delay circuit is applied to the input terminal, and an output signal of the inverter gate to the N
In a semiconductor memory device having a circuit for generating a pulse signal when the input signal falls from the NOR gate in addition to the other input terminal of the OR gate, when the delay circuit receives the rising input signal, A semiconductor memory device comprising a logic circuit in which a rising time of an output signal is short and a falling time of the output signal is long when a falling input signal is received.