KR200269239Y1 - Reference voltage generator - Google Patents

Abstract

The present invention relates to a reference voltage generator, and by using a 1/2 Vcc voltage that is always applied to the data output buffer output terminal from the outside of the DRAM to reduce the design area and unnecessary power consumption by creating a reference voltage without a separate reference voltage generator circuit In order to achieve this, a data output buffer, an input buffer, and connection means for connecting the two devices are provided.

Description

Reference voltage generator

The present invention relates to a reference voltage generator of a semiconductor memory device, and more particularly, a reference voltage generator for more effectively obtaining a reference voltage used in an input buffer of a DRAM (Dynamic Random Access Memory, hereinafter referred to as "DRAM"). It is about.

In general, when the memory devices are highly integrated, the area of the chip increases and power consumption cannot be ignored.

Accordingly, the company is moving toward reducing power consumption by reducing the size of external voltages, and various measures are being made to reduce the size of chips in layout.

The present invention aims to obtain a reference voltage that can reduce the size of the chip and reduce power consumption.

1A and 1B illustrate a reference voltage generation circuit used in a conventional DRAM and an input buffer circuit that generates an address using a reference voltage.

The input buffer 200 circuit latches the incoming external signal EXT-An at the moment when CON1 changes from "low" to "high" and compares the AXn and / AXn with phases opposite to each other. Make it.

This kind of buffer is called a dynamic buffer, and the reference voltage in this dynamic buffer is Vref.

That is, if the input from the outside is lower than the reference voltage, AXn is "low", / AXn is "high", and if the input from the outside is higher than the reference voltage, vice versa.

In this case, the reference voltage is usually about 1/2 Vcc.

However, until now, such a reference voltage has been made using the conventional reference voltage generating circuit 100 as shown in FIG. 1A.

Since it occupies a certain area in the DRAM, the area of the chip is increased and there is a problem in that the current must be continuously consumed due to the generation of the reference voltage.

Therefore, the present invention was devised to solve this problem, and the current voltage is reduced by using the high-impedance voltage present at the data input / output terminal instead of the conventional reference voltage generator. It is an object of the present invention to provide a reference voltage generator for reducing the area of a chip.

1A is a conventional reference voltage generation circuit diagram.

1B is a conventional row address buffer circuit diagram.

2 is a conventional data output buffer circuit diagram.

Figure 3a is a reference voltage generation circuit diagram according to an embodiment of the present invention.

3B is an operation timing diagram of FIG. 3A.

Explanation of symbols on the main parts of the drawing

100: reference voltage generation circuit 200: input buffer

300: data output buffer 400: external DRAM

500: delay unit 600: connection unit

700: capacitor

The reference voltage generator of the present invention for achieving the above object is an input buffer for operating the first signal to output the address signal;

A reference voltage generator of a semiconductor memory device comprising a data output buffer controlled by a second signal and outputting predetermined data,

Connected between the data output buffer output terminal and the input buffer input terminal and operated by the first signal to turn on when the data output buffer is in a high-impedance state to use the potential of the data output buffer output terminal,

When the data output buffer is in operation, characterized in that it comprises a connecting means for cutting off the output terminal potential of the data output buffer.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

FIG. 2 illustrates a data output buffer generally used in a DRAM, and 400 illustrates a model of a load applied from the outside of the DRAM to the data output buffer output terminal.

The VTT of 400 is about 1/2 Vcc.

In FIG. 2, when the control signal CON2 is in the "high" state, one of the pull-up transistor and the pull-down transistor is "high" according to DO and / DO to operate the data output buffer 300.

While CON2 is "low", the pull-up transistor and pull-down transistor are both "low", so the data output node is in a high-impedance state disconnected from inside the DRAM.

At this time, the data output node maintains a VTT voltage of about 1/2 Vcc.

3A shows a circuit for generating a reference voltage used as an input buffer according to an embodiment of the present invention, which is controlled by CON2 to generate "high" or "low" data, and The data output buffer 300 is composed of a connection unit 600 connected to an output terminal of the control signal CON1, and an input buffer 200 connected to the output terminal of the connection unit 600.

The connection unit 600 receives the CON3 signal from the inverter IV receiving the CON1 signal, the delay unit 500 outputting the CON3 signal by delaying the output signal of the inverter IV for a predetermined time, and One terminal includes an NMOS transistor MN connected to an output terminal of the data output buffer 300, and a capacitor 700 connected between the other terminal of the NMOS transistor MN and a ground voltage terminal.

3B illustrates an operation timing diagram of FIG. 3A.

Hereinafter, the operation relationship with respect to FIG. 3A will be described with reference to the operation timing diagram of FIG. 3B.

First, as shown in FIG. 2, the data output buffer 300 outputs data of "high" or "low" level to the output terminal when the CON2 signal is "high", and when the CON2 signal is "low". The output stage is 1/2 Vcc with high impedance.

As shown in FIG. 1B, the input buffer outputs the address signals AXn and / AXn by latching a signal input from the outside as compared with the reference voltage when the CON1 signal transitions from the "low" level to the "high" level. Done.

Accordingly, in FIG. 3A, while CON1 is "low", CON3 is "high", so the NMOS transistor MN is turned on to store charge in the capacitor 700. At this time, the data output node is in the high-impedance state and is 1/2 Vcc, so the reference voltage level is 1/2 Vcc.

When the DRAM starts to operate and CON1 goes to "high", the input buffer 200 of FIG. 1B operates and the delay unit 500 maintains the "high" state. The CON3 drops to "low" before CON2 becomes "high" as shown in FIG. 3B. When CON2 becomes "high", the data output buffer 300 operates so that the data output terminal is "high" or "." Low "level.

In summary, when CON2 is "low", the data output buffer 300 is in a high-impedance state, and in this case, the NMOS transistor MN is turned on to store charge in the capacitor 700, where CON3 is "high". "State.

After that, when CON2 is "high", the data output buffer 300 operates, and since the data output stage at this time is at the "high" or "low" level, CON3 falls to the "low" level before the CON2. The NMOS transistor MN is turned off.

As a result, in this way, the voltage when the data output terminal is in the high-impedance state is used as the reference voltage (Vref), and when the level of the data output terminal is changed, it turns off between the data output terminal and the input buffer 200 using the reference voltage. The same function can be performed without using the reference voltage generation circuit 100.

As described above, the present invention can generate a reference voltage using only a simple circuit without using a reference voltage generating circuit separately, so that the area of the reference voltage generating circuit can be reduced in the layout, and the data input / output terminal from the outside. There is an effect that can reduce unnecessary power consumption by using a voltage that is always applied.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, substitutions and additions will be possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (3)

An input buffer operating by the first signal and outputting an address signal; A reference voltage generator of a semiconductor memory device comprising a data output buffer controlled by a second signal and outputting predetermined data, Connected between the data output buffer output terminal and the input buffer input terminal and operated by the first signal to turn on when the data output buffer is in a high-impedance state to use the potential of the data output buffer output terminal, And a connecting means for cutting off the potential of the output terminal of the data output buffer when the data output buffer is in operation. The method of claim 1, The connecting means includes inverting means for receiving the first signal; Delay means for delaying the output signal of the inversion means until the second signal is enabled and outputting a third signal; Transfer means operating by the third signal to transfer a high-impedance potential of the data output buffer; And a capacitor connected between one side terminal of the transfer means and a ground voltage terminal to store charges transferred by the transfer means. The method of claim 2, The transfer means is a reference voltage generator of the semiconductor memory device, characterized in that the MOS transistor.