JPS63113892A - Output circuit - Google Patents

Abstract

PURPOSE:To already complete driving of an output buffer at the time of accessing an OE and to access the OE at a high speed by providing a transfer TR between the output of the output buffer and an output transistor (TR) and driving the transfer TR with the voltage of an OE type power source voltage or above. CONSTITUTION:The output buffer of an output circuit is driven beforehand, and a transfer TR is provided between the output of the output buffer and the gate of an output TR. To a block C the output buffer to output a data output Dout of the constitution, an output buffer by a block B and a clock generator by a block A are connected. The signal of the voltage value of the power source voltage or above inputted to the gate of a transfer TRQ1 of the block C by the block A is generated and outputted. From the block B, output signals phiout and -phiout of the output buffer are added to transfers TR1 and TR2. At the time of the OE access, the driving time of the output buffer is not included and the OE access is executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a common input/output terminal method (
(1) This relates to an output circuit whose output is controlled by an external signal OE in the case of 10 commons.

Prior Art A conventional output circuit is shown in FIG. The output buffer is OE (
Output enable: Output φ driven by active signal of 0output enable) system. ut Nφ.

Outputs 0°. The output of these output sofas is connected to the gate of an output transistor consisting of a first transistor whose source is connected to the power supply voltage and whose drain is connected to the node N2, and a second transistor whose source is connected to the node N2 and whose drain is connected to the ground voltage. Directly connected. That is, the output φ
. , is the output φ to the gate of the first transistor. ut
is connected to the gate of the second transistor. Output from node N2. ut is output.

In this manner, in the conventional output circuit, the output buffer and the output transistor are directly connected, and the drive of the output buffer is triggered by an OE-based active signal that controls the output.

Problems to be Solved by the Invention In the conventional output circuit described above, the output buffer starts to be driven only after the signal ○E becomes active low. In this way, the output buffer driving time is included in the OE access time, which has been an obstacle to speeding up the OE access.

Means for Solving the Problems In order to solve the above problems, the present invention connects a transfer transistor between the output buffer circuit and the output transistor, with its drain connected to the output buffer circuit and its source connected to the gate of the output transistor. By providing a buffer circuit, transmission of the output signal of the output buffer circuit to the output transistor is controlled. The transfer transistor is driven by applying a signal higher than the power supply voltage to the gate.

- Production J As shown in FIG. 1, in the present invention, the output buffer is operated in advance, and a transfer transistor is provided between the output of the output buffer and the gate of the output transistor. Then, the transfer transistor is driven by an OE system active signal having a power supply potential or higher. In such a configuration, the output φ of the output buffer at the time of OE access.

ut　/φ. . .

Whether it is high or low has already been determined, so as soon as the gate of the transfer transistor goes high, the output φ of the output buffer is applied to the gate of the output transistor. ut/φ. ut information is transmitted. Then, the output transistor is driven and output information is output. In this way, the circuit configuration does not include the drive time of the output buffer in the OE access time.
E-access can be made faster.

Example The present invention will be explained below based on examples.

FIG. 3 shows an embodiment in which the circuit of the present invention shown in FIG. 1 is specifically constructed. FIG. 4 shows the principle of operation of this embodiment. The circuit shown in FIG. 3 can be roughly divided into three blocks.

Block A is a clock generator that generates a signal having a voltage value higher than the power supply voltage input to the gate of the transfer transistor. This block A consists of a transistor Qll whose drain is connected to the power supply potential, its gate to the signal φOE', and its source to the node N3; Q12, a transistor Q13 whose drain is connected to the node N3, whose gate is connected to the node N4, and whose source is connected to the ground potential, whose drain is connected to the power supply potential, and whose gate is connected to the CAS system precharge signal P. , a delay circuit including a transistor Q14 whose source is connected to the node N4, a transistor Q15 whose drain is connected to the node N14, whose gate is connected to the node N3, and whose source is connected to the ground potential; A transistor Q16 has a drain connected to the node N5, a gate connected to the power supply potential, a transistor Q17 whose drain is connected to the signal φOE'', a source connected to the node N6, a gate connected to the node N5, a drain connected to the node N6, a source connected to the ground potential, and a gate connected to the node N5. A transistor 01g connected to the RAS system precharge signal PR, a transistor QO whose drain is connected to the node N6, whose source is the ground potential, and whose gate is connected to the output stop signal φ.2, whose drain is the power supply potential, and whose source is the node N7, A transistor Qi9 whose gate is connected to node N6, a capacitance CO between nodes N6 and N7, and a transistor Q20 whose drain is connected to node N7, source is ground potential, and gate is connected to node N4.
and a signal generating section having these as constituent elements. A signal φ is output from the node N6.

Block B is the output buffer. signal φ. . 2,φ.

Output ut.

Block C is the output section. The source of this block C is the signal φ. 1, a transfer transistor Q1 whose gate is the signal φ2 from the block A, whose drain is connected to the node N8, and whose source is the signal φ. .

A transfer transistor Q2 has a gate connected to a signal φ6, a drain connected to a node N9, a drain connected to a node N8,
The source is the ground potential, and the gate is the output stop signal φ. 1. A transistor Q3 is connected to the node N9 at its drain, a ground potential at its source, and an output stop signal φ at its gate. 4. an output transistor Q5 whose drain is connected to the power supply potential, whose source is connected to the node NIO, and whose gate is connected to the node N8; and an output transistor Q6 whose drain is connected to the node NIO, whose source is connected to the ground potential, and whose gate is connected to the node N9. It consists of. An output Dout is output from the node NIO. Transistors Q3 and Q4 are transistors that set the gates of output transistors Q5 and Q6 to low upon reset, and make the output terminals high impedance.

The operation of the above circuit will be explained with reference to the waveform diagram shown in FIG. At the time of OE access, the output buffer has already been driven and its output φ. ut/φ. 1. It has already been decided whether it will be Ha High or Low.

In the precharge state, the signal φop' is low and the precharge signal P. SPR is high. In this case, the node N3 is low, the node N4 is high, and the node N6 is low. Therefore, the signal φ is low. Here, when the precharge signal PcSPR becomes low and the output control signal ○E from the outside becomes active low, the OE system is driven and the output stop signal φ is activated. , F become low, and the OE system active signal φ. 6' goes high. Then, node N3 changes from low to high, and then, in response to the change in node N3, node N4 changes from high to low. signal φ. Utilizing this delay time until a change in 1 leads to a change in node N4, the potential at node N6 changes from 0 to 5, and the current capability ratio of transistors Q19 and Q20 and the couple capacitance CO
Due to the boot effect of , the voltage changes to a high level of about 5■ to 6■, which is higher than the power supply potential.

In this way, a signal φ6 higher than the power supply potential is output. Transfer transistors Ql and Q2 open when a signal φ higher than the power supply voltage is input to their gates. As a result, output transistors Q5 and Q6 are driven and output D6ut is output.

When the external output control signal OE is reset to high, the output stop signal φ is generated. 1. Since the signal φ becomes high, the signal φ is pulled by the transistor QO, and the signal φ becomes low. As a result, transfer transistor QISQ2 is closed. At the same time, a high level output stop signal φ is applied to each gate. Transistors Q3 and Q4 to which PF is input are turned on. Therefore, the gates of the output transistors Q5 and QFi become low level, and the output transistors Q5 and Q6 are turned off. Therefore, the output terminal becomes high impedance.

In the output circuit of the present invention, since the output transistor is driven through the transfer transistor, it is difficult to maintain the gate potential of the output transistor at a level sufficient for long-term hold.

To solve this problem, it is necessary to connect an active pull-up circuit driven by a clock signal to its gate.

Effects of the Invention In the output circuit of the present invention, a transfer transistor is provided between the output of the output buffer and the gate of the output transistor. Output control is performed by driving this transfer transistor with an active signal higher than the power supply voltage of the OE system. In this method, the output buffer is already driven at the time of OE access, and it is only necessary to turn the gate of the transfer transistor high, so that the OE access can be made faster than in the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an output circuit of the present invention, FIG. 2 is a schematic diagram of a conventional output circuit, FIG. 3 is a diagram showing an embodiment of the output circuit of the present invention, and FIG. 4 is a diagram representing the operating principle of the embodiment shown in FIG. 3. FIG. (Main reference numbers) QO~Q6, Qll~Q20...(field effect) transistor φ02%φ. E', φ,... OE system active signal φO
FF...Output stop signal φ. ut sφout ・・Output buffer output signal P, ・RAS system precharge signal P, ・CAS system precharge signal Dout ・
・Data output N1 to NIO... Node Figure 4

Claims (2)

[Claims] (1) By providing a transfer transistor between the output buffer circuit and the output transistor, with its drain connected to the output buffer circuit and its source connected to the gate of the output transistor, the output signal of the output buffer circuit is transmitted to the output transistor. An output circuit characterized by controlling. (2) The output circuit according to claim 1, wherein the high level of the drive signal of the transfer transistor is higher than the power supply voltage.