JPH02105391A - Precharging circuit - Google Patents

Abstract

PURPOSE:To perform the self-control of the precharging time and to avoid the collision against an address control signal by using a circuit which controls the gate signal of an FET of a precharging circuit with use of the voltage information on a 1st bit line and a gate control signal. CONSTITUTION:The Nch FET 1 - 3 are connected to a gate control circuit 4 as prescribed. When a gate control signal line 6 is kept at 'L', the output of the circuit 4 is set at 'L' with all FETs turned off. When the line 6 is kept at 'H', all FETs are turned on to precharge the 1st and 2nd bit lines 9 and 10. When the precharge voltage drops by one stage of the FET gate, the voltage information is inputted to the circuit 4 through a feedback line 5. Thus the circuit 4 drops its output to 'L' despite the input of a control signal and turns off each FET. The threshold voltage VT and the length and the width of a gate of each FET are changed for selection of the precharge voltage level and the precharging speed. In such a constitution, the precharging time can be self-controlled and therefore the collision is avoided between the gate and address control signals.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a precharge circuit, and particularly to a precharge circuit for random access memory (RAM) and read-only memory 'J (
This invention relates to precharge circuits used in ROM, etc.

[Conventional technology]

Conventionally, this type of precharge circuit, as shown in FIG.
MOS) The drain terminal of transistor 1 and the third MOS
) is connected to the source terminal of the transistor 3 and to the first bit line 9, and is also connected to the drain terminal of the second MOS transistor 2 and the third MOS transistor 3.
and the second pin (bi).
t) 10 lines, and a gate control signal ls6 was connected to each gate terminal of the first to third MOS transistors 1.2.3.

[Problem to be solved by the invention]

In the conventional precharge circuit described above, as shown in FIG. 4, the gate control signal on the gate control signal line 6 is generated using a half cycle of the clock. Therefore, at clock change point 11, a collision occurs between the gate control signal and the address control signal (described later), causing unnecessary current to flow from the precharge circuit, and it takes a long time for the memory data to stabilize. There are some drawbacks.

Furthermore, the time required for precharging is unclear, and generally a margin is provided for the precharging time.

Therefore, there is a drawback that when operating the RAM and ROM at high speed, the speed cannot be increased by the margin of the precharge time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a precharge circuit which solves the above drawbacks and operates at high speed without unnecessary current flowing.

[Failure to solve the problem]

The configuration of the precharge circuit of the present invention is as follows. 2nd, 3rd
transistors, and a gate control circuit that controls the gate terminals of these transistors, the first terminals of the first transistor and the second transistor are each connected to a power supply, and the first terminal of the first transistor and the second transistor are connected to a power supply. a second terminal of the second transistor and a first terminal of the third transistor are commonly connected and connected to a first bit line; are commonly connected and connected to the second bit line, and the first... Second. A gate terminal of the third transistor is connected to the output of the gate control circuit, and a feedback line connected to the first bit line and a gate control signal line are connected to the input of the gate control circuit. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a self-controlled precharge circuit according to a first embodiment of the present invention. In FIG. 1, the self-controlled precharge circuit of this embodiment connects the source terminal of a first MOS transistor 1 and the source terminal of a second MOS transistor 2 to a power supply voltage (Vcc), and The drain terminal of the first MOS transistor 1 is connected to the third M
It is connected to the source terminal of the OS transistor 3 and the first
The drain terminal of the second MOS transistor 2 is connected to the drain terminal of the third MOS transistor 3 and also to the second bit line 1°. Second. 3rd MOS) transistor 1. 2. The gate terminal 3 is connected to the output of the gate control circuit 4, and the feedback line 5 connected to the first bit line 9 and the gate control signal 1Is6 are connected to the input of the gate control circuit 4.

By including and configuring the circuit elements as described above, it becomes a precharge circuit in a memory circuit.

Here, the gate control circuit 4 controls the first degree, the second degree, and the like by a gate control signal input from the gate control signal line 6. A signal is generated to control the gate of the third MOS transistor, and when the voltages of the first bit line and the second bit line reach optimum values, the information is sent to the gate control circuit 4 through the feedback line 5. was sent, and the first. Second. Third
It has the function of turning off the gate signal of the MOS transistor.

In addition, the first MOS transistor 1, the second MOS transistor 2, and the third MO8I transistor 3 are N
Channel MOS) transistor or P channel MO8I
- Consists of transistors.

Generally, it is composed of N-channel MOS) transistors, so the following explanation will be based on the first. Second. A case will be described in which the third MOS transistors X1, 2, and 3 are constructed of Nf-type MOS transistors. When configured with a P-channel MOS transistor, the level of the gate control voltage is reversed.

In the gate control circuit 4, the signal on the gate control signal line 6 is “L”
At this time, the output of the gate control circuit 4 generates L" and keeps the first, second, and third MOS transistors 1, 2, and 3 in the OFF state. Next, when the gate control signal becomes H" , the output of the gate control circuit 4 generates HII, and the output of the first .
Second. Third MOS transistor t, 2.3 eON
K and precharges the first bit line 9 and second bit line 1o. When the precharge voltage drops by one stage of the gate of the transistor, the voltage information is inputted to the gate control circuit 4 through the feedback line 5. As a result, the gate control circuit 4 drops its output to 'L' even if the gate control signal is input, and the first, second, and third M
OS) Turn off transistor 1゜2.3.

The gate control circuit 4 is configured to perform the operations described above. By providing the gate control circuit 4 in the precharge circuit, the precharge time of the first bit line 9 can be self-controlled. Regarding the precharge voltage value and speed, see 1. 2nd, 3rd MOS) transistor 1
．． By changing ■T in 2.3, gate length, and gate width, arbitrary values can be obtained.

FIG. 2 is a circuit diagram showing a self-controlled precharge circuit according to a second embodiment of the present invention. In the figure, the precharge circuit of this embodiment includes an address control circuit 7 in the precharge circuit of FIG. In this embodiment, a case is shown in which the output signal of the gate control circuit 4 is used to generate an address control signal. The output signal of the gate control circuit 4 and the signal of the address control signal line 8 are input to the input of the address control circuit 7 . The address control circuit 7 creates a new address control signal for the address control line 12 using these two signals. This address control signal is applied to RAM or ROM.
address enable signal. Gate control circuit 4
can self-control the precharge time of the first bit line 9 and the second bit line 10 to the necessary minimum.

Therefore, even within the time previously required for precharging,
If the output of the gate control circuit 4 is used, an address control signal can be generated, and there is an advantage that there is no need to consider the time required for precharging in the design.

〔Effect of the invention〕

As explained above, the present invention includes a gate control circuit that controls the gate signal of the MO8I-transistor used in the precharge circuit using the voltage information of the first bit line and the gate control signal in the conventional precharge circuit. By providing this, it is possible to self-control the precharge time, thereby creating a margin in the conventional precharge time, and having the effect of avoiding collision between the gate control signal and the address control signal. Furthermore, in the present invention, when the address control signal is generated using the output of the gate control circuit, the address control signal can be generated within the time conventionally required for precharging, and the precharging time at that time is It has the effect that there is no need to consider it.

Dopatsu line, 6... Gate control signal line, 7...
... Address control circuit, 8 ... Address control signal line, 9 ... First bit line, 1o ...
...Second bit line, 11... Change point, 12
...Address control line.

Agent: Patent Attorney Susumu Uchihara

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a precharge circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a precharge circuit according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a precharge circuit according to a second embodiment of the present invention. FIG. 4 is a circuit diagram showing a circuit diagram, and FIG. 4 is a waveform diagram showing a waveform of a gate control signal. l...First MOS transistor, 2...
... second MOS transistor, 3 ... third MOS transistor, 4 ... gate control circuit,
5...Fee rod fertilization 4 times

Claims (1)

[Claims] comprising first, second, and third transistors, and a gate control circuit that controls gate terminals of these transistors,
First terminals of the first transistor and the second transistor are each connected to a power source, and a second terminal of the first transistor and a first terminal of the third transistor are commonly connected, and a first bit line, a second terminal of the second transistor and a second terminal of the third transistor are commonly connected and also connected to a second bit line; 2. Connect the gate terminal of the third transistor to the output of the gate control circuit, and
A precharge circuit characterized in that a feedback line connected to the bit line of the gate control circuit and a gate control signal line are connected to an input of the gate control circuit.