JPS62117366A - Manufacture of amorphous silicon image sensor - Google Patents
Manufacture of amorphous silicon image sensorInfo
- Publication number
- JPS62117366A JPS62117366A JP60256531A JP25653185A JPS62117366A JP S62117366 A JPS62117366 A JP S62117366A JP 60256531 A JP60256531 A JP 60256531A JP 25653185 A JP25653185 A JP 25653185A JP S62117366 A JPS62117366 A JP S62117366A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- electrode
- lower electrode
- image sensor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 11
- 239000011229 interlayer Substances 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Facsimile Heads (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
アモルファスシリコンイメージセンサ・の製造方法であ
って、下部電極をマスクとして基板をエツチングし、基
板に段差を設けることにより、その上に形成されるａ−
ｓ ｉ膜を各素子毎に電気的分離することができ、厳密
な”ｌスフ合わせを不要とし、工程の簡易化を可能とす
る。Detailed Description of the Invention [Summary] A method for manufacturing an amorphous silicon image sensor, in which a substrate is etched using a lower electrode as a mask, and a step is formed on the substrate.
The Si film can be electrically isolated for each element, eliminating the need for strict alignment and simplifying the process.
本発明は、ファクシミリ、光学文字読取り装置などに用
いられるアモルファスソリごＩンイメージセンサの製造
方法に関するものである。The present invention relates to a method of manufacturing an amorphous solid-line image sensor used in facsimiles, optical character reading devices, and the like.
第３図は従来のアモルファスシリコンイメージセンサを
示す図であり、ａは平面図、ｌ）はａ図のｂ−ｂ線にお
ける断面図である。FIG. 3 is a diagram showing a conventional amorphous silicon image sensor, in which a is a plan view and l) is a cross-sectional view taken along line bb in FIG.
同図において、１はガラス基板、２ば下部電極（透明又
は不透明）、３はＰｉｎ−ａ−ｓｉ膜、４は層間絶縁膜
、５は上部共通電極である。In the figure, 1 is a glass substrate, 2 is a lower electrode (transparent or opaque), 3 is a Pin-a-Si film, 4 is an interlayer insulating film, and 5 is an upper common electrode.
この従来のアモルファスシリコンイメージセンサの製造
方法は先ず基板１に各素子毎の下部電極２をエツチング
法又はホトリソグラフィ法で形成する。次に全面にＰｉ
ｎ−ａ−ｓｉ膜を形成し、バターニングして各下部電極
上にＰｉｎ−ａ−ｓｉ膜３を形成する。In this conventional method of manufacturing an amorphous silicon image sensor, first, a lower electrode 2 for each element is formed on a substrate 1 by an etching method or a photolithography method. Next, Pi
A na-a-si film is formed and patterned to form a pin-a-si film 3 on each lower electrode.
次に下部電極２と上部電極５とを絶縁するための層間絶
縁膜４を形成し、窓あけした後、上部共通電極５を形成
するのである。Next, an interlayer insulating film 4 is formed to insulate the lower electrode 2 and the upper electrode 5, and after opening a window, the upper common electrode 5 is formed.
上記従来の製造方法では、Ｐｉｎ−ａ−８ｉ膜をバター
ニングするときに下部電極との厳密なマスク合わせを必
要とするという欠点があった。The conventional manufacturing method described above has a drawback in that strict mask alignment with the lower electrode is required when patterning the Pin-a-8i film.
本発明はこのような点に鑑Ｚｌで案出されたもので、厳
密なマスク合わ・１を必要と・）１ず、］稈がｆｉｎ車
なアモルファスシリコンイメージ・Ｌ！ンザの製造方法
を桿供することを「１的と１−７゛こいる。The present invention was devised in consideration of these points, and requires strict mask matching. Providing information on the manufacturing method for danza is said to be ``one target and 1-7 degrees''.
このため本発明においては、基板１ｏ−１−に素子毎の
下部電極１１を形成する工程と、該下部電極１１をマス
クとして基板１ｏをエツチングし、下部電極１１の周辺
部に段差部１０ａを形成する工程と、該段差部１０ａを
含んで基板１ｏ及び下部電極１１上に連続したＰｉｎ−
ａ−ｓｉ膜を形成する工程と、該Ｐｉｎ−ａ−ｓｉ膜１
２にに上部共１Ｊ１１電極１３を形成する工程とより成
ることを特徴としている。Therefore, in the present invention, the steps include forming a lower electrode 11 for each element on the substrate 1o-1-, etching the substrate 1o using the lower electrode 11 as a mask, and forming a stepped portion 10a around the lower electrode 11. A continuous Pin-
Step of forming an a-si film and the Pin-a-si film 1
The method is characterized in that it consists of a step of forming 1J11 electrodes 13 on both the upper and lower parts.
下部電極をマスクにして基板をエツチングし段差部を形
成することにより、その上に形成されるＰｉｎ−ａ−ｓ
ｉ膜に高抵抗部分をｔ［ぜしめ、各素子−毎の電気的分
離が可能となる。By etching the substrate using the lower electrode as a mask and forming a stepped portion, the Pin-a-s formed thereon.
By adding a high resistance portion to the film, electrical isolation of each element becomes possible.
第１図は本発明の詳細な説明するための図であり、ａ
’％’ Ｃはその工程を説明する図である。FIG. 1 is a diagram for explaining the present invention in detail, and a
'%' C is a diagram explaining the process.
本実施例のアモルファスシリコンイメージセンサの製造
方法は１．先ず第１図ａに示すようにガラス基板１０１
にホトリソグラフィ法を用いて下部電極１１を形成し、
これをマスクとしてガラス基板１０のエツチングをウェ
ット法により行なう。The manufacturing method of the amorphous silicon image sensor of this example is 1. First, as shown in FIG. 1a, a glass substrate 101 is
A lower electrode 11 is formed using a photolithography method,
Using this as a mask, the glass substrate 10 is etched by a wet method.
これにより下部電極１１の外周に沿って基板１０に段差
部１０ａが形成される。次にＰｉｎ−ａ−ｓｉ膜を基板
１０の全面に形成し、第１図すのようにダイオード部分
にストライブでバターニングする。従ってこの場合のＰ
ｉｎ−ａ−ｓｉ膜１２は各下部電極１１上に連続したか
っこうで形成されるため厳密なマスク合ね廿を必要とし
ない。最後に第１図ＣのようにＰｉｎ−ａ−ｓｉ膜１２
トに上部共通電極１３を形成するのである。As a result, a stepped portion 10a is formed on the substrate 10 along the outer periphery of the lower electrode 11. Next, a Pin-a-Si film is formed on the entire surface of the substrate 10, and the diode portion is patterned with stripes as shown in FIG. Therefore, in this case P
Since the in-a-si film 12 is formed in a continuous layer on each lower electrode 11, strict mask alignment is not required. Finally, as shown in FIG. 1C, the Pin-a-Si film 12
The upper common electrode 13 is formed on the top.
このようにして形成されたアモルファスシリコンイメー
ジセンサは、基板１０の段差部１０ａによって、Ｐｉｎ
−ａ−ｓｉ膜１２に高抵抗部分１２ａが生じ、Ｐｔｎ−
ａ−ｓｉ膜１２が連続していても各下部電極１１は電気
的に分離されたことになり、各素子はそれぞれ素子特性
を維持することができる。The amorphous silicon image sensor formed in this way has a pin
A high resistance portion 12a is generated in the -a-si film 12, and the Ptn-
Even if the a-si film 12 is continuous, each lower electrode 11 is electrically isolated, and each element can maintain its element characteristics.
このように本実施例によればＰｉｎ−ａ−ｓｉｌ’２１
２のパターンのマスク合わせが簡ｒｌｌ化され、１１つ
層間絶縁膜が不要となるため製造ブ１１セスが簡略化さ
れる。In this way, according to this embodiment, Pin-a-sil'21
The mask alignment of the second pattern is simplified, and eleven interlayer insulating films are not required, so the manufacturing process is simplified.
第２図は本発明の他の実施例を説明するための図である
。同図において第１図と同一・部分は同一符号を付して
示した。FIG. 2 is a diagram for explaining another embodiment of the present invention. In this figure, the same parts as in FIG. 1 are designated with the same reference numerals.
本実施例が前実施例と異なるところは、基板１０のエツ
チングをウェブＩ・法により行ない、それにより段差１
０ａにアンダーカットを生ゼし７め、Ｐｔｎ−ａ−ｓｔ
膜１２に高抵抗部分を形成し易くしたことである。なお
本実施例の効果は前実施例と同様である。This embodiment differs from the previous embodiment in that the substrate 10 is etched by the web I method, thereby reducing the level difference.
Create an undercut on 0a, 7th, Ptn-a-st
This makes it easier to form a high resistance portion in the film 12. Note that the effects of this embodiment are similar to those of the previous embodiment.
以上述べてきたように、本発明によれば、基板に設けた
段差によりＩ”１ｎ−ｎ−ｓｉ膜に高抵抗部分かできる
ことを利用してｔ”１ｎ−ａ−ｓｊ膜の電気的分離を行
なうことにより、厳密なマスク合わせを必要とせず、ま
た層間絶縁層が不要となるので、製造プロセスの簡易化
ができ、実用的には極めて有用である。As described above, according to the present invention, the electrical isolation of the t"1n-a-sj film is achieved by utilizing the fact that a high resistance portion is formed in the I"1n-n-si film due to the step provided on the substrate. This eliminates the need for strict mask alignment and eliminates the need for an interlayer insulating layer, which simplifies the manufacturing process and is extremely useful in practice.
第１図は本発明の詳細な説明するだめの図、第２図は本
発明の他の実施例を説明するための図、
第３図は従来のアモルファスシリコンイメージセンサを
示す図である。
第１図、第２図において
１０は基板、
１０ａは段差部、
】Ｉは下部電極、
１２はＰｉｎ−ａ−ｓｉ膜、
■３は−１一部共通電極である。
本発明の詳細な説明するための間
第１図
１２°°３ｐｉｎ−ａ−８ｉ膜
１２ｏ ・・・高抵抗部分
］３・・・上部共通電極
Ｙ七
［ｊ ｆｉ
。
ニ 写
麻
子
１ ・・・ガラス基板
２゛°・下部電極
３°゛°ｐｉｎ−ａ−８ｉ膜
４・・・層間絶縁膜
５・・・上部電極FIG. 1 is a diagram for explaining the present invention in detail, FIG. 2 is a diagram for explaining another embodiment of the present invention, and FIG. 3 is a diagram showing a conventional amorphous silicon image sensor. 1 and 2, 10 is a substrate, 10a is a stepped portion, ]I is a lower electrode, 12 is a Pin-a-Si film, and 3 is a -1 partial common electrode. 12°°3pin-a-8i film 12o...high resistance portion]3...upper common electrode Y7 [j fi
. D Shamako 1...Glass substrate 2゛°・Lower electrode 3゛°pin-a-8i film 4...Interlayer insulating film 5...Upper electrode
Claims (1)
形成する工程、 ｂ、上記下部電極（１１）をマスクにして基板（１０）
をエッチングし、下部電極（１１）周辺部に段差部（１
０ａ）を形成する工程、 ｃ、上記段差部（１０ａ）を含んで基板（１０）及び下
部電極（１１）に連続したＰｉｎ−ａ−ｓｉ膜（１２）
を形成する工程、 ｄ、上記Ｐｉｎ−ａ−ｓｉ膜（１２）上に上部共通電極
（１３）を形成する工程とより成ることを特徴とするア
モルファスシリコンイメージセンサの製造方法。 ２、上記基板（１０）のエッチングはドライエッチング
で行なうことを特徴とする特許請求の範囲第１項記載の
アモルファスシリコンイメージセンサの製造方法。 ３、上記基板（１０）のエッチングはウェットエッチン
グで行なうことを特徴とする特許請求の範囲第１項記載
のアモルファスシリコンイメージセンサの製造方法。[Claims] 1. a. Step of forming a lower electrode (11) for each element on the substrate (10); b. Using the lower electrode (11) as a mask, forming the lower electrode (11) on the substrate (10).
is etched to form a stepped portion (1) around the lower electrode (11).
Step 0a) of forming a Pin-a-Si film (12) that includes the stepped portion (10a) and is continuous to the substrate (10) and the lower electrode (11);
d) forming an upper common electrode (13) on the Pin-a-Si film (12). 2. The method of manufacturing an amorphous silicon image sensor according to claim 1, wherein the etching of the substrate (10) is performed by dry etching. 3. The method of manufacturing an amorphous silicon image sensor according to claim 1, wherein the etching of the substrate (10) is performed by wet etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60256531A JPS62117366A (en) | 1985-11-18 | 1985-11-18 | Manufacture of amorphous silicon image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60256531A JPS62117366A (en) | 1985-11-18 | 1985-11-18 | Manufacture of amorphous silicon image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62117366A true JPS62117366A (en) | 1987-05-28 |
Family
ID=17293915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60256531A Pending JPS62117366A (en) | 1985-11-18 | 1985-11-18 | Manufacture of amorphous silicon image sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62117366A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH049748U (en) * | 1990-05-14 | 1992-01-28 |
-
1985
- 1985-11-18 JP JP60256531A patent/JPS62117366A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH049748U (en) * | 1990-05-14 | 1992-01-28 |
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