JPS62117050A - Protocol processor - Google Patents

Abstract

PURPOSE:To reduce considerably the load of a device control processor by securing such constitution where the protocol processor of each layer performs independently each layer protocol and the protocol data is transferred only between the protocol processors of upper and lower layers. CONSTITUTION:The information (primitive information, etc.) such as the pointer information pointing out the data stored in a shared memory 3 as well as the primitive header part is delivered to a protocol processor 2 where the protocol of a layer is executed via an FIFO 22b. This FIFO 22b absorbs the difference of processing speed between adjacent protocol processors 2a and 2b and also attains the primitive queuing. A microcontrol part 21a for primitive information, etc. defines a register file 24 as a work area and uses a counter and a timer 25 as necessary to carry out its own layer protocol. Then the part 21a recompiles its own primitive information, etc. received previously for application to an upper protocol processor 2a or a lower protocol processor 2b to supply it to the processor 2a or 2b via an exclusive data route 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a protocol processor for executing a communication control procedure (protocol) having a hierarchical structure.

2. Description of the Related Art As a conventional protocol processor of this type, one shown in FIG. 3 is known. In Figure 3, 20
21 is a modem, and 21 is a line side interface unit, which corresponds to a part where physical protocols such as modem signal management are executed. Reference numeral 22 denotes a processor body consisting of a communication LSI, etc., which corresponds to the part where the data link protocol is executed.

23 is a memory connected to the system bus.

24 is a CPU interface section, which is an interface section between the network layer and the section where the application layer protocol is executed.

As represented by the protocol processor with the above configuration, for the lower two layers (physical layer, data link layer) of the conventional 08I (International Organization for Standardization) seven layers, there are dedicated processors that are fast and capable of assisting. For executing the proto-p of these upper layers (from the network layer to the application layer), a general-purpose CPU is required.
In most cases, the system bus of the CPU is used as the interface between the lower two layers and the upper layer.

Problems to be Solved by the Invention However, recently, as typified by LAN (Local Area Network), the conventional line speed has increased by 10%.
Lines at speeds 3 to 104 times faster have come into use, achieving line speeds sufficient to meet the demand for high-speed transfer of large amounts of data, such as computer files and facsimile images.

However, when looking at current communication control systems, (1) Protocol execution is performed using a general-purpose CP [
Relying on J.

(2) Since communication data flows through the system bus, it monopolizes the system bus and obstructs the flow of data (protocol data) that are not needed to execute the protocol.

Due to these factors, the overhead time required to execute the 7-layer protocol becomes large, and the time required for protocol processing becomes large compared to the actual transfer time of communication data, which hinders the realization of high-speed communication of large amounts of data. Ta.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a protocol processor capable of high-speed communication processing of a large amount of data.

Means for Solving the Problems In order to achieve the above object, the present invention provides a dedicated data path for exchanging primitive data between protocol processors in adjacent upper and lower layers, and a key link between protocol processors in each layer. The present invention is characterized in that it comprises: means for accessing a shared memory that can take a different structure; means for interfacing with a device control processor; and control means to which the dedicated data path is connected and controlling the access means and the interface means.

Effects With the above configuration, each layer's protocol is executed independently without regard to other layers, so the load on the device control processor is greatly reduced, making it possible to execute protocols at high speed and achieve high-speed transfer of large amounts of data. is realized.

Embodiment FIG. 1 is a schematic block diagram showing the main parts of a communication control system to which a protocol processor according to the present invention is applied.
2a and 2b are protocol processors of the present invention for executing protocols of each layer, of which 2a is an upper protocol processor and 2b is a lower protocol processor.

3 is a protocol processor 2.2a for each layer.

This memory pool 3 is a shared memory (memory pool) that can be accessed from the protocol processors of each layer. The data part is stored.

4 is a protocol processor 2a for both adjacent upper and lower layers;
, 2b is a dedicated data line 2 (primitive data, route) for exchanging primitives with 2b.

5 is the CPUI, protocol processor 2゜2a, 2
Communication data does not flow through this system bus 5; for example, operation command information to protocol processors 2.2a, 2b, processors 2.2a, 2b, etc. Only management data such as status notification information is transmitted.

An example of the specific internal structure of the protocol processors 2.2a and 2b is shown in FIG. 2 for the protocol processor 2.

In FIG. 2, reference numeral 21 denotes a control section that controls the operation of the entire protocol processor, and is composed of a microcontroller 21a, a microcode RAM 21b, and the like. Reference numeral 22 denotes an input/output mechanism section for exchanging and keying the header portion of primitives between the protocol processors 2a and 2b of the adjacent upper and lower layers, and is composed of an input/output mechanism section 22a, a FIFO (first-in first-out memory) 22b, etc. .

23 is a general-purpose interface for controlling interaction with the CPUI.
The CPU interface section 23a is a CPU interface section 23a, an input/output register section 23b, and the like. 24 is the microcontroller 2
A register file 25 is also used for the microcontroller 21a, and a memory access arbitration section 26 is provided so that the protocol processors of each layer can access the shared memory 3 without conflict.

The main functions of the protocol processor of the present invention having the above configuration are listed below.

(1) Protocol processor 2.2a for each layer.

2b is used only between adjacent protocol processors of both upper and lower layers (2.23 or 2.2b in the example of FIG. 1).
Primitive data is exchanged via the dedicated data path 4.

(2) Protocol processor 2*2 a for each layer
*2 b can be executed independently.

(3) The protocol is executed by the microcode RAM 2b inside each protocol processor 2.2a, 2b.
This is done by microcode read from.

Note that since this microcode is compatible with various protocol implementations, it can be downloaded from the microcode RAM 2 from an external memory (not shown) via a CPU, etc.
It is downloaded to b.

Next, the operation of the protocol processor based on this embodiment will be explained with reference to FIGS. 1 and 2.

First, when starting up the system, the microcode with the protocol implemented is downloaded from the CPU 1 side to the microcode RAM 2lb.

Information such as a header portion of a primitive and pointer information pointing to data in the shared memory 3 (hereinafter referred to as primitive information, etc.) is passed to the processor 2 that executes the layer protocol via the FIFO 22b.

This FIFO functions to absorb the difference in processing speed between the adjacent processors 2a and 2b and to realize primitive queuing.

The primitive information ring microcode 21a executes its own layer protocol using the register file 24 as a work area and using the counter and timer 25 as necessary.

On the other hand, the microcontroller 21a re-creates its own primitive information etc. received earlier for the upper or lower protocol processor 2a + 2b, and transfers this re-created data to the upper or lower protocol processor 2a + 2b. The data is sent to the protocol processors f2a, 2b via a dedicated data path (primitive data path) 4.

By repeating the above processing and operations, the protocol data is transmitted to each layer's protocol processor in turn, and the protocol of each layer is executed.

Incidentally, the protocol processor 2゜2a of each layer,
As is clear from the above, 2b is a specific CP
It has the ability to operate even if it is not U, and it has the ability to access only its own protocol.

Effects of the Invention As detailed above, according to the present invention, the protocol processors of each layer execute the layer protocols independently, and the protocol data is exchanged only between the protocol processors of both the upper and lower layers. , the load on the device control processor can be greatly reduced.

Also, since communication data does not flow on the system bus,
The load on the system bus is also reduced.

Therefore, compared to the conventional protocol implementation using a general-purpose CPU, there is an effect that a higher effective communication speed can be achieved.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing main parts of a communication control i#/system to which a protocol processor according to the present invention is applied, and FIG. 2 is a schematic block diagram showing an example of the internal structure of the protocol processor according to the present invention. Block Diagram FIG. 3 is a schematic block diagram showing a typical example of a conventional protocol processor. 1.-CPU (M location control processor), 2
, 2a. 2b...Protocol processor, 21...Control unit,
22... Input/output mechanism section, 23... General purpose interface section, 24... Register file, 25... Counter and timer, 26... Memory access arbitration section, 3... Shared memory, 4. ... Dedicated data path (primitive data path), 5... System bus. Name of agent: Patent attorney Toshio Nakao and 1 other person
Figure 1 / CPU (Jh'mJH5-2q・
Monument worri old Eshishi (〕〕Machi Nomitifute ° Nitaken S System bus figure 3

Claims (1)

[Claims] A protocol processor that executes a communication control procedure with a hierarchical structure, and can have a dedicated data path for exchanging primitive data between adjacent upper and lower layer protocol processors, and a queue structure between the protocol processors of each layer. a means of accessing shared memory;
A protocol processor comprising: an interface means for an apparatus control processor; and a control means connected to the dedicated data path and controlling the access means and the interface means.