JPS6416046A - Protocol converter and its operation control system - Google Patents

Protocol converter and its operation control system

Info

Publication number
JPS6416046A
JPS6416046A JP62172151A JP17215187A JPS6416046A JP S6416046 A JPS6416046 A JP S6416046A JP 62172151 A JP62172151 A JP 62172151A JP 17215187 A JP17215187 A JP 17215187A JP S6416046 A JPS6416046 A JP S6416046A
Authority
JP
Japan
Prior art keywords
code
hierarchy
associative memory
count means
token
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62172151A
Other languages
Japanese (ja)
Other versions
JPH0547148B2 (en
Inventor
Tsunesuke Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62172151A priority Critical patent/JPS6416046A/en
Priority to AU18931/88A priority patent/AU607516B2/en
Priority to EP88111037A priority patent/EP0298520B1/en
Priority to US07/217,198 priority patent/US4916660A/en
Priority to DE3851796T priority patent/DE3851796T2/en
Publication of JPS6416046A publication Critical patent/JPS6416046A/en
Publication of JPH0547148B2 publication Critical patent/JPH0547148B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To reduce the processing time by supplying selectively each code of a token to an associative memory means of a hierarchy commanded by a logical control means and to a code count means. CONSTITUTION:An associative memory 120 and a code count means 130 are prepared for each hierarchy and the hierarchy code is found out by using a table memory (logic control means 140) monitoring the status transition from a nest bit signal and a carry signal outputted from them. Then the selector switch means 110 selects the associative memory 120 and the code count means 130 depending on the hierarchy code and inputs the input code to a proper hierarchy associative memory 120 and a code count means 130. Thus, the token inputted consecutively is processed in real time and its processing time is reduced.
JP62172151A 1987-07-09 1987-07-09 Protocol converter and its operation control system Granted JPS6416046A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62172151A JPS6416046A (en) 1987-07-09 1987-07-09 Protocol converter and its operation control system
AU18931/88A AU607516B2 (en) 1987-07-09 1988-07-11 Nest level judging hardware device for high speed message handling systems
EP88111037A EP0298520B1 (en) 1987-07-09 1988-07-11 Device capable of judging a nest level at a high speed
US07/217,198 US4916660A (en) 1987-07-09 1988-07-11 Nest level judging hardware device for high speed message handling systems
DE3851796T DE3851796T2 (en) 1987-07-09 1988-07-11 Device for high-speed decision of the nesting level.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62172151A JPS6416046A (en) 1987-07-09 1987-07-09 Protocol converter and its operation control system

Publications (2)

Publication Number Publication Date
JPS6416046A true JPS6416046A (en) 1989-01-19
JPH0547148B2 JPH0547148B2 (en) 1993-07-15

Family

ID=15936511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62172151A Granted JPS6416046A (en) 1987-07-09 1987-07-09 Protocol converter and its operation control system

Country Status (1)

Country Link
JP (1) JPS6416046A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6163139A (en) * 1984-09-04 1986-04-01 Nippon Telegr & Teleph Corp <Ntt> Communication protocol controller
JPS62117050A (en) * 1985-11-15 1987-05-28 Matsushita Graphic Commun Syst Inc Protocol processor
JPS62252242A (en) * 1986-04-25 1987-11-04 Fujitsu Ltd Data transmission/reception system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6163139A (en) * 1984-09-04 1986-04-01 Nippon Telegr & Teleph Corp <Ntt> Communication protocol controller
JPS62117050A (en) * 1985-11-15 1987-05-28 Matsushita Graphic Commun Syst Inc Protocol processor
JPS62252242A (en) * 1986-04-25 1987-11-04 Fujitsu Ltd Data transmission/reception system

Also Published As

Publication number Publication date
JPH0547148B2 (en) 1993-07-15

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