JPH05276222A - Communication control processor - Google Patents

Abstract

PURPOSE:To perform fast communication processing on large amount of data by providing a dedicated route which directly transfers header information and pointer information between adjacent communication control processing means at upper and lover layers. CONSTITUTION:The pointer information indicating the header part of primitive and data in common memory 3, etc., are delivered from a CPU 1 to a protocol processor 2. Such primitive information, etc., is interpreted by the microcontrol part of the processor 2, and its own layer protocol is executed. Received its own primitive information, etc., is re-generated to the one for a high-order or low-order protocol processor 2a or 2b, and it is transferred to the processor 2a or 2b via a private data line 4. Thereby, the protocol processor at each layer executes the layer protocol independently, respectively, which reduces burden on a device control processor and a system bus. Therefore, fast execution communication speed can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control processing device for executing a communication control procedure (protocol) having a hierarchical structure.

[0002]

2. Description of the Related Art As a conventional communication control processing device of this type, a device shown in FIG. 3 is known. In FIG. 3, reference numeral 20 denotes a modem 21 and an interface unit on the line side.
It corresponds to a part where a physical protocol such as management of a modem signal is executed. Reference numeral 22 denotes a processor main body composed of a communication LSI or the like, and corresponds to a portion for executing the data link protocol. A memory 23 is connected to the system bus. Reference numeral 24 denotes a CPU interface section which is an interface section with a section where the protocol of the application layer is executed from the network layer.

As represented by the protocol processor having the above structure, the lower two layers (physical layer, data link layer) of the conventional OSI (International Organization for Standardization) 7 layers
There is a dedicated processor that can operate at high speed, but for the execution of these higher layer (network layer to application layer) protocols,
It is realized by software with a general-purpose CPU, and as an interface unit between the lower 2 layer and the upper layer,
Most of them used the system bus of the CPU.

[0004]

[Problems to be Solved by the Invention] However, recently,
As represented by LANs (Local Area Networks), high-speed lines 10 ³ to 10 ⁴ times faster than conventional line speeds have come to be used. For example, large-capacity data such as electronic computer files and facsimile images can be transferred. Sufficient line speed has been achieved to meet the demand for high speed transfer.

However, regarding the current communication control system, (1) The protocol execution depends on the general-purpose CPU as described above.

(2) Since the communication data flows through the system bus, it occupies the system bus and hinders the flow of data (protocol data) for executing the protocol. As a result, the overhead time for executing the 7-layer protocol becomes large, the time required for protocol processing becomes large compared to the actual transfer time of communication data, and realization of high-speed communication of a large amount of data is hindered. Was there.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a communication control processing device capable of high-speed communication processing of a large amount of data.

[0008]

In order to achieve the above object, the present invention comprises a plurality of communication control procedure processing means for independently executing a communication control procedure having a hierarchical structure for each hierarchy.
A system path through which the management information of the communication control procedure processing means is input / output, header information indicating the content of the communication control procedure to be executed independently of this system path, and a pointer of data executed by this header information. And a dedicated path for directly passing information to and from the communication control procedure processing means on both upper and lower layers adjacent to each other.

[0009]

With the above construction, the protocol of each layer is executed independently of the other layers, so the load on the device control processor is greatly reduced, high-speed execution of the protocol becomes possible, and a large amount of data can be stored. High-speed transfer is realized.

[0010]

1 is a schematic block diagram showing a main part of a communication control system to which a communication control processing device according to the present invention is applied, in which 1 is a CPU for controlling the entire communication control system,
2, 2a and 2b are protocol processors for executing the protocol of each layer, of which 2a is an upper protocol processor and 2b is a lower protocol processor. 3 is a protocol processor of each layer 2, 2a, 2
b and a shared memory (memory pool) accessible from the CPU 1, the memory pool 3 has a structure capable of forming a queue structure between protocol processors of each layer, and all data portions common to the protocol processors of each layer. Is stored.

Reference numeral 4 denotes a dedicated data path (primitive data path) for exchanging primitives between the protocol processors 2a and 2b of the upper and lower layers adjacent to each other.

Reference numeral 5 denotes a system bus provided in such a manner as to be connected to the CPU 1, the protocol processors 2, 2a and 2b, and the shared memory 3, respectively. Communication data does not flow to the system bus 5, and, for example, the protocol processors 2, 2
a, 2b operation command information and processors 2, 2a, 2b
Only the management data such as the status notification information of is flowed.

FIG. 2 shows the protocol processors 2, 2
An example of a concrete internal structure of a and 2b is shown for the protocol processor of reference numeral 2.

In FIG. 2, reference numeral 21 is a control unit for controlling the operation of the entire protocol processor, which is composed of a micro control unit 21a, a micro code RAM 21b and the like.
22 is a protocol processor 2 of both upper and lower layers adjacent to each other.
An input / output mechanism unit for transmitting and receiving the head portion of the primitive between a and 2b and for queuing, and includes an input / output control unit 22a and a FIFO (first-in first-out memory) 22b. A general-purpose interface unit 23 controls the dialogue with the CPU 1, and includes a CPU interface unit 23a and an input / output register unit 23b. Reference numeral 24 is a register file for the micro control unit 21a, 25 is a counter and timer for the micro control 21a, and 26 is a memory access provided so that the shared memory 3 can be accessed without competition between protocol processors of respective layers. It is the Arpitation Department.

The main functions of the communication control processing device of the present invention having the above configuration are listed below.

(1) The protocol processors 2, 2a, 2b of the respective layers are connected via the dedicated data path 4 only between the protocol processors of the upper and lower layers adjacent to each other (2, 2a or 2, 2b in the example of FIG. 1). To send and receive primitive data.

(2) The protocol processors 2, 2a and 2b of each layer can be independently executed.

(3) Execution of the protocol processor
It is performed by the microcode read from the microcode RAM 2b inside each protocol processor 2, 2a, 2b. Since this microcode can support various protocol implementations, the CPU1
Etc. via an external memory (not shown) to the microcode RAM 2b.

Next, the operation of the communication control processing device according to this embodiment will be described with reference to FIGS. 1 and 2.

First, when the system is started up, the microcode implemented with the protocol is downloaded from the CPU 1 side to the microcode RAM 21b.

For the processor 2 in which the layer protocol processor is executed, the header portion of the primitive and pointer information indicating the data in the shared memory 3 (hereinafter referred to as primitive information) is stored in the FIFO 2.
Passed via 2b. This FIFO functions to absorb the difference in processing speed between the adjacent processors 2a and 2b and realize the queuing of primitives.

The primitive information and the like are interpreted by the micro controller 21a, the register file 24 is used as a work area, and the counter and timer 2 are used as necessary.
5 to execute the own layer protocol.

Then, the micro control unit 21a re-creates its own primitive information received earlier for the upper or lower protocol processors 2a and 2b, and re-creates the re-created data into the upper or lower data. It flows to the lower protocol processors 2a and 2b through a dedicated data path (primitive data path) 4.

By repeating the above-described processing and operations, the protocol of the next layer is executed as the protocol data.

The protocol processors 2, 2a and 2b of the respective layers are, as is clear from the above description,
It has a function to operate even if it is not a specific CPU, and has a function to access only the primitive header of its own protocol.

[0026]

As described in detail above, according to the present invention,
The protocol processor of each layer independently executes the layer protocol, and the protocol data is exchanged between the protocol processors of both upper and lower layers, so that the load on the device control processor can be greatly reduced.

Further, since the communication data does not flow on the system bus, the load on the system bus can be reduced.

Therefore, as compared with the conventional protocol implementation using a general-purpose CPU, there is an effect that a higher execution communication speed is achieved.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a main part of a communication control system to which a communication control processing device according to an embodiment of the present invention is applied.

FIG. 2 is a schematic diagram showing an example of an internal structure of a communication control processing device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing a representative of a conventional communication control processing device.

[Explanation of symbols]

 1 CPU (device control processor) 2 protocol processor 2a protocol processor 2b protocol processor 3 shared memory 4 dedicated data path (primitive data path) 5 system bus 21 control section 22 input / output mechanism section 23 general-purpose interface 24 register file 25 counter and timer 26 Memory access arbitration unit

Claims (1)

[Claims] 1. A plurality of communication control procedure processing means for independently executing a communication control procedure having a hierarchical structure for each layer,
A system path through which the management information of the communication control procedure processing means is input / output, header information indicating the content of the communication control procedure to be executed independently of this system path, and a pointer of data executed by this header information. A communication control processing device, comprising: a dedicated path for directly passing information to and from the communication control procedure processing means on both upper and lower layers adjacent to each other.