JPS62114250A - Manufacture of printed circuit board - Google Patents

Manufacture of printed circuit board

Info

Publication number
JPS62114250A
JPS62114250A JP25532285A JP25532285A JPS62114250A JP S62114250 A JPS62114250 A JP S62114250A JP 25532285 A JP25532285 A JP 25532285A JP 25532285 A JP25532285 A JP 25532285A JP S62114250 A JPS62114250 A JP S62114250A
Authority
JP
Japan
Prior art keywords
line
leads
plated
exposed
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25532285A
Other languages
Japanese (ja)
Inventor
Toru Higuchi
徹 樋口
Toshiyuki Yamaguchi
敏行 山口
Kaoru Mukai
薫 向井
Takeshi Kano
武司 加納
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP25532285A priority Critical patent/JPS62114250A/en
Publication of JPS62114250A publication Critical patent/JPS62114250A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To eliminate the damage of a semiconductor chip through plated leads due to static electricity charged on an operator by cutting by etching a portion crossing the profile finishing line of plated leads exposed by removing a protecting material, and then cutting it along the profile finishing line. CONSTITUTION:Before coating a solder resist 3, a portion 4a crossing the profile finishing line L of plated leads 4 is covered with a protecting material 5, coated with the resist 3, the exposed portion of the portion 4a crossing the line L of the leads 4 is cut by etching by removing the material 5, and then cut along the line L. That is, since the portion 4 crossing the line L of the leads 4 is mechanically removed before finishing the profile, the ends of the leads 3 are not exposed on the end face of the obtained printed circuit board 2.

Description

【発明の詳細な説明】 [技術分野] 本発明はビングリッドアレイ(PG^)とかリードレス
チップキャリア(LCC)9の半導体チップキャリア用
のプリント配線板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of manufacturing a printed wiring board for a semiconductor chip carrier such as a bin grid array (PG^) or a leadless chip carrier (LCC) 9.

[背量技術1 従来より、スルーホールめっきプリント配線板をチップ
キャリアとして半導体チップが実装されているが、プリ
ント配線板の端面にスルーホールと連続して形成された
スルーホールめっき用のめつきリード線の切断面が露出
しており、取り扱いの際に、取り扱い者に帯電している
静電気がこの露出しているめっきリード線を通じて半導
体チップに通電して破壊させてしまうという問題があっ
た。
[Background technology 1 Conventionally, semiconductor chips have been mounted using through-hole plated printed wiring boards as chip carriers, but plated leads for through-hole plating are formed continuously with the through-holes on the end face of the printed wiring board. The cut surface of the wire is exposed, and there is a problem in that when handling the wire, static electricity charged on the handler may conduct electricity through the exposed plated lead wire to the semiconductor chip, causing it to be destroyed.

[発明の目的1 本発明は上記事情に鑑みてなされたものであり、その目
的とするところは、製品端面にめっきリード線が露出す
ることがなく、実装した半導体チップが取り扱い者のa
電気により破壊することがないプリント配線板を製造す
ることある。
[Objective of the Invention 1 The present invention has been made in view of the above circumstances, and its purpose is to prevent the plating lead wires from being exposed on the end face of the product and to prevent the mounted semiconductor chip from being exposed to the handler's a
We manufacture printed wiring boards that cannot be destroyed by electricity.

[発明の開示1 本発明のプリント配線板の製造方法は、金属箔張積層板
1からスルーホールめっきプリント配線板2を製造する
方法であって、ソルダーレジスト3を塗布rる前に、め
っきリード線、8の外形仕上げ線りと交差する部分4a
を保護材5で被覆し、ツルグーレジスト3を塗布した後
、保護材5を除去してめっきリード線4の外形仕上げ線
りと交差する部分4aである露出部をエツチングにて切
断し、この後外形仕上げ線りに沿って切断加工すること
を特徴とするものであり、この構成により上記目的を達
成できたものである。即ち、外形仕上げに先立って、め
っきリード#iI4の外形仕上げ線りと交差する部分4
aを811械的に除去するするので、得られたプリント
配線板2の端面にはめっきリード線3の端部が露出する
ことがなN1ものである。
[Disclosure 1 of the Invention The method for manufacturing a printed wiring board of the present invention is a method for manufacturing a through-hole plated printed wiring board 2 from a metal foil-clad laminate 1, in which the plating leads are removed before applying the solder resist 3. Line, part 4a that intersects with the external finishing line of 8
After covering with a protective material 5 and applying a Tsurugu resist 3, the protective material 5 is removed and the exposed portion, which is the portion 4a that intersects with the outer finish line of the plated lead wire 4, is cut by etching. This feature is characterized in that cutting is performed along the rear contour finishing line, and with this configuration, the above object can be achieved. That is, prior to external finishing, the portion 4 that intersects with the external finishing line of plating lead #iI4
Since 811 a is mechanically removed, the ends of the plated lead wires 3 are not exposed on the end face of the obtained printed wiring board 2.

以下、本発明を添付の図面を参照して詳細に説明する。Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

本発明においては、金属箔張積層板16−らスルーホー
ルめっきプリント配線板2の製造は周知の工程が採用さ
れる6たとえば、サブトラクティブ法では、銅張積層板
に順次、穴明け、活性化処理、無電解めっき、スクリー
ン印刷又は露光・現像(めっきレジスト)、電%銅めっ
さ、電解はんだめっき(エツチングレノスト)、めっき
レジスト剥離、エツチング、ヒユージング、ツルグーレ
ノスト印刷、外形仕上げ、シンボルマーク印刷といった
工程で入ルーホールめっきプリント配線板2は製造され
る。金m箔張積層板1は、樹脂基板の上に樹脂含浸基材
、金属箔を配置し、このものを−組みとして成形プレー
トを介して複数組み熱盤間に配置し、例えば、250℃
以上、20−150kg/em2.40〜100分で加
熱加圧してM層一体化させて得られる。樹脂基板の代わ
りにチップ実vcFM所だけが金属である樹1m基板な
どを使用してもよい。
In the present invention, a well-known process is adopted to manufacture the through-hole plated printed wiring board 2 from the metal foil-clad laminate 16.6For example, in the subtractive method, a copper-clad laminate is sequentially drilled and activated. Processing, electroless plating, screen printing or exposure/development (plating resist), electrolytic copper plating, electrolytic solder plating (etching resist), plating resist peeling, etching, fusing, turgorlenost printing, external finishing, symbol mark printing Through these steps, the through-hole plated printed wiring board 2 is manufactured. The gold foil-clad laminate 1 is made by arranging a resin-impregnated base material and metal foil on a resin substrate, and placing a plurality of these as a set between hot platens via a molding plate, and heating at, for example, 250°C.
The above is obtained by heating and pressing 20-150 kg/em2.40-100 minutes to integrate the M layer. Instead of a resin substrate, a 1m wood substrate in which only the actual chip VCFM portion is made of metal may be used.

本発明にあっては、従来周知の工程の内、ツルグーレジ
スト3を塗布する前に、回路パターンと同時に形成され
たスルーホール部ランドと連続するめっきリード#it
4の外形仕上げ線りと交差する部分4aを保護材5で被
覆する(第1図)。この保護材5としては、テープを貼
着したり、めっきレノストなどを採用できる。この後、
ツルグーレジスト3を塗布しく第2図)、次いで保護材
5を除去してめっきリード線4の外形仕上げff1Lと
交差する部分4aを露出させ、この部分をエツチングに
て切断しく第3図)、この後外形仕上げ線りに沿ってプ
レスして切断加工し、スルーホールめっきプリント配線
板2を得る(第4図)。尚、保護林5を除去してエツチ
ング処理をした後の露出部12にはソルダーレジストを
塗布しておいてもよい。このプリント配線板2の表面に
ミリング加工などの機械的切削加工によって半導体チッ
プ6の実装用凹部7を設けて半導体チップキャリアAを
形成する。
In the present invention, among the conventionally well-known steps, before applying the turret resist 3, a plating lead #it that is continuous with the through-hole land formed at the same time as the circuit pattern is formed.
A portion 4a that intersects with the external finishing line 4 is covered with a protective material 5 (FIG. 1). As this protective material 5, it is possible to use tape, plating, etc. After this,
Apply a strong resist 3 (Fig. 2), then remove the protective material 5 to expose the portion 4a that intersects with the external finish ff1L of the plated lead wire 4, and cut this portion by etching (Fig. 3). Thereafter, it is pressed and cut along the outer finishing line to obtain a through-hole plated printed wiring board 2 (FIG. 4). Note that a solder resist may be applied to the exposed portion 12 after the protected forest 5 has been removed and etched. A semiconductor chip carrier A is formed by providing a recess 7 for mounting a semiconductor chip 6 on the surface of this printed wiring board 2 by mechanical cutting such as milling.

このようにして形成した半導体チップキャリアAには、
第5図に示すように実装用凹部7にダイス8ボンデイン
グして半導体チップ6を搭載し、ワイヤ9ボンデイング
により回路パターン10と電気的に接続し、エポキシ樹
脂などの封止用樹脂により樹脂封止し、スルーホール1
1に端子ビンを保持させることによりピングリッドアレ
イとして、又、スルーホール11を接続孔として機能さ
せることによりリードレスチップキャリアとして使用で
きるものである。又、必要によりセラミック製などのカ
バー1、二より半導体チップキャリアAを気密封止して
実用に供する。
The semiconductor chip carrier A formed in this way has
As shown in FIG. 5, a semiconductor chip 6 is mounted by bonding a die 8 in a mounting recess 7, electrically connected to a circuit pattern 10 by bonding wires 9, and resin-sealed with a sealing resin such as epoxy resin. Through hole 1
1 can be used as a pin grid array by holding terminal bins, and can be used as a leadless chip carrier by allowing the through holes 11 to function as connection holes. Further, if necessary, the semiconductor chip carrier A is hermetically sealed with covers 1 and 2 made of ceramic or the like for practical use.

本発明は金属箔張積層板からスルーホールめっきプリン
ト配線板を製造する方法であって、ツルグーレジストを
塗布する前に、めっきリード線の外形仕上げ線と交差す
る部分を保護材で被覆し、ツルグーレジストを塗布した
後、保護材を除去して露出させためっきリード線の外形
仕上げ線と交差する部分をエツチングにて切断し、この
後外形仕上げ線に沿って切断加工するので、外形仕上げ
して得られたプリント配線板の端面にはめっきリード線
の端部が露出することがなく、従って、半導体チップを
実装した場合にも、取り扱い者に帯電している静電気が
めっきリード線より半導体チップに通電して破壊させる
ようなことがないものである。
The present invention is a method for manufacturing a through-hole plated printed wiring board from a metal foil-clad laminate, in which the portions of the plated lead wires that intersect with the external finishing line are covered with a protective material before applying the turret resist, After applying the Tsurugo resist, the protective material is removed and the exposed plated lead wire is cut by etching at the part that intersects with the external finishing line, and then cutting is performed along the external finishing line, so the external finishing is easy. The ends of the plated lead wires are not exposed on the end face of the printed wiring board obtained by this process, and therefore, even when semiconductor chips are mounted, static electricity charged on the handler is transferred from the plated lead wires to the semiconductor chips. There is no possibility that the chip will be destroyed by being energized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)(+1)、第2図(a)(b)及び第3図
(、)(b)はそれぞれ本発明の一実施例の工程を°示
′〒断面図及び平面図、第4図(a)(b)は同上によ
り得たプリント配#a仮を示す断面図及び平面図、第5
図は同チップキャリアを示す断面図であって、A1よ半
導体チップキャリア、Lは外形仕上1デ線、11よ金属
箔張積層板、2はプリント配線板、31よツルグーレジ
スト、4はめつきリード線、4alよ外形仕上げ線と交
差する部分、5は保護材である。 代理人 弁理士 石 1)長 七 ml 図
Figures 1(a) (+1), 2(a)(b) and 3(,)(b) respectively illustrate the steps of an embodiment of the present invention; FIGS. 4(a) and 4(b) are a sectional view and a plan view showing the tentative print layout #a obtained as above, and FIG.
The figure is a cross-sectional view showing the same chip carrier, where A1 is the semiconductor chip carrier, L is the external finish 1 delineation, 11 is the metal foil clad laminate, 2 is the printed wiring board, 31 is the solid resist, and 4 is the plating. The lead wire 4al intersects with the external finishing line, and 5 is a protective material. Agent Patent Attorney Ishi 1) Long 7ml Diagram

Claims (1)

【特許請求の範囲】[Claims] (1)金属箔張積層板からスルーホールめっきプリント
配線板を製造する方法であって、ソルダーレジストを塗
布する前に、めっきリード線の外形仕上げ線と交差する
部分を保護材で被覆し、ソルダーレジストを塗布した後
、保護材を除去して露出させためっきリード線の外形仕
上げ線と交差する部分をエッチングにて切断し、この後
外形仕上げ線に沿って切断加工することを特徴とするプ
リント配線板の製造方法。
(1) A method of manufacturing a through-hole plated printed wiring board from a metal foil-clad laminate, in which the portions of the plated lead wires that intersect with the external finish line are covered with a protective material before applying the solder resist, and the solder resist is Printing characterized by applying a resist, removing the protective material and cutting the exposed plated lead wire at the part that intersects with the finished outer line by etching, and then cutting along the finished outer line. Method of manufacturing wiring boards.
JP25532285A 1985-11-14 1985-11-14 Manufacture of printed circuit board Pending JPS62114250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25532285A JPS62114250A (en) 1985-11-14 1985-11-14 Manufacture of printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25532285A JPS62114250A (en) 1985-11-14 1985-11-14 Manufacture of printed circuit board

Publications (1)

Publication Number Publication Date
JPS62114250A true JPS62114250A (en) 1987-05-26

Family

ID=17277168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25532285A Pending JPS62114250A (en) 1985-11-14 1985-11-14 Manufacture of printed circuit board

Country Status (1)

Country Link
JP (1) JPS62114250A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002057243A (en) * 2000-08-09 2002-02-22 Dainippon Printing Co Ltd Semiconductor-chip mounting board, manufacturing method therefor, and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002057243A (en) * 2000-08-09 2002-02-22 Dainippon Printing Co Ltd Semiconductor-chip mounting board, manufacturing method therefor, and semiconductor device
JP4549499B2 (en) * 2000-08-09 2010-09-22 大日本印刷株式会社 Manufacturing method of semiconductor chip mounting substrate, semiconductor chip mounting substrate and semiconductor device

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