JPS62112435A - Signal decoder - Google Patents

Signal decoder

Info

Publication number
JPS62112435A
JPS62112435A JP60253932A JP25393285A JPS62112435A JP S62112435 A JPS62112435 A JP S62112435A JP 60253932 A JP60253932 A JP 60253932A JP 25393285 A JP25393285 A JP 25393285A JP S62112435 A JPS62112435 A JP S62112435A
Authority
JP
Japan
Prior art keywords
circuit
signal
pulse
output
waveform shaping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60253932A
Other languages
Japanese (ja)
Inventor
Norio Furuno
古野 紀雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60253932A priority Critical patent/JPS62112435A/en
Publication of JPS62112435A publication Critical patent/JPS62112435A/en
Pending legal-status Critical Current

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Landscapes

  • Manipulation Of Pulses (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To simplify a decoder and to miniaturize a logic circuit by providing a multivibrator circuit generating a delay signal of an output signal of a waveform shaping circuit and a decoding circuit reproducing a pulse signal at each transmission period and generating AND of delay signals. CONSTITUTION:Three synchronizing pulse signals in a remote transmission signal are inputted to the waveform shaping circuit 21 from an input terminal 111. The output pulse signal of the multivibrator circuit 22 and the output signal of the waveform shaping circuit 21 are inputted to an AND circuit 25, where AND operation is applied and the presence of the pulse signal is discriminated and the discrimination signal is outputted to the multivibrator circuit 23 of the next stage. The circuit 23 uses the discrimination signal of the AND circuit 25 to generate a pulse signal similarly as the circuit 22 and the signal is outputted to the AND circuit 26 of the next stage. The AND circuit 26 uses the output signal of the circuit 23 and the output signal of the circuit 21 to output the discrimination signal similarly as the AND circuit 25.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、レーダ装置から遠隔伝送する信号の同期パル
ス信号の復号器に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoder for synchronized pulse signals of signals remotely transmitted from a radar device.

〔従来の技術〕[Conventional technology]

レーダ装置から管制室まで受信ビデオ信号を遠隔伝送す
る場合には、送信周期毎の同期パルス信号と受信ビデオ
信号を時分割処理してひとつの信号に合成した遠隔伝送
信号を用いている。レーダ装置では遠隔伝送信号の中で
同期パルス信号は、伝送路での外来雑音による信号によ
る誤動作を防止するために、送信周期毎の同期パルスを
数μsec毎に遅延させて、複数パルス信号にして伝送
路に送出して管制室側の復号器では、複数のパルス信号
をパルス時間間隔毎の遅延をパルス数分だけ繰返し、遅
延させた各々の信号の論理損金とることによシ、送信周
期毎の同期パルス信号全再生している。外米雑音による
信号は、論理損金とった場合に、出力が得られない。従
来、遠隔伝送信号の信号復号器としては、リアクタンス
とキャパシタンスを用い友遅延線を用いた信号遅延回路
と、遅延回路の低下する信号レベルを高めるためのレベ
ル変換回路と、遅延信号の論理積を行なう論理積回路と
により、同期パルス信号′ft再生していた。
When remotely transmitting a received video signal from a radar device to a control room, a remote transmission signal is used in which a synchronization pulse signal for each transmission period and a received video signal are time-divisionally processed and combined into a single signal. In radar equipment, the synchronization pulse signal among the remote transmission signals is made into a multiple pulse signal by delaying the synchronization pulse for each transmission cycle by several μsec to prevent malfunction due to external noise on the transmission path. After being sent out to the transmission line, the decoder in the control room repeats the delay of multiple pulse signals for each pulse time interval by the number of pulses, and takes the logical loss of each delayed signal. The synchronized pulse signal is fully regenerated. Signals due to foreign noise cannot be output when logical losses are taken. Conventionally, signal decoders for remotely transmitted signals have consisted of a signal delay circuit that uses a delay line using reactance and capacitance, a level conversion circuit that increases the signal level that has decreased in the delay circuit, and a logical product of the delayed signals. The synchronizing pulse signal 'ft was regenerated by the AND circuit.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

パルス信号の遅延に遅延線を用いた場合には。 When a delay line is used to delay a pulse signal.

レーダ装置がら送出する同期パルス信号のパルス間隔は
、数μSecの時間てあり、遅延線での信号レベル減衰
がめるため増幅やレベル変整等を行なう必要があり、遅
延線の寸法も大きなものとなる。
The pulse interval of the synchronization pulse signal sent out by the radar device is several microseconds, and in order to reduce the signal level attenuation in the delay line, it is necessary to perform amplification, level adjustment, etc., and the size of the delay line becomes large. .

さらに伝送信号中の同期パルス信号の複数化されたパル
ス信号のパルス間隔金変更する場合には。
Furthermore, when changing the pulse interval of a plurality of synchronized pulse signals in a transmission signal.

あらかじめ必要に応じた出力タップを用意しておく必要
があるという欠点がめる。
The drawback is that it is necessary to prepare output taps according to needs in advance.

〔問題点全解決するための手段〕[Means to solve all problems]

本発明の復号器は、第1図に示すようにレーダ装置から
の遠隔伝送信号中の複数パルス信号を入力して、クロッ
クパルスにより波形成形を行なう波形成形回路3と、単
安定マルチバイブレータ全直列もしくは並列に接続して
波形成形回路3の出力信号の遅延信号を発生するマルチ
バイブレータ回路4と、遅延信号の論理積を行ない送信
周期毎の同期パルス信号を再生する復号回路5とを有し
ている。
As shown in FIG. 1, the decoder of the present invention includes a waveform shaping circuit 3 that inputs a plurality of pulse signals in a remote transmission signal from a radar device and shapes the waveform using clock pulses, and a monostable multivibrator all in series. Alternatively, it has a multivibrator circuit 4 which is connected in parallel to generate a delayed signal of the output signal of the waveform shaping circuit 3, and a decoding circuit 5 which performs ANDing of the delayed signals and reproduces a synchronized pulse signal for each transmission cycle. There is.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第2図は、本発明の一実施例である3バル一ス信号復号
器の構成図である。
FIG. 2 is a block diagram of a three-valve signal decoder which is an embodiment of the present invention.

遠隔伝送信号中の3パルス同期信号が入力端子11から
波形成形回路21に入力される。波形成形回路21には
、もうひとつ周期処理のためのクロックパルスが入力端
子12f:通して入力されており、クロックパルスによ
って、3パルス同期信号のタイミング変換が行なわれ、
クロックパルスに同期した3パルス信号となり1次段の
マルチバイブレータ回路22と論理積回路25.2fi
、27に送出さnる。
A three-pulse synchronization signal in the remote transmission signal is input from the input terminal 11 to the waveform shaping circuit 21. Another clock pulse for periodic processing is input to the waveform shaping circuit 21 through the input terminal 12f, and the timing of the three-pulse synchronization signal is converted by the clock pulse.
It becomes a 3-pulse signal synchronized with the clock pulse, and the primary stage multivibrator circuit 22 and AND circuit 25.2fi
, 27.

マルチバイブレーク回路22は、可変もしくは固定の抵
抗器とキャパシタンスによって定まった時間長のパルス
信号全出力する単安定マルチバイブレータである。マル
チバイブレータ回路22の出力パルス信号と波形成形回
路21の出力信号は、論理積回路25に入力さ扛て、論
理積演算ケ行ないパルス信号の有無の判定が行なわnて
、判定信号−が次段のマルチバイブレータ回路23に出
力さnる。マルチバイブレータ回路23では、論理積回
路25の判定信号によシ、マルチバレータ回路22と同
様にパルス信号を発生し、次段の論理積回路26に出力
される。論理積回路26は、マルチバイブレータ回路2
3の出力信号と波形成形回路21の出力信号とによシ、
論理積回路25と同様に判定信号全出力する。マルチバ
イブレータ回路24と論理積回路27は、マルチバイブ
レータ回路23と論理積回路26と同様の動作を行ない
最終判定信号が、論理積回路27よす出力さnる。
The multi-vibration circuit 22 is a monostable multivibrator that outputs a full pulse signal of a predetermined time length using a variable or fixed resistor and capacitance. The output pulse signal of the multivibrator circuit 22 and the output signal of the waveform shaping circuit 21 are input to the AND circuit 25, where the AND operation is performed to determine the presence or absence of the pulse signal, and the determination signal - is sent to the next stage. It is outputted to the multivibrator circuit 23 of. The multivibrator circuit 23 generates a pulse signal based on the determination signal from the AND circuit 25, similar to the multivalator circuit 22, and outputs it to the AND circuit 26 at the next stage. The AND circuit 26 is the multivibrator circuit 2
3 and the output signal of the waveform shaping circuit 21,
Similar to the AND circuit 25, all judgment signals are output. The multivibrator circuit 24 and the AND circuit 27 perform the same operation as the multivibrator circuit 23 and the AND circuit 26, and the final judgment signal is outputted from the AND circuit 27.

最終判定信号は、次段の波形回路28に入力されて、信
号のパルス@を調整されて出力端子13に出力さ扛る。
The final judgment signal is input to the waveform circuit 28 at the next stage, and the pulses of the signal are adjusted and outputted to the output terminal 13.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、単安定マルチバイブレー
タを用いることによって、論理回路のみで、遅延全実現
することが出来る上、単安定マルチバイブレータの抵抗
器を可変型とすることによシ容易にパルス間隔の異なる
パルス信号に対応する復号器が出来る上に、論理回路も
集積化によシ、遅延線に比べてはるかに小さく軽く作る
ことができる効果かめる。
As explained above, by using a monostable multivibrator, the present invention can realize all the delays with only a logic circuit, and by making the resistor of the monostable multivibrator variable, it can be easily achieved. Not only can a decoder be created that can handle pulse signals with different pulse intervals, but logic circuits can also be integrated, making them much smaller and lighter than delay lines.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の基本構成図、第2図は一実施例の3パ
ルス信号復号器の構成図である。 1.11.12・・・・・・入力端子、2,13・・・
・・・出力端子、3,21,28・・・・・・波形成形
回路、5・・・・・・復号回路、4,22,23.24
・・・・・・マルチバイブレータ回路、25.26.2
7・・・・・・論理積回路。
FIG. 1 is a basic configuration diagram of the present invention, and FIG. 2 is a configuration diagram of a three-pulse signal decoder according to an embodiment. 1.11.12...Input terminal, 2,13...
... Output terminal, 3, 21, 28 ... Waveform shaping circuit, 5 ... Decoding circuit, 4, 22, 23.24
・・・・・・Multi-vibrator circuit, 25.26.2
7...Logic product circuit.

Claims (1)

【特許請求の範囲】[Claims] 伝送信号の中の同期用パルス信号を入力して、周期処理
のためのクロックパルスにより波形成形を行なう波形成
形回路と、波形成形回路の出力信号の遅延信号を発生さ
せるマルチバイブレータ回路と、遅延信号の論理積を生
成し送信周期毎のパルス信号を再生する復号回路とを有
する信号復号器。
A waveform shaping circuit that inputs a synchronization pulse signal in a transmission signal and shapes the waveform using a clock pulse for periodic processing, a multivibrator circuit that generates a delayed signal of the output signal of the waveform shaping circuit, and a delayed signal. A signal decoder comprising a decoding circuit that generates a logical product of and reproduces a pulse signal for each transmission period.
JP60253932A 1985-11-12 1985-11-12 Signal decoder Pending JPS62112435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60253932A JPS62112435A (en) 1985-11-12 1985-11-12 Signal decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60253932A JPS62112435A (en) 1985-11-12 1985-11-12 Signal decoder

Publications (1)

Publication Number Publication Date
JPS62112435A true JPS62112435A (en) 1987-05-23

Family

ID=17258020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60253932A Pending JPS62112435A (en) 1985-11-12 1985-11-12 Signal decoder

Country Status (1)

Country Link
JP (1) JPS62112435A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5479608A (en) * 1977-12-08 1979-06-25 Teac Corp Synchronous signal circuit for pcm reproducer or like
JPS5619263A (en) * 1979-07-26 1981-02-23 Meidensha Electric Mfg Co Ltd Waveform shaping circuit
JPS57143963A (en) * 1981-03-02 1982-09-06 Fujitsu Ltd Data detector

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5479608A (en) * 1977-12-08 1979-06-25 Teac Corp Synchronous signal circuit for pcm reproducer or like
JPS5619263A (en) * 1979-07-26 1981-02-23 Meidensha Electric Mfg Co Ltd Waveform shaping circuit
JPS57143963A (en) * 1981-03-02 1982-09-06 Fujitsu Ltd Data detector

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