JPH0219044A - Phase adjustment circuit - Google Patents

Abstract

PURPOSE:To adjust the clock phase to a reception timing of a serial data by receiving an output of a shift register, comparing its content with an internally stored data and controlling a phase inversion circuit and a selection circuit. CONSTITUTION:The same data pattern as that of an 8-bit data stored in an internal register of a microcomputer 1 is inputted in advance to a serial data. A shift register 2 converts the serial data (a) into a parallel data by using an output clock (c) selected by a selection circuit 3 through the microcomputer 1, the converted parallel data being an output of the shift register 2 is extracted through a microcomputer bus (e) and compared with a data stored in advance. The data fetch and comparison are implemented for several number of times, and if they are dissident, a phase selection signal (d) or a clock polarity selection signal (f) is varied to apply the comparison. Thus, the clock is adjusted into the timing when the serial data is surely received.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase adjustment circuit, and more particularly to phase adjustment between serial data and an acquisition clock when acquiring serial data.

[Conventional technology]

Conventionally, when capturing serial data using a clock,
The side sending out serial data kept the serial data and clock in a fixed phase relationship, and the side receiving it did not make any timing adjustments.

[Problem to be solved by the invention]

The above-described conventional serial data acquisition has the disadvantage that if timing is not adjusted on the receiving side, the serial data acquisition will fail when the phase relationship changes due to wiring delay or the like. Another drawback is that serial data cannot be received unless the serial data is sent using the same clock on the sending and receiving sides.

[Means to solve the problem]

The phase adjustment circuit of the present invention includes a phase inversion circuit that inverts the phase of a clock, a delay circuit and a selection circuit that adjusts the phase of the clock, a shift register for receiving serial data using the clock, and a shift register for receiving serial data using the clock. It has a microcomputer control means that receives the output of the register, compares the contents with internally held data, and controls the phase inversion circuit and the selection circuit based on the result, and receives pre-scheduled serial data and corrects it. It is characterized in that the phase of the clock is adjusted to a timing that allows reception.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the phase adjustment circuit of the present invention, in which 1 is a microcomputer, 2 is a shift register, 3 is a selection circuit, 4 is a delay circuit, and 5 is an exclusive OR of a phase inversion circuit. (EX-OR circuit).

Serial data a is input from an external circuit (not shown) and is connected to the shift register 2, and is also sent to an external circuit (data receiving circuit), not shown.

The input clock b is an input from an external circuit (not shown), and is connected to the clock polarity selection signal of the microcomputer 1 as well as to the EX-OR circuit to send out the clock l.

Clock i is connected to delay circuit 4 and selection circuit 3.

The delay circuit 4 delays the phase of the clock i, generates a delayed clock g and a delayed clock h according to the magnitude of the delay time, and sends them to the selection circuit 3.

The selection circuit 3 selects one of the clock i, the delayed clock g, and the delayed clock h according to the phase selection signal d from the microcomputer 1, and outputs the output clock C.

The output clock C is connected to the shift register 2 and also to an external circuit (data receiving circuit) not shown.
will be sent to.

Shift register 2 converts serial data a into parallel data using output clock C. The microcomputer bus e is connected to the microcomputer 1 at the output of the shift register 2.

First, a start signal is sent from the host circuit to the microcomputer 1 using a phase adjustment start signal j, and the microcomputer 1 sends a phase selection signal d and a clock polarity selection signal f to determine the polarity of the input clock b and the initial delay time. Make settings.

The same data pattern as the 8-bit data previously stored in the internal register of the microcomputer 1, for example, a repeating pattern such as "10001000" is input as the serial data a. In the shift register 2, serial data a is converted into parallel data according to the output clock C selected by the microcomputer 1 in the selection circuit 3. The microcomputer 1 takes in the converted parallel data through the microcomputer bus e, which is the output of the shift register 2, and compares it with previously stored data. At this time, the data of the microcomputer 1 may be shifted and compared, or the parallel data may be shifted and compared.

If data acquisition and comparison operations are performed several times, but if they match all the times, it is recognized that data can be reliably acquired, and the set values of polarity and delay time are fixed. If they do not match, a comparison operation is performed by changing the phase selection signal d or clock polarity selection signal f.
By performing the above operations, the clock is adjusted to a phase that allows stable data capture.

〔Effect of the invention〕

As explained above, the present invention can automatically adjust the phase of the clock and reliably capture data without having to consider the phase relationship between the serial data and the clock to capture serial data from the outside. effective. Furthermore, even if the clock is not the one on the serial data sending side, if the clock cycle is the same, the clock can be adjusted to the timing at which the serial data can be reliably received by performing phase adjustment.

[Brief explanation of the drawing]

The first section is a block diagram of an embodiment of the phase adjustment circuit of the present invention. a... Serial data, b... Input clock, C...
...Output clock, d...Phase selection signal, e...Microcomputer bus, f...Clock polarity selection signal, g, h...Delayed clock, i...Clock, j
... Phase adjustment start signal, 1... Microcomputer, 2... Shift register, 3... Selection circuit,
4...Delay circuit, 5...EX~OR circuit.

Claims (1)

[Claims] A phase inversion circuit that inverts the phase of the clock, a delay circuit and a selection circuit that adjusts the phase of the clock, a shift register that receives serial data using the clock, and receives the output of this shift register and stores its contents internally. It has a microcomputer control means that compares it with the held data and controls the phase inversion circuit and the selection circuit based on the result, and adjusts the phase of the clock to a timing that can receive pre-scheduled serial data and correctly receive it. A phase adjustment circuit characterized by the following characteristics: