FR2722355A1 - Data transfer communication circuit for CPU's in image forming appts. - Google Patents

Abstract

The circuit has data receiving circuitry (6) to receive data items from a signal (RXD) co-ordinated by a predetermined timing signal (SCK2) (pref. a serial pulse clock signal). A time differing element (I,8) (pref. including circuitry (I) to invert the timing signal) provides a different time (SCK3) for operation of the data receiving circuitry. The received signal successively transmits the data items maintaining each for a predetermined time period (pref. between two adjacent similar edges of the clock). The time differing circuit provides its different time by delaying for a period within the data period.

Description

 The present invention relates to a communication circuit for performing data transfer between central processing units (CPU) such as microcomputers and between a CPU and an input / output (I / O) unit. The I / O unit such as that which includes a shift register is used to convert a signal in the form of parallel data to a signal in the form of serial data and vice versa. Such a communication circuit is suitable for use in an image forming apparatus such as a duplicator. The present invention relates in particular to a communication circuit included in an integrated circuit (IC) of such a CPU.

 Recently, an image forming apparatus such as a duplicator has been provided with multiple functions. Thus, a CPU used as the IC of the image forming apparatus is asked to control many functions. As a result, it is necessary to provide numerous wire harness units on the CPU IC. However, providing many wire harness units in the CPU IC can degrade the data processing performance of the CPU. For example, as a result of increasing the wire harness units of the CPU IC, the number of wires connected to the CPU IC is increased and therefore the area of one printed circuit board including the CPU IC should be increased. It follows from this that problems concerning electrical noise arise.

 In order to eliminate these problems, the CPU CPU is divided into a plurality of CPU CPUs which are distributed in various suitable locations in the device. A data transfer between each of the CPU ICs and a respective one of the I / O units is performed as serial data communication. The I / O unit is used between a CPU and terminal devices such as operation switches, display devices etc ... to transfer specification data from the switches to the IC of the CPU and display data from the CPU IC on the display devices. As a result, it is possible to decrease the number of wire harness units to be provided in each of the CPU ICs.

In such an image forming apparatus, it is necessary to perform data transfer between the ICs of the
CPU and also between each IC of the CPU and a respective one of the I / O units. In order to obtain a high degree of precision during data transfer operations, it is necessary to carry out these data transfer operations in a simple manner without using any special circuits inserted between the
CPU ICs as well as between each CPU IC and the relevant one of the I / O units.

However, in communication circuits for prior art image forming apparatuses, in comparison with the case where a data transfer is carried out between ICs of the CPUs, many conditions must be satisfied to allow the realization of data transfer operations between an IC of a CPU and an I / O unit. In the alternative, it is necessary to insert a special circuit between an IC of a CPU and an I / O unit to allow the performance of data transfer operations between an IC of a CPU and an I / O unit O. For example, when data transfer is performed between CPU ICs using a serial clock signal
SCK, data output from an IC of a CPU is obtained for each falling edge of the clock pulses of the clock signal SCK while data input by the other IC of the CPU is performed for each rising edge of the clock pulses of the clock signal SCK. Therefore, data output at a falling edge of the clock signal clock pulses from the CPU IC is input by the other CPU IC at the next rising edge of the clock pulses. clock of the clock signal.

However, when a data transfer is made between an IC of a CPU and an I / O unit, certain types of units
I / O output data for each rising edge of the clock pulses of the SCK serial clock signal. Thus, in certain cases, an I / O unit outputs data for each rising edge of the clock pulses of the serial clock signal SCK and an IC of a CPU enters the data also during the rising edge of the pulses d SCK series clock signal clock, as mentioned above. It is difficult to ensure that the data output at the edge of the clock pulses of the serial clock signal SCK by the unit
I / O are entered precisely at the same time by the IC of the
CPU. In fact, there may be a time delay due to an electric current which circulates in a circuit between the moment when the data are outputted from the I / O unit and the moment when the data outputted reach l 'CPU IC. In order to ensure that data output by one component is input by another component, it is necessary to make the input time when the receiving component enters the data different from the output time when the output component outputs the data.

 In order to cause the input timing to differ from the output time when data is transferred between an I / O unit which outputs data at each rising edge of the clock pulses and an IC of a CPU which enters the data during the rising edge of the clock pulses, it is necessary to provide a special circuit so as to ensure a finite time difference between the input timing of lC of real CPU and the output timing of 'real I / O unit.

 Instead of providing such a special circuit, it is possible to perform data transfer without using I / O units.

That is, a data transfer between an IC of a CPU and terminal devices such as operation switches, display devices etc. to transfer specification data from the switches to the IC of the
CPU and to display data from the CPU IC on the display device is achieved using signals as parallel data. However, if a data transfer is performed in the form of parallel data, many wire harness units must necessarily be provided and therefore, the accuracy of the data transfer operations may be degraded. Alternatively, it is also possible to pull a data bus from an IC of a CPU. The data bus is then connected to a dilator
I / O to convert a signal in the form of parallel data into a signal in serial form. However, according to this method, it is possible that electrical noise may be introduced into the data bus.

An object of the present invention is to provide a communication circuit in an IC of a CPU to allow simple carrying out of data transfer operations without the use of any special circuits inserted between the
CPU IC as well as between the CPU IC and the relevant one of the I / O units. Thus, a high degree of precision can be obtained during data transfer operations.

 In order to achieve this object of the present invention, the communication circuit includes time delay means for producing a delayed time at which data receiving means receives a plurality of data items from a received signal with respect to timing in accordance with a given timing signal. As a result, if the data items are transferred from an I / O unit at times in accordance with the given timing signal, the times of the given timing signal are delayed by the means for delaying. Then, the instants thus delayed are used so that the data reception means such as a shift register receives the data elements from the received data. As a result of this time delay, it is possible that the data receiving means receives each item of the multiple data items from the received signal after the data item supported by a received signal has reached the input means of data.

 The received signal supports the multiple data elements in a manner that the multiple data elements are successively supported and each element of the multiple data elements is maintained for a predetermined time period. Therefore, as long as the time period for which the time delay means delaying the time of data reception is within the predetermined time period for which each data item is held, the data reception means receives data element from the received data.

 More specifically, the given timing signal includes a clock signal consisting of serial clock pulses. The predetermined time period mentioned above for which each element of the several data elements is maintained is a duration between two same adjacent types of edges of the serial clock pulses. The same type of front is constituted by either increasing fronts or decreasing fronts. The data reception means receives each element of the several data elements from the signal received for the same type of edge, that is to say either a rising edge or a falling edge, serial clock pulses. The means for differing in time comprises an inverter for performing an inversion between a high level and a low level of the clock signal. As a result of the inversion of the clock signal, a duration for each rising edge and a duration for each falling edge are inverted with respect to each other in the clock signal.

Thus, the instant at which the data reception means receives a data element from the received signal is delayed until the next edge of the serial clock pulses.

 More specifically, if the I / O unit transfers the several data elements for each increasing edge of the serial clock pulses, each element of the several data elements is maintained for the predetermined time period between two adjacent increasing edges of the pulses. clock series. As a result of the action of the inverter which reverses the given timing signal, the instant of each rising edge of the delayed serial clock pulses resulting from an inversion of the original serial clock pulse is a time of each falling edge of the original serial clock pulses. That is, the instant of each increasing edge of the delayed serial clock pulse resulting from an inversion of the original serial clock pulse is significantly delayed relative to an instant of each increasing edge. original serial clock pulses for a time period between a rising edge and the falling edge following original serial clock pulses. The data receiving means then receives data at each rising edge of the delayed serial clock pulses.

Since a rising edge of the delayed serial clock pulses is present in the middle of each set of two adjacent rising edges of the original serial clock pulses, the data receiving means receives each data item from the signal. reception in the middle of the predetermined time period for which the data item is maintained.

 Alternatively, the time delay means may include signal delay means for delaying the received signal by a predetermined delay time. The predetermined time period includes a time period between a rising edge and the falling edge following serial clock pulses or between a falling edge and the rising edge following serial clock pulses. That is, the means for delaying delay the reception signal by a time period between either a rising edge and the following falling edge or a falling edge and the rising edge following serial clock pulses. .

 Consequently, if the I / O unit transfers the several data elements for each edge of the same type of edge, that is to say either each increasing edge or each decreasing edge of the serial clock pulses, each element of the more than one piece of data is maintained for the predetermined time period between two adjacent edges of the same type of edge of the serial clock pulses. The signal carrying the several data elements is then delayed, by the means for differing in time, by the time period between two adjacent edges of the serial clock pulses. The two adjacent edges of each set of edges of the serial clock pulses are of different types of edges, i.e. a rising edge and a falling edge. As a result, although the data receiving means receives data for each edge of the same type of edge mentioned above from the serial clock pulses, after the time delay means has delayed the received signal, the data receiving means receives each data item from the reception signal in the middle of the predetermined time period for which the data item is held.

 That is, if the I / O unit transfers the multiple data elements for each increasing edge of the serial clock pulses, each element of the multiple data elements is maintained for the predetermined time period between two increasing edges adjacent serial clock pulses. The carrier signal of the several data elements is then delayed by the means to differ in time from the time period between two adjacent edges of the serial clock pulses. As a result, each element of the multiple data elements is maintained for the predetermined time period between two adjacent falling edges of the serial clock pulses. The data receiving means then receives data for each rising edge of the serial clock pulses. Since a rising edge is present in the middle between each set of two adjacent falling edges, the data receiving means receives each data element from the reception signal in the middle of the predetermined time period for which the data is maintained.

 The communication circuit may include data placement means for placing multiple pieces of data on a transmission signal at a time consistent with either the given timing signal or another given timing signal. Thus, it is possible to transfer data in addition to receiving the data.

In addition, the communication circuit may further comprise a selection means for selecting whether or not the means for differing in time is used. If data communication is carried out between CIs including
CPU, an instant at which each data element is transferred from an IC and an instant at which the same data element is received by the other IC are different from each other. Therefore, it is necessary to use this means to defer over time.

Another aspect of the present invention consists of an integrated circuit comprising
a central processing unit which performs a predetermined processing
a communication circuit which performs data communication between the central processing unit and the outside of the integrated circuit
the communication circuit comprising:
data receiving means for receiving data items from a signal received at an instant in accordance with a given timing signal; and
time delay means for producing a delayed time at which said data receiving means receives said data items from said received signal.

 Due to the provision of the means to differ in time in the integrated circuit, it is not necessary to insert any special circuit between the integrated circuit and the I / O unit in order to carry out data communication between them .

 The communication circuit may further comprise a selection means for selecting whether or not the time delay means is used and other selection means for selecting whether or not the given timing signal is applied from the outside. of the integrated circuit or is applied by an internal pulse generation circuit provided in the integrated circuit. Thus, if data is transferred between two similar integrated circuits as mentioned above, a time at which each data element is transferred from one IC and a timing at which the same data element is received for the other IC are different. one of the other.

 In addition, it is chosen in a first integrated circuit that the given timing signal is applied by the internal pulse generation circuit provided therein and it is chosen in the second integrated circuit that the given timing signal is applied from its exterior. Therefore, the same given timing signal is used in both integrated circuits as a result of the fact that the first integrated circuit applies the given signal to the second integrated circuit.

Other objects and other characteristics of the present invention will appear more clearly in the light of the detailed description which follows, which will be read in conjunction with the accompanying drawings, among which
FIG. 1 represents a partial circuit diagram of an IC including a communication circuit according to a first embodiment of the present invention
Figures 2A, 2B and 2D show timing diagrams of a data transfer operation of the communication circuit shown in Figure 1;
Figure 2C shows the state of a shift register contained in the communication circuit shown in Figure 1;
FIGS. 3A, 3B, 3C and 3D represent time diagrams of an operation for receiving data from the communication circuit shown in FIG. 1;
Figure 3E shows the state of a shift register 6 contained in the communication circuit shown in Figure 1;
FIG. 4 represents a wired connection between two ICs, each of which may be an IC including the communication circuit according to any one of the first and second embodiments of the present invention
FIG. 5 represents a circuit diagram of an I / O unit of the prior art and represents a wired connection between the I / O unit and an IC, which includes the communication circuit according to any one of the first and second embodiments of the present invention
FIG. 6 represents a partial circuit diagram of an IC including a communication circuit according to the second embodiment of the present invention
Figures 7A, 7B, 7C and 7D show timing diagrams of a data reception operation of the communication circuit shown in Figure 6;
Figure 7E shows the state of a shift register contained in the communication circuit shown in Figure 6;
FIG. 8 represents a partial circuit diagram of an IC including a communication circuit according to a third embodiment of the present invention
Figure 9 shows a wired connection between two ICs, each of which includes the communication circuit according to the third embodiment of the present invention; and
Figure 10 shows a circuit diagram of a unit
I / O of the prior art and represents a wired connection between the I / O unit and an IC, which includes the communication circuit according to the third embodiment of the present invention.

With reference to FIGS. 1, 2, 3, 4 and 5, a communication circuit according to a first embodiment of the present invention is now described. The communication circuit according to the first embodiment of the present invention is included in an IC 100 contained in a
CPU. The CPU is for example used to control data processing in an image forming apparatus such as a duplicator, in a well known manner. The communication circuit includes a shift register 4 of the parallel input serial output type which is connected to an internal data bus 1 of the CPU. A data loading signal LD for data transmission and a serial clock signal SCK1 are input to the shift register 4. The serial clock signal
SCK1 is generated by a pulse generation circuit (not shown in the figure) in response to transmission instructions output by the CPU in the IC 100. A flip-flop 5 is also included in the communication circuit and it is connected to a terminal Q of the shift register 4, as shown in the figure. The flip-flop 5 outputs a TXD serial transmission signal in the form of serial data via its terminal Q.

In addition, the communication circuit includes a shift register 6 of the parallel input serial output type and it is connected to the internal data bus mentioned above 1 of the
CPU. A serial reception signal in the form of serial data
RXD and a serial clock signal SCK3 are entered on the shift register 6. The serial clock signal SCK3 is selectively output by a data selector 8 included in the communication circuit. A serial clock signal SCK2 and an inverted clock signal are input to the data selector 8. The inverted clock signal is obtained by inverting the signal
SCK2 via an inverter I. The data selector 8 selects an appropriate signal taken from the serial clock signal SCK2 and the inverted clock signal. The signal is output as a serial clock SCK3 from the data selector 8.

 An output terminal of an establishment register 9 is connected to a terminal S of the data selector 8. The establishment register 9 is connected to the above-mentioned data bus 1. A write signal WR is also entered on the establishment register 9. The write signal WR is a control signal. The data present in the internal data bus 1 is written to the establishment register 9 under the control of the write signal WR.

With reference to FIGS. 2A, 2B, 2C and 2D, an operation for transmitting data of the communication circuit described above is now described. Data is transferred from CPU 1 in the IC 100 to another CPU or unit
I / O, the CPU in the IC 100 applying data D7, D6, D5, D4,
D3, D2, D1 and Do (hereinafter called data D7-Do) to be transferred.

A control unit contained in the CPU of the IC 100 applies the above-mentioned data loading signal LD to the shift register 4 before the generation of the serial clock signal SCK1, as shown in FIGS. 2A and 2B . As a result of the data loading signal LD being input to the shift register 4, the data D7-Do is loaded into the shift register 4, as shown in Fig. 2C via the bus internal data 1 by the
CPU. Then 8 data bits of the data D7-Do thus loaded in the shift register 4 are shifted during each falling edge of the clock pulses of the serial clock signal
SCK1. Because the 8 data bits are shifted, the most significant bits (MSB) of the data D7-D0 are successively output from terminal Q of the shift register 4. The flip-flop 5 takes the data bit thus transmitted at output via terminal D during the falling edge of the clock pulses and outputs the data bit via terminal Q as a transmission signal TXD represented in FIG. 2D.

With reference to FIGS. 3A, 3B, 3C, 3D and 3E, an operation for receiving data from the communication circuit is now described, an operation during which data transferred from another CPU or an I / O unit is received by the CPU contained in the IC 100. When a signal of level "H" (represented on the left part of figure 3B) is entered via the terminal S on the selector of data 8, the selector of data 8 emits out via terminal Y the serial clock signal SCK3 (shown on the left side of Figure 3C) which is the serial clock signal SCK2 (shown in Figure 3A) which is input via terminal A. When a signal from level "L" (represented at the level of the right-hand part of FIG. 3B) is entered via terminal S on the data selector 8, the data selector 8 emits as output via terminal Y the clock signal SCK3 (represented in the right part of Figure 3C) which is the inverted signal of the signal d SCK2 series clock entered via a terminal
B. Whether the level signal "H" or the level signal "L" is applied to terminal S of the data selector 8 is determined by the establishment register 9 on the basis of data written in the establishment register under the control of the write signal WR.

The serial reception signal RXD carrying the data D7-D0 (see FIG. 3D) is successively entered on the shift register 6 and is shifted within it in synchronization with each rising edge of the clock pulses of the serial clock signal SCK3. Thus, as a result of the fact that 8 successive clock pulses of the serial clock signal SCK3 are input to the shift register 6, 8 data bits representing the reception data D7-Do are captured and stored in the register shift 6, as shown in Figure 3E. Thus, when the serial clock signal SCK2 is chosen by the data selector 8, the data D7-Do of the signal RXD are received by the shift register 6 during each increasing edge of the clock pulses of the clock signal SCK2 series, as shown on the left side of Figures 3A, 3B, 3C, 3D and 3E. When the clock signal reversed from the serial clock signal
SCK2 is selected by the data selector 8, the data
D7-Do of the signal RXD are received by the shift register 6 during each falling edge of the clock pulses of the serial clock signal SCK2, as shown in the right part of FIGS. 3A, 3B, 3C, 3D and 3E. The fact of knowing whether a rising edge or a falling edge of the clock pulses of the serial clock signal SCK2 is used to enter the data of the reception signal is determined by the signal entered on the terminal S of the data selector 8, which signal is applied by the establishment register 9 on the basis of data written in the establishment register 9 under the control of the writing signal WR.

Then the CPU contained in the IC 100 outputs data read instructions and therefore applies a data read signal RD to the shift register 6. As a result, the 8 elements of the reception data
D7-Do stored in the shift register 6 are read by the CPU via the internal data bus 1 in the form of parallel data.

 Furthermore, in the communication circuit according to the first embodiment of the present invention, means for passing an interrupt signal, not shown in the figure, is provided. When the interrupt signal indicating the end of the transfer of the 8 data bits is passed to the CPU, the CPU reads reception data and loads data to be transferred thereafter. In addition, an indicator register is provided to monitor whether or not data is being transferred.

 In addition, the data transfer operation is started after the loading of the data into the shift register 4 is completed. However, by providing another register between the internal data bus 1 and the shift register 4, it is possible for the CPU to independently perform the data loading operation via the internal data bus 1 and a actual data transfer operation.

That is, even if data is being loaded via the internal data bus 1 in the other register, data previously loaded in the shift register 4 can be transferred.

 Similarly, by providing another register between the shift register 6 and the internal data bus 1, it is possible that the CPU independently performs a data read operation via the internal data bus 1 as well. than an actual data reception operation.

That is, even if data is being received by the shift register 6, data
C2. Similarly, the serial clock signal SCK1 of the IC C2 is the serial clock signal SCK2 received by the IC C1.

In this case, the CPU contained in each of the ICs C1 and C2 can determine, by appropriately allocating the write signal WR to the establishment register 9 and consequently writing appropriate data in the establishment register 9, that the data selector 8 selects
SCK2 via terminal A. Thus, the reception data RXD is received by the shift register 6 during each increasing edge of the clock pulses of the serial clock signal.
SCK2 in a first IC taken from C1 and C2, as shown in the left part of FIGS. 3A, 3B, 3C, 3D and 3E. The same data is transferred from the flip-flop 5 during each falling edge of the clock pulses of the same serial clock signal in the second IC, as shown in FIGS. 2A, 2B, 2C and 2D. Thus, the instant at which the shift register 6 receives data in the first IC is different from a range of a pulse of the serial clock signal from the instant at which the flip-flop 5 transfers the same data in the second IC.

With reference to FIG. 5, a description according to which data is transferred between a certain IC C1 and an I / O unit 200 is produced. The IC C1 is the same as the IC 100 described above according to the first embodiment of the present invention. The I / O unit 200 includes shift registers 21, 22 and 23, as shown in the figure. The shift registers 21, 22 and 23 can be of the type SN74LS164, SN74LS374 and
SN74LS165 manufactured by Texas Instruments Inc.

 The I / O unit 200 receives input data from terminal devices such as operation switches etc. via input ports in the form of parallel data.

Then the shift register 23 converts the input data from the parallel data form to input data in the form of serial data which is then transferred to the CPU in the IC C1. The CPU contained in the IC C1 transfers the output data as serial data to the shift register 21 contained in the I / O unit 200. The shift registers 21 and 22 convert the serial data to the form serial data as output data in the form of parallel data, which are then applied to terminal devices such as display devices, etc., via output ports.

 In this case, the serial clock signal SCK1 is also used as the serial clock signal SCK2, as shown in the figure. Then the CPU contained in the IC C1 can determine, by allocating the write signal WR to the establishment register 9 and therefore writing data in the establishment register 9, that the data selector 8 selects the signal d reverse clock mentioned above of the serial clock signal SCK2 which is input to it via its terminal B.

Thus, the reception data RXD are received by the shift register 6 during each falling edge of the clock pulses of the serial clock signal SCK2 in the IC C1, as shown in the right part of FIGS. 3A, 3B, 3C, 3D and 3E while the same data is transferred from the shift register 23 during each rising edge of the clock pulses of the same serial clock signal in the I / O unit 200. Thus, I ' time at which shift register 6 inputs data into IC C1 is different from a pulse width of the serial clock signal from the time at which shift register 23 transfers the same data to unit l / O 200.

As a result, the data can be transferred without using any special circuits between the IC C1 and the l / O 200 unit.

 In the IC 100 described above, establishment data is written to the establishment register 9 under the control of the write signal WR. This determines whether the "H" level signal or the "L" level signal is output as a function of the software programs in relation with which the CPU is operating, the software programs and their modifications being well known in the art. data transfer by communication. Therefore, it is very easy for a user to select one of two operating modes. A first operating mode is selected when the IC 100 performs data communication with an I / O unit such as the I / O unit mentioned above 200, as shown in FIG. 5. In order to select the first mode the user simply needs to modify an appropriate part of the software programs. As a result, the communication circuit is automatically established so that the inverter I is used in response to the fact that the CPU writes appropriate establishment data to the establishment register 9.

A second operating mode is selected when the IC 100 performs data communication with a
IC similar to that shown in FIG. 4. In order to select the second operating mode, the user must simply modify an appropriate part of the software programs. As a result, the communication circuit is automatically established so that the inverter I is not used in response to the fact that the CPU writes appropriate establishment data to the establishment register 9.

A communication circuit according to a second embodiment of the present invention is now described with reference to FIG. 6. The communication circuit according to the second embodiment is included in an IC 300. In the communication circuit, instead of the inverter I shown in Figure 1, a flip-flop 1 1 is provided. The serial reception signal RXD and the serial clock signal SCK2 are entered on the flip-flop 11. Furthermore, the terminal Y of the data selector 8 is connected to the terminal D of the shift register 6 and the clock
SCK2 is also connected to the clock terminal of the shift register 6. With the exception of these connections, the communication circuit according to the second embodiment is the same as the communication circuit according to the first embodiment shown in Figure 1.

In the communication circuit of the second embodiment, either the signal SCK2 or the inverted signal is selected, depending on whether the reception signal RXD is directly received by the shift register 6 or whether it is first of all received by the flip-flop 11 and then by the shift register 6. Therefore, when the flip-flop 11 is used as a result of the fact that the level signal "L" is applied to the data selector 8, the reception signal
RXD shown in the right part of Figure 7C is converted into a signal shown in the right part of Figure 7D. That is to say that the start time for which the signal carries each of the 8 data elements D7-Do is delayed to be in synchronization with the falling edge following clock pulses of the clock signal SCK2 series shown in Figure 7A. Then the shift register 6 captures the data of the signal shown in the right part of FIG. 7D during increasing edges of the serial clock signal
SCK2, as shown on the right side of Figure 7E.

 A description that data is transferred between the two ICs C1 and C2 as shown in Figure 4 is now produced. Each of the ICs C1 and C2 comprises a CPU and the communication circuit of the second embodiment described above. In this case, the CPU in each of the ICs C1 and C2 can determine, by transmitting the write signal WR to the establishment register 9 and consequently writing data in the establishment register 9, that the data selector 8 selects the reception signal RXD via terminal A. Thus, the reception data RXD is directly received by the shift register 6 during each increasing edge of the clock pulses of the serial clock signal SCK2 in a first IC, as shown at the left side of Figures 7A, 7B, 7C, 7D and 7E. The same data is transferred from the flip-flop 5 during each falling edge of the clock pulses of the same serial clock signal in the second IC, as shown in FIGS. 2A, 2B, 2C and 2D. Consequently, the instant at which the shift register 6 inputs data into the first IC is different from a pulse width of the serial clock signal from the instant at which the flip-flop 5 transfers the same data in the second IC.

 A description that data is transferred between an IC C1 and an I / O unit 200 as shown in Figure 5 is now produced. The IC C1 includes a CPU and the communication circuit of the second embodiment described above. The serial clock signal SCK1 is also used as the serial clock signal SCK2, as shown in FIG. 5. The CPU contained in the IC C1 can determine, by allocating the write signal WR to the register of establishment 9 and therefore writing data in the establishment register 9, that the data selector 8 and the terminal B select the output at the terminal Q of the flip-flop 11.

The reception data RXD are transmitted from the shift register 23 during each rising edge of the clock pulses of the serial clock signal in the I / O unit 200. Thus, the instant of the start of a time period for which the signal carries each element of the 8 data elements D7.D0 coincides with the rising edge of the clock pulses of the serial clock signal. Then in the signal obtained via the flip-flop 11,
The instant of the start of the time period for which the signal carries each element of the 8 data elements
D7-Do is delayed to be in synchronization with the falling edge following clock pulses of the serial clock signal SCK2, as shown in the right part of FIG. 7A. Thus, the waveform represented in FIG. 7C is converted into the waveform represented in FIG. 7D by the function of the flip-flop 11.

 The data D7-Do supported by the signal thus obtained are received by the shift register 6 during the following rising edge of the clock pulses of the serial clock signal in the IC C1, as shown in the right part of FIGS. 7A , 7B, 7C, 7D and 7E. Thus, the shift register 23 transfers data to the I / O unit 200 during a rising edge of the clock pulses of the serial clock signal. Then this instant of data transfer is delayed until the falling edge following clock pulses of the serial clock signal via the flip-flop 11. The delay time is equal to a pulse width between the rising edge and the next falling edge. Then the shift register 6 receives data in the IC C1 during the rising edge following clock pulses of the serial clock signal.

 Thus, the instant at which the shift register 6 captures the data in the IC C1 is different from a pulse width of the serial clock signal between the following falling edge mentioned above and the following rising edge mentioned above. -before the moment in question. This instant is obtained as a result of the delay, by means of the flip-flop 11, from the instant when the shift register 23 transfers the same data to the I / O unit 200. As a result, the data is transferred without using any special circuit inserted between the IC C1 and the l / O 200 unit.

In the IC 300 described above, the fact of knowing which establishment data is written in the establishment register 9 is determined according to the software programs in accordance with which the CPU operates, the software programs and their modifications being well known in the field of data transfer by communication. Therefore, it is very easy for a user to select one of two operating modes. A first operating mode is selected when the IC 300 performs data communication with an I / O unit such as the unit
I / O mentioned above 200. In order to select the first operating mode, the user must simply modify an appropriate part of the software programs. As a result, the communication circuit is automatically established so that the flip-flop 11 is used as a result of the writing by the CPU of appropriate establishment data to the establishment register 9.

A second operating mode is selected when the IC 300 performs data communication with a
IC similar to that shown in FIG. 4. In order to select the second operating mode, the user must simply modify an appropriate part of the software programs. As a result, the communication circuit is automatically established so that the flip-flop 1 1 is not used in response to the writing by the CPU of appropriate establishment data in the establishment register 9.

 With reference to FIG. 8, a communication circuit according to a third embodiment of the present invention is now described. The communication circuit according to the third embodiment is included in an IC 400 which includes a CPU. According to the third embodiment, the CPU outputs data write instructions and appropriate establishment data are written to an establishment register 15 under the control of a write signal WR2. A signal output by the establishment register 15 is entered on a terminal S of a data selector 17 via an AND circuit A. The data selector 17 selects one of two signals, entered via terminals A respectively and B, and outputs the selected signal via a terminal Y. Thus, the communication circuit uses a serial clock signal SCK input from the outside or the communication circuit uses the serial clock signal SCK1 which is applied by the internal pulse generation circuit. The selected clock signal is used as the SCK4 serial clock signal in the communication circuit.

Two three-state buffers T1 and T2 are provided. When a level signal "H" is entered on the buffers from the circuit
AND A, the buffer T1 does not allow any signal to pass through itself and the buffer T2 lets a signal pass through itself. Thus, the serial clock signal SCK applied from the outside is brought to pass through the buffer T2 and is entered on the terminal A of the data selector 17.

However, the serial clock signal SCK1 applied by the internal pulse generation circuit is not output from the IC 400. When the level signal "L" is entered on the buffers from the AND circuit , the T1 buffer lets a signal pass through itself and the T2 buffer does not let any signal pass through itself. Thus, the serial clock signal SCK1 applied by the internal pulse generation circuit is output from the IC 400 through the buffer T2 and the serial clock signal SCK is not applied to the selector data 17.

In the communication circuit according to the third embodiment, when establishment data is written to the establishment register 9 by a write signal WR1 coming from the CPU via the internal data bus 1, the "H" level signal is output and an "inter-CPU" communication mode is selected. This mode is a mode for transferring data between ICs, each comprising a CPU. If the establishment data is written to the establishment register 15 and therefore the level signal "H" is outputted therefrom, it is determined that the serial clock signal SCK is used as the signal d SCK4 series clock. In fact, as a result of the level signals "H" being output from the two establishment registers 9 and 15, the AND circuit outputs the signal level "H" on the data selector 17 and on the three-state buffers T1 and T2. So the three-state buffers
T1 and T2 pass the SCK signal on the data selector 17 and do not let the SCK1 signal pass outside the IC 400. In addition, the data selector 17 selects the input SCK clock signal on terminal A from outside the IC 400. Thus, the clock signal SCK is used as the clock signal SCK4.

If the establishment data is written to the establishment register 15 and if the level signal "L" is output therefrom, it is determined that the serial clock signal
SCK1 is used as the SCK4 serial clock signal. In this case, the serial clock signal SCK1 is also applied to the outside. In fact, as a result of the fact that the level signal "H" is output from the establishment register 9 and that the level signal "L" is output from the establishment register 15, the ET circuit therefore outputs the level signal "L" on the data selector 17 and on the three-state buffers T1 and T2. So the three-state buffers
T1 and T2 do not let the SCK signal pass on the data selector 17 and let the SCK1 signal pass on the outside of the IC 400. The data selector 17 selects the clock signal SCK1 entered on terminal B from the internal pulse generation circuit. Thus, the clock signal SCK1 applied by the internal pulse generation circuit is used as the clock signal SCK4.

 In the communication circuit according to the third embodiment of the present invention, the clock signal SCK4 is used in common for data transfer and data reception, and data transfer and data reception are performed in parallel.

 With the exception of the operations described above, the communication circuit according to the third embodiment of the present invention is the same as the communication circuit of the second embodiment of the present invention.

If data is transferred between two CIs, i.e. C1 and
C2 shown in FIG. 9, each being the same as the IC 400, the CPU contained in each of the ICs C1 and C2 establishes the communication circuits in the "inter-CPU" communication mode mentioned above.

 Furthermore, the CPU of a first IC C1 of the ICs can establish the communication circuit in the first IC C1 in order to use the serial clock signal SCK1 in the first IC C1 as the serial clock signal SCK4 and in order to output this same clock signal SCK1 on the second IC C2. The CPU contained in the second IC C2 can therefore establish the communication circuit in the second IC C2 so as not to use the serial clock signal SCK1 applied by the internal pulse generation circuit of the second IC C2 as as SCK4 serial clock signal and also so as to use the SCK1 serial clock signal applied by the first IC C1. With the exception of these operations, the operation of the communication circuit according to the third embodiment is the same as that of the second embodiment of the present invention described above.

 The operation of the communication circuit according to the third embodiment of the present invention is now described for the case in which, as shown in FIG. 10, data is transferred between an IC C1, which is the same as the IC 400 , and the l / O 200 unit, which is the same as the l / O 200 unit shown in FIG. 5.

 In this case, the establishment data are written to the establishment register 9 under the control of the write signal WR1 and therefore, the level signal "L" is output. As a result, the level signal "L" output from the establishment register 9 as mentioned above is also input to the AND circuit A. Therefore, regardless of the level of the signal output from the other establishment register 15, the AND circuit A outputs the level signal "L" on the shift register 17 at its terminal S. Thus, the buffers with three states T1 and T2 do not allow the signal to pass SCK on the data selector 17 and let pass the signal SCK1 on the unit IIO 200. In addition, the data selector 17 selects the clock signal SCK1 entered on terminal B from the internal pulse generation circuit.

Thus, the clock signal SCK1 is used as the clock signal SCK4.

 In addition, similar to the operation of the communication circuit according to the second embodiment of the present invention, the data selector 8 selects the reception signal RXD via the flip-flop 11. Thus, the time difference d 'a pulse width is created between the instant delayed by a pulse width via the flip-flop ^ 1 from the moment when the shift register 23 transfers a data element contained in the signal and the instant when shift register 6 captures the same data item in the same signal. As a result, data can be transferred securely without using any special circuits inserted between the IC C1 and the l / O 200 unit.

 The other operations of the communication circuit according to the third embodiment of the present invention are the same as those according to the second embodiment.

 In the IC 400 described above, the establishment data is written to the establishment register 9 and is under the control of the write signal WR1. Thus, it is determined whether the level signal "H" or the level signal "L" is output from the establishment register 9 according to the appropriate software programs which operate the CPU, these software programs and their modifications being well known in the field of data transfer by communication. In addition, the establishment data is written to the establishment register 15 and is under the control of the write signal WR2. Thus, it is determined whether the level signal "H" or the level signal "L" is output from the establishment register 15 as a function of the software programs which operate the CPU the software programs and their modifications being well known in the field of data transfer by communication.

 Consequently, it is very easy for a user to select an operating mode from a first operating mode, a second operating mode and a third operating mode. The selection described above can be carried out quite simply by modifying an appropriate part of the software programs. As a result of the modification of the software programs, the CPU automatically writes appropriate establishment data to the establishment registers 9 and 15.

 The first operating mode is selected when the IC 400 performs data communication with an I / O unit such as the I / O unit 200. If the first operating mode is selected as a result of the program modification of software mentioned above carried out by the user, the following selection operation is automatically carried out: the communication circuit is established by means of the establishment register 9 so that the flip-flop 1 1 is used . In addition, via the establishment registers 9 and 15, the serial clock signal SCK1 generated by the internal generation circuit is used as the serial clock signal SCK4 in the IC 400 and also, the same signal SCK1 is applied outside the IC 400.

The second operating mode is selected when the IC 400 performs data communication with an IC similar to that shown in FIG. 9 and also when the serial clock signal SCK1 generated by the internal generation circuit is used as SCK4 serial clock signal and the SCK1 signal is applied to the outside of the IC 400. If the second operating mode is selected as a result of the modification of software programs by the user,
The selection operation which follows is carried out automatically: the communication circuit is established via the establishment register 9 so that the flip-flop 1 1 is not used. Thus, via the establishment registers 9 and 15, the serial clock signal SCK1 is used as the serial clock signal SCK4 and also, the same signal SCK1 is applied to the outside of the IC 400.

The third operating mode is selected when the IC 400 performs data communication with a
IC similar to that shown in Figure 9 and also when the SCK serial clock signal applied by the similar IC mentioned above is used as the serial clock signal
SCK4 in the IC 400. If the third operating mode is selected as a result of the modification of the software programs by the user, the following selection operation is automatically carried out: the communication circuit is established by the through the establishment register 9 so that the flip-flop 11 is not used. In addition, via the setting registers 9 and 15, the serial clock signal SCK applied by the IC is used as the serial clock signal SCK4 in the IC 400.

 Thus, according to the above-mentioned embodiments of the present invention, it is possible to perform data transfer in serial data form using a relatively simple circuit construction even between an IC including a CPU and an I / O. Thus, a reliable data transfer according to which noise contamination is eliminated can be obtained.

 Furthermore, according to the third embodiment, data transfer and reception can be performed in parallel using a common serial clock signal. Thus, the performance of data communication can be improved.

 The present invention is not limited to the embodiments described above and variants and modifications can be made without departing from the scope of the present invention.

Claims (12)

 1. Communication circuit characterized in that it comprises  data receiving means (6) for receiving data items from a received signal at a certain time in accordance with a given timing signal; and  time delay means (I; 11) for producing a delayed time at which said data receiving means receives said data items from said received signal.  2. Communication circuit according to claim 1, characterized in that:  said received signal transmits said data elements therein so that said data elements are successively transmitted and each element of said data elements is maintained for a predetermined period of time; and  said time delay means (I; 11) produces said delayed time by delaying by a certain period in said predetermined time period.  3. Communication circuit according to claim 2, characterized in that:  said given timing signal comprises a clock signal comprising serial clock pulses, said predetermined time period being a time between two same adjacent adjacent types of edges of said serial clock pulses  said data receiving means (6) receives each element of said data elements from said signal received for the same type of edge of said serial clock pulses; and  said time delay means (I) includes an inverter (I) for reversing said clock signal between a high level and a low level.  4. Communication circuit according to claim 2, characterized in that:  said timing signal comprises a clock signal producing serial clock pulses, said predetermined time period being a time between two same adjacent types of edges of said serial clock pulses;  said data receiving means (6) receives each element of said data elements from said signal received for the same type of edge of said serial clock pulses; and  said time delay means (11) includes signal delay means (11) for delaying said reception signal by a predetermined delay time.  5. Communication circuit according to claim 4, characterized in that said predetermined delay time comprises a time period between a type of edge and a different type of edge according to said serial clock pulses.  6. Communication circuit according to claim 1, characterized in that said communication circuit further comprises data placement means (4, 5) for placing said data elements on a transmission signal at an instant in accordance with a signal selected from said given timing signal and another given timing signal.  7. Communication circuit according to claim 1, characterized in that said communication circuit further comprises selection means (9, 8) for selecting whether or not said means for differing in time (I; 11) is used .  8. Integrated circuit comprising a central processing unit which performs a predetermined processing,  characterized in that:  said integrated circuit further comprises a communication circuit which ensures data communication between said central processing unit and the exterior of said integrated circuit  said communication circuit comprising:  data receiving means (6) for receiving data items from a signal received at an instant in accordance with a given timing signal; and  time delay means (I; 11) for producing a delayed time at which said data receiving means receives said data items from said received signal.  9. Integrated circuit according to claim 8, characterized in that said communication circuit further comprises a selection means (9, 8) for selecting whether or not said means for differing in time (I; 11) is used.  10. Integrated circuit according to claim 9, characterized in that a selection by said selection means (9, 8) is automatically carried out as a result of a modification of a software program.  11. Integrated circuit according to claim 8, characterized in that said communication circuit further comprises selection means (T1, T2) for selecting said given timing signal which is produced either from outside of said integrated circuit or from an internal pulse generation circuit provided in said integrated circuit.  12. Integrated circuit according to claim 11, characterized in that a selection by said selection means (T1, T2) is automatically carried out as a result of a modification of a software program.