JPS6211101Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an image signal transmission control device in a device such as a facsimile device that optically reads information and converts it into electrical information, and in particular, it can read accurately regardless of the recording state of the image to be read. The present invention relates to an image signal transmission control device that can efficiently transmit image signals.

Optical reading devices such as facsimile machines usually illuminate images on recording paper with a light source such as a fluorescent lamp.
This reflected light is scanned and read by an optical sensor such as a charge-coupled device (CCD).

FIG. 1 is a diagram explaining the principle of the optical reading device. Character 1 recorded on the paper is in lines l1 to l6
The image information is read as black and white pixel signals for each line, and the paper is sequentially moved from line 11 to line 16 so that character 1 can be read.

However, if there are extremely thin lines 10 in the characters, such as those written in Mincho typeface,
The sensitivity of the optical sensor may become insensible or unstable depending on the light source characteristics, etc., and when characters are reproduced from the read image signal, if the condition is poor, this thin line 10 will be missing as an image signal, so it will be difficult to reproduce. This method has the drawback of reproducing meaningless characters with missing pixels.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, and by reading the scanning unit line of the image multiple times, when a thin line is detected as image information multiple times, the image information is used to correct and reproduce the image. It is an object of the present invention to provide an image signal transmission control device which can efficiently modify image information and transmit it to a line.

In order to achieve the above object, the present invention includes a conversion means that scans a medium on which an image is recorded line by line and outputs black and white image signals read from the image in each unit scan, and a memory that stores the image signals. an image signal transmission control device which stores an image signal outputted by the conversion means for each unit scan in the memory and reads out the image signal from the memory at a predetermined period according to the transmission speed of the line; an image signal supply means for forming a first memory and a second memory to store an image, and supplying an image signal for each unit scan to the first or second memory;
Alternatively, the readout means for reading out the image signal from the second memory, the image signal supply means, and the readout means are respectively switched to the readout side or the supply side at a predetermined period, and the supply of the image signal for each unit scan is switched to the first or the first or second memory. A switch means is provided for controlling switching to one of the two memories and switching image signal readout from the other memory, and for one memory connected to the image signal supply side, unit scanning of the recording medium is performed multiple times. Then, the black and white image signals at the time of the first scan are supplied and accumulated, and at the time of the next scan, the black image signals detected by the conversion means are supplied to correct the accumulated image signals, and the image signal is connected to the image signal readout side. The image signal is read out from the other memory.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

Explanation of the structure of FIG. 2 FIG. 2 is a principle block diagram of an embodiment of the present invention. In the figure, WCT is a write counter, RCT is a read counter, CONT is a control unit, CCD is a read element, and SW
1. SW2 is a switch, and MEML and MEMR are memories. In the figure, before transmitting the image signal for one line of the original (for example, l3 in Figure 1),
The same line 13 is scanned twice, and the black and white image signals obtained in the first scan are stored in the memory as they are, and in the second scan, only the detected black image signals are supplied to the memory. The image signal consists of, for example, a 1024-bit pixel signal per row, and each memory MEML and MEMR is configured to store a 512-bit pixel signal, and when one row is scanned, the pixel signal is 1024 bits. Switch the pixel signal of
Switch with SW1 and store 512 bits in the left half as memory.
In MEML, the right half of 512 bits is input and stored in memory MEMR.

Explanation of operation in Fig. 2 When creating the transmission signal SD shown in Fig. 4 using the device shown in Fig. 2, first, the first 512 bits of the read signal RD from the CCD of the reading element and the write counter are used.
The control signal shown by the broken line output by the WCT is the switch
It is applied as a write signal LW to the memory MEML via SW1, and is controlled to write the read signal RD based on the control of the write counter WCT. SW1 and switch SW2 are control unit CONT
Each can be switched by . Read side switch
When SW2 is switched to the memory MEML side and write side switch SW1 is switched to the memory MEMR side, the read signal RD is sent to the memory MEMR as described above.
The latter 512 bits and the control signal from the write counter WCT are given as the write signal RW, and the read signal RD is controlled to be written based on the control of the write counter WCT.

Also, by inputting the control signal of the read counter RCT to the memory MEML, the read signal LR is output from the memory MEML according to the transmission speed of the line (not shown).
is read out and controlled to send a transmission signal SD to the line via switch SW2.

The read signal LR is read out from this memory MEML, and before the switches SW1 and SW2 are switched, the memory MEMR that is currently being written is written multiple times ( Control is performed so that a black and white image signal is used the first time, and only a black image signal is used from the next time onwards.

This switching operation and writing operation will be explained in more detail based on the block diagram and time chart of a specific example of the present invention shown in FIGS. 3 and 4.

Explanation of the structure of FIG. 3 In FIG. 3, parts corresponding to those shown in FIG. 2 are indicated by the same symbols. Here, MICL
and MICR are memory MEML and memory MEMR respectively
A dedicated mode specification section that specifies the write or read mode. Next, AICL and AICR are address specifying sections dedicated to the memory MEML and memory MEMR, respectively, and specify the write address for the read signal RD and the read address for the send signal SD. Furthermore, ADRL and ADRR are address signals dedicated to memory MEML and memory MEMR, respectively, A1 to A5, A'1 to A'3 are AND gates, and O1 to O5, O'1 to O'2 are OR gates. .

Functional explanation of counters (WCT, RCT) in Figure 3 Furthermore, write counter WCT and read counter RCT
Each has the functions described below.

That is, by counting clock signals each having a predetermined frequency equal to or more than the number of bits of the pixel signal and outputting the counted value, the read counter RCT receives the read address signals RA1 to RAn, while the write counter
The WCT performs the first function of outputting write address signals WA1 to WAn, respectively, while the count value is counting 0 to 511, which is the number of bits in the first half of one line, and 512 to 1023, which is the number of bits in the second half of one line. (i.e., while counting 0 to 1023), the second function is to hold the output at a constant level, for example, level "1".
IWSR is held at level “1” alternately, while
The read counter RCT has a second function of alternately holding the switching signals IS1 and IS2 at level "1", and furthermore, the read counter RCT has a second function that keeps the switching signals IS1 and IS2 at level "1" alternately. [IW2R], counting from 512 to n (512<n≦1023) [IW2L], 1024 to r(0) [r
(0) is a return where the counter value returns to “0”.
Each has a third function of holding the output at level "1" during each counting of "0".

The write counter WCT mentioned above is driven by a clock synchronized with the reading speed of the reading element CCD, and the read counter RTC mentioned above is driven by a clock synchronized with the sending speed of the transmission line. The counter RCT is controlled to be synchronized when the count value is "0".

Note that the symbols shown for the outputs of the read counter RCT and the counter WCT indicate that they are connected to input lines with the same symbol of each circuit.

Here, the addressing part AICL is the logic gate A
2, A3, and O2 as many as necessary to specify the address in the memory MEML, and the other address specification section AICR has the same logic gates A'2, A'3, O'2 as the address specification section AICL. As for its input signals, the signals that are different from the address designation part AICL are the write memory designation signal IWSR, which is replaced with the write memory designation signal IWSL, and the write designation signal
Write designation signal IWOR replaced with IWOL and switching signal
The switching signal IS2 is changed to IS1.

Explanation of the operation of FIG. 3 The operation of the block diagram of FIG. 3 will be explained below based on the time chart of FIG. 4.

The operation will be explained based on the clock classification of the read counter RCT: the first period (1024 to r(0)), the second period (0 to 511), the third period (512 to 1023), and the fourth period (1024 to r(0)). (0))...

First period (1024-r(0)) First, when the write counter WCT operates and starts counting, the first function described above outputs the write address signals WA1-n, and at the same time, the second function outputs the write address signals WA1-n. When the count value is 0 to 511, the write memory designation signal IWSL is output, and when the count value is 512 to 1023, the write memory designation signal IWSR is output at level "1", and after that, the count of the write counter WCT returns to 0. Repeat this each time.

On the other hand, the read counter RCT outputs the write designation signal IW1 which becomes level "1" between 1024 and r(0) by the above-mentioned third function, and sends this output through OR gates O4 and O3, respectively. IWOL
and IWOR (the broken line part in LWOL and IWOR in Figure 4).

During the period when the write designation signal IW1 is at the level "1", the AND gate A1 in the mode designation unit MICL becomes "open" when the black bit of the read signal RD whose level is "1" is input, and the OR gate O1 is opened. The state 〓W2〓 is reached in which the memory MEML is put into write mode.

At this time, if the write counter WCT is in the period of counting 0 to 511, the write address signals WA1 to n input to the AND gate A2 in the addressing unit AICL are given as write address information ADRL0 to 511 for the memory MEML via the OR gate O2 because the AND gate A2 is opened by the write designation signal IWOL (the broken line portion in FIG. 4) which has reached level "1" and the write memory designation signal IWSL.

Also, during the same period when the write designation signal IW1 is at level "1", the mode designation unit MICR outputs the write designation signal IW1 to the OR gate.
The signal is supplied to the memory MEMR via O'1, and the memory MEMR is in the write mode during this entire period (W1).

At this time, if the write counter WCT counts 512 to 1023, the address specification section AICR
are supplied with write address signals WA1 to WAn, a write memory designation signal IWSR, a write designation signal IWOR which is a write designation signal IW1 which is at level "1" via an OR gate O3,
Since the above three write address signals WA1 to WAn are input to the AND gate A'2, the write address signals WA1 to WAn supplied to the AND gate A'2 are passed through the OR gate O'2. Address information for writing to memory MEMR
Read signal given as ADRR512 to 1023 and input to input terminal Di of memory MEMR
All RDs are stored in addresses ADRR512 to ADRR1023 designated by the address designation section AICR.

In relation to the above explanation, the ADRL and
ADRR indicates a mode signal for each memory MEML and MEMR, and the state in which all read signals RD are written to each memory MEML and MEMR is indicated by 〓W1〓, and the already stored read signal RD is written by a black level signal. The state of correction writing is indicated by 〓W2〓.

Second period (0 to 511) Writing to memory MEMR〓W1〓 and memory
If both the write counter WCT and the read counter RCT count “0” after completing the correction write to MEML〓W2〓, the write counter
WCT starts counting from 0 again, and the count value is 0~
Write address signals WA1-n, write memory designation signals IWSL, IWSR between 511 and 512-1023, respectively.
On the other hand, the read counter RCT outputs a switching signal IS1.
is output as level “1” and the memory
RA1 to RAn are supplied as read address signals of MEML or MEMR to addressing units AICL and AICR.

In the addressing section AICL, since the switching signal IS1 is at level "1", the read address signals RA1-n are supplied to the memory MEML as read address information ADRL0-511 via the AND gate A3 and the OR gate O2. During this period, AND gate A2 outputs the write designation signal.
Since IWOL is at level "0", it is "closed" and prevents output of write address signals WA1 to WAn.

Also, the mode specifying part MICL is the input signal.
Since both IW2L and write designation signal IW1 are at level "0", the output from OR gate O1 is at level "0", and the memory MEML is placed in the read mode (R). Also, the transmission signal SD read from the memory MEML is the switching signal
Switch SW2 becomes “open” state due to IS1
The image signal of the left half of one row read from the memory MEML is sent to the line via AND gate A4 and OR gate O5.

Incidentally, these memories MEML and MEMR are in read mode as shown in Figure 4.
Signal ADRL corresponding to MEML, memory MEMR
The signal ADRR corresponding to is indicated by 〓R〓.

During the same period, the read counter RCT
After counting “m” by the function of “511”
The level "1" is output as the signal IW2R until the signal IW2R is reached. This signal IW2R is the mode designation part
The read signal RD is input to the AND gate A'1 of MICR, and the AND gate A'1 becomes level "1".
When the black bit of is inputted, it becomes "open" and the state W2 is established in which the memory MEMR is put into the write mode via the OR gate O'1. At this time, memory
MEMR write address information ADRR512~
1023 is performed by the write address signals WA1 to WAn of the write counter WCT, the write memory designation signal IWSR becomes level "1", and the signal IW
During the output period of 2R, that is, the write designation signal IWOR
is supplied to the memory MEMR during the period of level “1”.

Third Period (512-1023) Next, when the read counter RCT counts "512", the switching signal IS2 rises instead of the switching signal IS1, and furthermore, the signal IW2L rises instead of the signal IW2R. This puts the memory MEML in write mode and the memory MEMR in read mode.

In other words, regarding the memory MEML, the signal IW2L is input to the mode specifying unit MICL at level "1" (until the read counter RCT counts "n"), and the memory MEML is set to the write mode via the OR gate O1. Condition〓W1〓
Therefore, the write address is the write counter WCT
By counting the count value 0 to 511, the write memory designation signal IWSL becomes level “1”, and the write designation signal IWOL from the read counter RCT becomes level “1” via OR gate O4, so the write Write counter WCT write address signal
WA1~n is AND gate A2, OR gate O
Memory MEML address information 0 through 2
511.

On the other hand, regarding the memory MEMR, the switching signal IS2 is at level “1” and the signal IW
Since 2R is at level "0", the write designation signal IWOR via OR gate O3 is also at level "0", so the input of the mode designation section MICR is at level "0", and the output is also at level "0" for reading. mode becomes 〓R〓, and the AND gate A'2 is "closed" in the address specification section AICR.
In this state, the AND gate A'3 is in the "open" state, and only the read address signals RA1 to RAn are supplied to the memory MEMR via the OR gate O'2 as address information ADRR512 to ADRR1023.
In addition, the switching signal IS2 makes the AND gate A5 in the switch SW2 open, so the memory
The image signal of the right half of one line read from MEMR is sent to the line via AND gate A5 and OR gate O5.

According to the above explanation, half of the read signal RD for one line of the image recorded on the recording medium is stored in each memory MEML and MEMR (state W1), and then modified (state W1). 〓W2〓), then read (state 〓R〓, 〓R〓)
and will be sent out to the line as a continuous transmission signal SD.

Fourth period (1024 to r(0)) When the period in which the memory MEMR is in the read state 〓R〓 ends, the transmission signal SD enters the synchronization signal sending period T.

During this period T, the memory MEML modifies the image signal recorded in the write mode W1 as described above in the modification mode W2, while the memory MEMR modifies the image signal recorded from the new scanning line. This is done during the writing period of the read signal RD 〓W1〓.

Note that during this synchronization signal sending period T, a write designation signal for the read counter RCT is sent from a circuit system (not shown).
A synchronization signal is created and output during the output period of IW1.

Effects of the present invention As explained in detail above, according to the present invention, two
By providing two memories and performing scanning multiple times, while reading data from one memory, the image signal from the first scan is stored in the other memory, and corrections are made using the image signal from the next scan. Moreover, since the correction is carried out using only the black pixels read from the image, it is not only possible to efficiently transmit the correct signal, but also to reduce the memory capacity to only the capacity for storing one line of data. A signal transmission control device is realized.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an image reading method of a facsimile device, FIG. 2 is a block diagram explaining the principle of the present invention, and FIG. 3 is a block diagram of an embodiment of the present invention.
FIG. 4 is an operation time chart of FIG. 3. In the figure, 1 is a character, 1 to 6 are lines, 10 is a thin line,
CCD is a reading element, SW1 and SW2 are switches,
MEML, MEMR are memory, WCT is write counter, RCT is read counter, CONT is control unit, RD
is a read signal, SD is a transmission signal, LW, RW are write signals, LR, RR are read signals, AICL, AICR are address specification parts, MICL, MICR are mode specification parts,
ADRL0-511, ADRR512-1023 are address information, WA1-n are write address signals,
RA1 to n are read address signals, IWSL, IWSR are write memory designation signals, IW1, IWOL, IWOR,
IW2L and IW2R are write designation signals, and IS1 and IS2 are switching signals.

Claims (1)

[Scope of utility model registration request] It has a conversion means that scans a medium on which an image is recorded line by line and outputs a black and white image signal read from the image in each unit scan, and a memory that stores the image signal. In an image signal transmission control device that stores an image signal to be output in the memory and reads out the image signal from the memory at a predetermined period according to the transmission speed of the line, the memory for storing the image signal is divided into a first and a second memory. The image signal for each unit scan is stored in the first memory.
or a means for supplying an image signal to the second memory, a readout means for reading out the image signal from the first or second memory, and a means for supplying the image signal to the readout side or the readout means at a predetermined period. switch means connected to the image signal supply side, for controlling the supply of the image signal for each unit scan to one of the first or second memory and the readout of the image signal from the other memory. For one memory, unit scanning of the recording medium is performed a plurality of times, black and white image signals from the first scanning are supplied and stored, and black image signals detected by the converting means are supplied for the next scanning. 1. An image signal sending control device, which corrects an image signal stored in a memory, and reads out the image signal from another memory connected to an image signal reading side.