JPS62108878U - - Google Patents

Info

Publication number
JPS62108878U
JPS62108878U JP20000485U JP20000485U JPS62108878U JP S62108878 U JPS62108878 U JP S62108878U JP 20000485 U JP20000485 U JP 20000485U JP 20000485 U JP20000485 U JP 20000485U JP S62108878 U JPS62108878 U JP S62108878U
Authority
JP
Japan
Prior art keywords
test
additional
test head
board
space
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20000485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20000485U priority Critical patent/JPS62108878U/ja
Publication of JPS62108878U publication Critical patent/JPS62108878U/ja
Pending legal-status Critical Current

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Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は従来のテストヘツドの概要を
示した図。第3図、第4図、第5図は本考案によ
る一実施例を示す図。 1……テストヘツド、2……テストボード、3
……被測定デイバイス、4……ソケツト、5……
端子、6……配線ケーブル、7……ピンカード、
8……付加回路を構成し得る空間、9……ボード
、10……コネクタ、11……配線ケーブル、1
2……付加回路実装部、13,14……接触部。
FIGS. 1 and 2 are diagrams showing an outline of a conventional test head. FIG. 3, FIG. 4, and FIG. 5 are diagrams showing one embodiment of the present invention. 1...Test head, 2...Test board, 3
...Device under test, 4...Socket, 5...
Terminal, 6... Wiring cable, 7... Pin card,
8... Space that can configure an additional circuit, 9... Board, 10... Connector, 11... Wiring cable, 1
2... Additional circuit mounting part, 13, 14... Contact part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体集積回路等の試験装置で、ドライバ、コ
ンパレータ回路を有するピンカードを内蔵するテ
ストヘツドにおいて、被測定デイバイスの試験の
ために必要な付加回路を構成しうる空間を設け、
該付加回路を搭載したボードを容易に着脱可能に
したことを特徴とする試験装置のテストヘツド。
In test equipment for semiconductor integrated circuits, etc., in a test head that has a built-in pin card with a driver and comparator circuit, a space is provided in which additional circuits necessary for testing the device under test can be configured.
A test head for a test device, characterized in that a board on which the additional circuit is mounted can be easily attached and detached.
JP20000485U 1985-12-25 1985-12-25 Pending JPS62108878U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20000485U JPS62108878U (en) 1985-12-25 1985-12-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20000485U JPS62108878U (en) 1985-12-25 1985-12-25

Publications (1)

Publication Number Publication Date
JPS62108878U true JPS62108878U (en) 1987-07-11

Family

ID=31162155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20000485U Pending JPS62108878U (en) 1985-12-25 1985-12-25

Country Status (1)

Country Link
JP (1) JPS62108878U (en)

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