JPS62105541A - Optical receiving circuit - Google Patents

Optical receiving circuit

Info

Publication number
JPS62105541A
JPS62105541A JP60243890A JP24389085A JPS62105541A JP S62105541 A JPS62105541 A JP S62105541A JP 60243890 A JP60243890 A JP 60243890A JP 24389085 A JP24389085 A JP 24389085A JP S62105541 A JPS62105541 A JP S62105541A
Authority
JP
Japan
Prior art keywords
bias voltage
circuit
pin photodiode
depletion layer
photodiode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60243890A
Other languages
Japanese (ja)
Inventor
Daisuke Maruhashi
丸橋 大介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60243890A priority Critical patent/JPS62105541A/en
Publication of JPS62105541A publication Critical patent/JPS62105541A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To omit an equalizing circuit composes of L and C by adjusting a bias voltage applied to a PIN photodiode, and varying frequency characteristics corresponding to the width of depletion layer and thus equalizing waveform. CONSTITUTION:An electric signal converted by the PIN photodiode 11 is passed through amplifiers 14 and 15 and extracted by a tank circuit 16, whose output is amplified 17, so that received data from a level discriminator 18 is outputted as a timing signal for level discrimination. The depletion layer width of the diode 11 varies with the bias voltage and the electrostatic capacity between terminals varies, so that the output of a high frequency area decreases as the bias voltage becomes lower. For the purpose, the bias voltage is adjusted to adjust the frequency characteristics of the photodiode and perform desired equalization, so the equalizing circuit as a conventional example is omitted.

Description

【発明の詳細な説明】 (概要〕 PINフォトダイオードに印加するバイアス電圧を調整
することにより、PINフォトダイオードの空乏層幅に
対応した周波数特性を変化させて波形等化を行い、コイ
ルやコンデンサ等からなる等化回路を省略可能としたも
のである。
[Detailed Description of the Invention] (Summary) By adjusting the bias voltage applied to the PIN photodiode, the frequency characteristics corresponding to the depletion layer width of the PIN photodiode are changed to equalize the waveform, and the coil, capacitor, etc. This allows the equalization circuit consisting of the following to be omitted.

〔産業上の利用分野〕[Industrial application field]

本発明は、光信号を電気信号に変換し、レベル識別によ
り受信データを出力する光受信回路に関するものである
The present invention relates to an optical receiving circuit that converts an optical signal into an electrical signal and outputs received data based on level identification.

光伝送システムに於いては、光伝送路を介して伝送され
る光信号は、減衰、波形歪を受けることになり、光受信
回路に於いては、受信した光信号を受光素子により電気
信号に変換し、増幅、波形等化を行った後に、レベル識
別により受信データを出力するものである。このような
光受信回路は所望の特性を簡単な構成で得ることが望ま
しいものである。
In an optical transmission system, an optical signal transmitted through an optical transmission line is subject to attenuation and waveform distortion, and in an optical receiving circuit, the received optical signal is converted into an electrical signal by a light receiving element. After conversion, amplification, and waveform equalization, the received data is output based on level identification. It is desirable for such an optical receiving circuit to obtain desired characteristics with a simple configuration.

〔従来の技術〕[Conventional technology]

従来の光受信回路は、例えば、第4図に示す構成を有し
、21は受光素子、22は抵抗、23は前置増幅器、2
4は主増幅器、25は等化回路、26はタンク回路、2
7はタイミング信号増幅器、28はレベル識別器である
。受光素子21と抵抗22との直列回路に、所定のバイ
アス電圧VCCが印加され、受光素子21に光伝送路を
介して光信号が入射される。
A conventional optical receiving circuit has, for example, a configuration shown in FIG. 4, in which 21 is a light receiving element, 22 is a resistor, 23 is a preamplifier,
4 is the main amplifier, 25 is an equalization circuit, 26 is a tank circuit, 2
7 is a timing signal amplifier, and 28 is a level discriminator. A predetermined bias voltage VCC is applied to the series circuit of the light receiving element 21 and the resistor 22, and an optical signal is input to the light receiving element 21 via the optical transmission path.

受光素子21により光信号は電気信号に変換され、前置
増幅器23により増幅され、増幅出力は主増幅器24に
加えられ、AGC機能等により所定のレベルに増幅され
て等化回路25に加えられる。等化回路25はコイルや
コンデンサ等の組合せ回路で構成され、一種のローパス
フィルタを形成している。この等化回路25により波形
等化された信号は、レベル識別器28に加えられると共
に、タンク回路26に加えられる。このタンク回路26
は伝送信号のクロック信号成分の周波数を共振周波数と
するタンク回路で、クロック信号成分が抽出されてタイ
ミング信号増幅器27により増幅され、レベル識別器2
8にレベル識別のタイミング信号として加えられる。
The optical signal is converted into an electrical signal by the light receiving element 21, amplified by the preamplifier 23, the amplified output is applied to the main amplifier 24, amplified to a predetermined level by an AGC function, etc., and applied to the equalization circuit 25. The equalization circuit 25 is composed of a combination circuit of a coil, a capacitor, etc., and forms a kind of low-pass filter. The signal whose waveform has been equalized by the equalization circuit 25 is applied to a level discriminator 28 and also to a tank circuit 26. This tank circuit 26
is a tank circuit whose resonant frequency is the frequency of the clock signal component of the transmission signal, in which the clock signal component is extracted and amplified by the timing signal amplifier 27,
8 as a timing signal for level identification.

レベル識別器28は、波形等化された信号をタイミング
信号によるタイミングでレベル識別し、受信データを出
力するものである。
The level discriminator 28 discriminates the level of the waveform-equalized signal at the timing according to the timing signal, and outputs received data.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の光受信回路に於ける等化回路25は、コイルやコ
ンデンサ等の組合せ回路で構成されているから、小型化
することが困難であり、又受信信号の波形等化の為の調
整が複雑となる欠点があった。
The equalization circuit 25 in the conventional optical receiving circuit is composed of a combination circuit of coils, capacitors, etc., so it is difficult to miniaturize it, and the adjustment for equalizing the waveform of the received signal is complicated. There was a drawback.

本発明は、コイルやコンデンサ等からなる等化回路25
を省略できる光受信回路を提供することを目的とするも
のである。
The present invention provides an equalization circuit 25 consisting of a coil, a capacitor, etc.
The object of the present invention is to provide an optical receiving circuit that can omit the above steps.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の光受信回路は、受光素子としてPINフォトダ
イオードを用い、このPINフォトダイオードの空乏層
幅に対応した周波数特性を利用して波形等化を行うもの
であり、第1図を参照して説明すると、受光素子として
のPINフォトダイオード1と、このPINフォトダイ
オードlへのバイアス電圧により空乏層幅を変化させて
、その周波数特性を変化させ、それによって波形等化を
行うバイアス回路2を設け、PINフォトダイオード1
により変換された電気信号を増幅部3で増幅し、タイミ
ング再生部4で再生したタイミング信号に従って、レベ
ル識別部5でレベル識別し、受信データを出力するもの
である。
The optical receiving circuit of the present invention uses a PIN photodiode as a light receiving element, and performs waveform equalization using the frequency characteristic corresponding to the depletion layer width of the PIN photodiode. To explain, a PIN photodiode 1 as a light receiving element is provided, and a bias circuit 2 is provided which changes the depletion layer width by applying a bias voltage to the PIN photodiode 1, changes its frequency characteristics, and thereby equalizes the waveform. , PIN photodiode 1
The electrical signal converted by the above is amplified by an amplifying section 3, and according to the timing signal reproduced by a timing reproducing section 4, the level is discriminated by a level discriminating section 5, and received data is output.

〔作用〕[Effect]

PINフォトダイオード1の空乏層幅は、バイアス電圧
を大きくすると大きくなり、PINフォトダイオード1
の端子間の静電容量が小さくなって、周波数特性は高域
まで延長することになる。
The depletion layer width of the PIN photodiode 1 increases as the bias voltage increases, and the width of the depletion layer of the PIN photodiode 1 increases.
The capacitance between the terminals becomes smaller, and the frequency characteristics extend to higher frequencies.

従って、バイアス回路2によりPINフォトダイオード
1に印加するバイアス電圧を調整することにより、所望
の周波数特性を得ることができ、それによって波形等化
を行うものである。
Therefore, by adjusting the bias voltage applied to the PIN photodiode 1 by the bias circuit 2, a desired frequency characteristic can be obtained, thereby performing waveform equalization.

〔実施例〕〔Example〕

以下図面を参照して本発明の実施例について詳細に説明
する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図は本発明の実施例のブロック図であり、11は受
光素子としてのPINフォトダイオード、12はバイア
ス回路を構成する可変抵抗、13は直列抵抗、14は前
置増幅器、15は主増幅器、16はタンク回路、17は
タイミング信号増幅器、18はレベル識別器である。
FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a PIN photodiode as a light receiving element, 12 is a variable resistor constituting a bias circuit, 13 is a series resistor, 14 is a preamplifier, and 15 is a main amplifier. , 16 is a tank circuit, 17 is a timing signal amplifier, and 18 is a level discriminator.

PINフォトダイオード11により変換された電気信号
は、前置増幅器14及び主増幅器15により増幅され、
タンク回路16及びレベル識別器18に加えられ、タン
ク回路16で抽出され、タイミング信号増幅器17で増
幅されたタイミング信号はレベル識別n18にレベル識
別のタイミング信号として加えられ、レベル識別器18
から受信データが出力される。
The electrical signal converted by the PIN photodiode 11 is amplified by a preamplifier 14 and a main amplifier 15,
The timing signal added to the tank circuit 16 and the level discriminator 18, extracted by the tank circuit 16, and amplified by the timing signal amplifier 17 is added to the level discriminator n18 as a timing signal for level discrimination, and the timing signal is added to the level discriminator 18.
The received data is output from.

又PINフォトダイオード11には、可変抵抗12によ
り電源電圧VCCを調整してバイアス電圧を印加するも
のであり、バイアス電圧に対応してPINフォトダイオ
ード11の空乏層幅が変化し、端子間の静電容量が変化
する。
In addition, a bias voltage is applied to the PIN photodiode 11 by adjusting the power supply voltage VCC using a variable resistor 12, and the depletion layer width of the PIN photodiode 11 changes in accordance with the bias voltage, thereby reducing the static voltage between the terminals. Capacity changes.

PINフォトダイオード11の周波数特性は、(1)接
合容量と負荷抵抗とによるCR時定数、(2)空乏層内
での光キャリアの走行時間、(3)P層中及びN層中の
拡散電流成分、によって決まるものである。PINフォ
トダイオード11のバイアス電圧を低くした時は、空乏
層幅が狭い為、(3)の拡散電流が支配的となり、応答
速度は遅くなる。又バイアス電圧を、拡散電流が無視で
きる程、空乏層幅が拡がるまで高くすると、(2)によ
る周波数特性となり、光キャリアの走行時間で応答速度
が決定される。この場合の応答速度は、(3)に於ける
応答速度よりも速いものである。
The frequency characteristics of the PIN photodiode 11 are: (1) CR time constant due to junction capacitance and load resistance, (2) transit time of photocarriers in the depletion layer, (3) diffusion current in the P layer and the N layer. It is determined by the ingredients. When the bias voltage of the PIN photodiode 11 is lowered, since the depletion layer width is narrow, the diffusion current (3) becomes dominant, and the response speed becomes slow. If the bias voltage is increased until the depletion layer width is widened to the extent that the diffusion current is negligible, the frequency characteristic will be as shown in (2), and the response speed will be determined by the transit time of the photocarriers. The response speed in this case is faster than the response speed in (3).

又(2)による場合、キャリアが空乏層を走行するのに
成る時間を要する為、高速で変化する光に対しては、そ
の速度に対応して変換効率が低下する。この変換効率が
3dB低下する周波数を高域カットオフ周波数fcとす
ると、走行時間t1に反比例する。空乏層幅をW、キャ
リア速度をVとすると、 t r =W / v             ・−
・(11であるから、カットオフ周波数fcは、一般に
次のように表される。
In the case of (2), it takes time for carriers to travel through the depletion layer, so for light that changes at high speed, the conversion efficiency decreases in proportion to the speed. If the frequency at which this conversion efficiency decreases by 3 dB is the high cutoff frequency fc, it is inversely proportional to the travel time t1. When the depletion layer width is W and the carrier velocity is V, tr = W / v ・-
(Since 11, the cutoff frequency fc is generally expressed as follows.

f c= 0.44 v / W         −
・・(2)即ち、バイアス電圧を高(すると、空乏層幅
Wが太き(なるが、キャリア速度Vが更に大きくなって
、カットオフ周波数数fcが高くなるから、PINフォ
トダイオード11の周波数特性が良くなる。逆にバイア
ス電圧を低くすると、空乏層幅Wは小さくなると共にキ
ャリア速度Vが一層小さくなり、カットオフ周波数fC
は低くなる。
f c = 0.44 v/W −
(2) That is, the bias voltage is increased (then the depletion layer width W becomes thicker), but the carrier velocity V becomes further larger and the cutoff frequency number fc becomes higher, so the frequency of the PIN photodiode 11 The characteristics improve. Conversely, when the bias voltage is lowered, the depletion layer width W becomes smaller, and the carrier velocity V becomes even smaller, reducing the cutoff frequency fC.
becomes lower.

第3図はPINフォトダイオードの周波数特性曲線図で
あり、AβGaAs半導体レーザの出力光をPINフォ
トダイオードで受光し、そのバイアス電圧を変化させた
時の周波数特性を示す。同図に於いて、曲TJaはバイ
アス電圧を5■、曲線すはIOV、曲線Cは20V、曲
線dは50Vとした場合を示し、バイアス電圧を5vと
した時の空乏層幅は9μm、50Vとした時の空乏層幅
は125μmであった。曲線a w dから判るように
、バイアス電圧を低くするに従って高周波頭載の出力が
低下する。従って、バイアス電圧を調整することにより
、PINフォトダイオード11の周波数特性を調整して
、所望の等化を行うことができる。それによって、従来
例に於ける等化回路を省略することが可能となる。
FIG. 3 is a frequency characteristic curve diagram of the PIN photodiode, which shows the frequency characteristics when the output light of the AβGaAs semiconductor laser is received by the PIN photodiode and its bias voltage is changed. In the same figure, the song TJa shows the case where the bias voltage is 5■, the curve is IOV, the curve C is 20V, and the curve d is 50V.When the bias voltage is 5V, the depletion layer width is 9μm and 50V. The depletion layer width at this time was 125 μm. As can be seen from the curve a w d, as the bias voltage is lowered, the high frequency overhead output decreases. Therefore, by adjusting the bias voltage, the frequency characteristics of the PIN photodiode 11 can be adjusted to achieve desired equalization. This makes it possible to omit the equalization circuit in the conventional example.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、受光素子としてPIN
フォトダイオード1.11を用い、そのバイアス電圧を
調整して空乏層幅の変化に対応する周波数特性を調整し
、受信信号の波形等化を行うものであり、それによって
、コイルやコンデンサ等からなる等化回路を省略するこ
とができ、光受信回路の小型化並びに経済化を図ること
ができるものである。更に、バイアス電圧の調整だけで
伝送周波数に対応した最適な等化を行うことができ、調
整が簡単である利点がある。
As explained above, the present invention uses PIN as a light receiving element.
It uses a photodiode 1.11 and adjusts its bias voltage to adjust the frequency characteristics that correspond to changes in the depletion layer width, thereby equalizing the waveform of the received signal. The equalization circuit can be omitted, and the optical receiving circuit can be made smaller and more economical. Furthermore, it is possible to perform optimal equalization corresponding to the transmission frequency simply by adjusting the bias voltage, which has the advantage of easy adjustment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理ブロック図、第2図は本発明の実
施例のブロック図、第3図は周波数特性曲線図、第4図
は従来例のブロック図である。 l、11はPINフォトダイオード、2はバイアス回路
、3は増幅部、4はタイミング再生部、5はレベル識別
部、I2は可変抵抗、13は直列抵抗、14は前置増幅
器、15は主増幅器、16はタンク回路、17はタイミ
ング信号増幅器、18はレベル識別器である。
FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a frequency characteristic curve diagram, and FIG. 4 is a block diagram of a conventional example. 1 and 11 are PIN photodiodes, 2 is a bias circuit, 3 is an amplifier section, 4 is a timing recovery section, 5 is a level discrimination section, I2 is a variable resistor, 13 is a series resistor, 14 is a preamplifier, and 15 is a main amplifier , 16 is a tank circuit, 17 is a timing signal amplifier, and 18 is a level discriminator.

Claims (1)

【特許請求の範囲】 受光素子により光信号を電気信号に変換し、該電気信号
を増幅、波形等化してレベル識別により受信データを出
力する光受信回路に於いて、前記受光素子としてのPI
Nフォトダイオード(1)と、 該PINフォトダイオード(1)へのバイアス電圧を調
整し、該PINフォトダイオード(1)の空乏層幅の変
化に対応した周波数特性を調整して波形等化を行うバイ
アス回路(2)を備えたことを特徴とする光受信回路。
[Scope of Claims] In an optical receiving circuit that converts an optical signal into an electrical signal by a light receiving element, amplifies the electrical signal, equalizes the waveform, and outputs received data by level discrimination, a PI as the light receiving element
Waveform equalization is performed by adjusting the bias voltages to the N photodiode (1) and the PIN photodiode (1), and adjusting the frequency characteristics corresponding to changes in the depletion layer width of the PIN photodiode (1). An optical receiving circuit comprising a bias circuit (2).
JP60243890A 1985-11-01 1985-11-01 Optical receiving circuit Pending JPS62105541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60243890A JPS62105541A (en) 1985-11-01 1985-11-01 Optical receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60243890A JPS62105541A (en) 1985-11-01 1985-11-01 Optical receiving circuit

Publications (1)

Publication Number Publication Date
JPS62105541A true JPS62105541A (en) 1987-05-16

Family

ID=17110512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60243890A Pending JPS62105541A (en) 1985-11-01 1985-11-01 Optical receiving circuit

Country Status (1)

Country Link
JP (1) JPS62105541A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453225A (en) * 1987-08-24 1989-03-01 Ricoh Kk Data processor
JPH04103021U (en) * 1991-02-08 1992-09-04 日本電気株式会社 optical receiver circuit
JP2007208746A (en) * 2006-02-02 2007-08-16 Oki Electric Ind Co Ltd Optical access network system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453225A (en) * 1987-08-24 1989-03-01 Ricoh Kk Data processor
JPH04103021U (en) * 1991-02-08 1992-09-04 日本電気株式会社 optical receiver circuit
JP2007208746A (en) * 2006-02-02 2007-08-16 Oki Electric Ind Co Ltd Optical access network system

Similar Documents

Publication Publication Date Title
US3728649A (en) Automatic equalizer for digital cable transmission systems
US4375037A (en) Receiving circuit
JPH11355080A (en) Receiver
CA1127299A (en) Biasing of magnetoresistive read head using gyrators
JP2655130B2 (en) Digital receiver circuit
US4890170A (en) Waveform equalization circuit for a magnetic reproducing device
JPS62105541A (en) Optical receiving circuit
EP0322803A2 (en) Automatic gain control amplifier for compensating cable loss
JPS63250928A (en) Light reception circuit
JPH05227104A (en) Light receiver
WO1985004773A1 (en) Apparatus for increasing the dynamic range in an integrating optoelectric receiver
KR101048019B1 (en) High Speed Single Chip CMOS Optical Receiver
WO1990012452A1 (en) Optical receivers
JP2571363B2 (en) Integrated circuit for receiving PCM optical communication
SU1647847A1 (en) Amplifying device
KR101061137B1 (en) High speed adaptive equalizer and its control method
JPH0222873A (en) Temperature compensation circuit of bias circuit for avalanche photodiode
JPH02206261A (en) Optical input disconnecting/detecting circuit
JPH03140026A (en) Optical reception circuit
JPS61177041A (en) Photodetecting circuit
JPS6187440A (en) Optical signal detector
JP2677186B2 (en) Timing extraction circuit
JPS6373723A (en) Optical reception circuit
JPH0918026A (en) Photoreceiving module
JPH079450Y2 (en) Optical receiver circuit