JP2007208746A - Optical access network system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical access network by which a high speed signal is transmitted/received and the number of subscribers can be increased without increasing the number of wavelength to be used. <P>SOLUTION: An optical line terminating device 100 and an optical terminal 10 are coupled to each other via an optical fiber transmission path 70, an optical multiplexer/demultiplxer 66 and a plurality of branching optical fiber transmission paths. The optical line terminating device 100 and the optical terminal are constituted by providing an optical processing part 12 (102) and an electric processing part 14 (104) thereto. The optical processing part is equipped with a light emitting element 20 (122) and a light receiving element 18 (126). The electric processing part is equipped with a transmission signal processing part 24 (106) which encodes a transmission signal to generate an encoded transmission signal in the form of an electric signal and a receiving signal processing part 22 (108) which decodes a code division multiplexing signal converted into the form of the electric signal from the form of an optical signal by the light receiving element to take out a receiving signal. A decoding processing circuit 30 provided to the receiving signal processing part is constituted by providing an analog matched filter 44 and a determination circuit 46 thereto. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an optical access network system for communication between a business operator and a subscriber using a Code Division Multiplexing (CDM) method in a PON (Passive Optical Network).

  Attention has been focused on an optical access network system in which a provider (hereinafter sometimes referred to as a “center”) and a plurality of subscribers (hereinafter also referred to as “users”) are connected via a PON. ing. In the following description, the provider side device may be referred to as an optical line terminal device or OLT (Optical Line Terminal), and the subscriber side device may be referred to as an optical terminal device or ONU (Optical Network Unit).

  PON is an optical fiber transmission line that is connected to an optical multiplexer / demultiplexer, which is a passive element, and branches one optical fiber transmission line into multiple optical fiber transmission lines. A network that connects a plurality of optical terminal devices to each other (for example, see Non-Patent Document 1). By adopting PON for the network connecting the center and the user, the optical fiber transmission line between the center and the optical multiplexer / demultiplexer can be shared by a plurality of users, and the equipment cost can be reduced.

  In the conventional optical access network system using PON, a time division multiplexing (TDM) method is adopted, and the user assigned to each channel is identified by controlling the time slot of the TDM signal ( For example, see Non-Patent Document 2.) Here, an optical signal having a wavelength different from a signal from the user to the center (hereinafter, also referred to as “upstream signal”) and a signal from the center to the user (hereinafter also referred to as “downstream signal”). Is used. This is because the upstream signal and downstream signal share a single optical fiber transmission line, so that the upstream signal and downstream signal are identified based on the difference in wavelength. The upstream signal and the downstream signal are separated and combined by an optical bandpass filter, and the signal between each user and the center is multiplexed and demultiplexed by an optical multiplexer / demultiplexer.

  On the other hand, in an optical access network system using PON, a method of transmitting an uplink signal by a wavelength division multiplexing (WDM) system has also been studied (for example, see Non-Patent Document 3). However, in order to increase the number of channels to be multiplexed (in this case, the number of users), since the usable wavelength band has a finite width, it is necessary to narrow the wavelength interval assigned to adjacent channels. In order to narrow the wavelength interval in this way, the wavelength stability of the light source is necessary, and a lot of equipment costs are required to ensure this stability.

  Therefore, it is desired to increase the number of channels to be multiplexed and substantially increase the transmission capacity without increasing the number of wavelengths to be used. As one of the methods, a method of performing communication between the center and the user by CDM transmission has been studied (for example, see Patent Document 1).

  In the communication method disclosed in Patent Document 1, an electric signal to be transmitted is code-multiplied, up-converted to a radio frequency (RF) signal, and then converted to an optical transmission signal. In addition, in the passive subscriber network disclosed in Patent Document 2, a method is employed in which an electric signal to be transmitted is code-multiplied and then converted into an optical transmission signal and transmitted, and in addition to this, WDM The system is also adopted. Here, the transmission optical signal and the reception optical signal are combined and branched by an optical circulator, and the same wavelength is used for the transmission optical signal and the reception optical signal.

  In each of the devices disclosed in Patent Documents 1 and 2, in order to receive a signal, the received signal is multiplied by a code synchronized with the transmission side. A configuration example of a receiver used for this purpose is disclosed in Non-Patent Document 4. In this receiver, an RF signal is converted into a baseband electric signal, and then A / D converted, and an autocorrelation waveform is generated by a digital shift register and a digital correlation operation device, whereby a received signal is extracted.

By adopting the CDM method for PON, the number of channels to be multiplexed (corresponding to the number of users) can be increased without increasing the number of wavelengths used.
Yokota, et al., “Optical Access System ATM-PON” Oki Electric Research and Development No.182, Vol. 67, No. 1, April 2000 Ian M. McGregor, et al. "Implementation of a TDM Passive Optical Network for Subscriber Loop Applications", J. Lightwave Technology, Vol. 7, No. 11, November 1989 KW Lim, et al. "Fault Localization in WDM Passive Optical Network by Reusing Downstream Light Sources", IEEE Photonics Technology Letters Vol. 17, No. 12, December 2005 Rushikesh S. Kalaspurkar, et al. "Performance Evaluation of a Recurring State Dynamic Digital Matched Filter for DS-CDMA", IEEE 2003 Special Table 2001-512919 JP 2004-282742 A

  However, if an optical access method based on PON including a step of code-multiplying an electric signal to be transmitted and up-converting to an RF signal and an A / D conversion step by an A / D converter is executed, the following problem arises. In other words, a case where a high-speed signal (a high bit rate signal) having a bit rate of 100 Mbit / s is transmitted and received will be described as an example. In this case, the spreading rate required to encode the signal with a code having a code length of 16 (the code length will be described later) is at least 1.6 Gbit / s. Furthermore, since the frequency of about 8 times is required, a carrier wave of 12.8 GHz or more is required. Therefore, it is necessary to operate the A / D converter and the digital multiplier that code-multiplies the electric signal to be transmitted at a speed of at least 1 Gbit / s. At present, it is difficult to obtain an A / D converter and a digital multiplier that can be operated at such a high speed.

  Also, in the conventional PON optical access network system, the upstream signal and the downstream signal are different in order to prevent reflection noise from being generated in an optical connector or the like for connection to the optical multiplexing / demultiplexing device provided in the optical transmission line. Wavelength light is used. For this reason, every time one subscriber terminal is added, two types of light having different wavelengths are required, and the number of light having different wavelengths is extremely large.

  Accordingly, an object of the present invention is first to provide an optical access network system based on PON capable of transmitting and receiving a high-speed signal. A second object is to provide a PON optical access network system in which the number of wavelengths to be used does not need to be increased as in the conventional optical system of the same type even when the number of subscribers is increased.

  The present invention relates to an optical access network system that performs bidirectional optical communication by code division multiplexing between an optical line terminating device that is a device installed on a provider side and an optical terminal device that is a device installed on a user side. About. The optical line termination device and the plurality of optical terminal devices are coupled via an optical fiber transmission line, an optical multiplexer / demultiplexer, and a plurality of branch optical fiber transmission lines. The optical fiber transmission line is provided with an optical coupler at one end, and an optical line terminator is coupled to the other end of the optical fiber transmission line. The optical fiber transmission line is branched into a plurality of branched optical fiber transmission lines by an optical multiplexer / demultiplexer, and one optical terminal device is coupled to each of the branched optical fiber transmission lines.

  Different codes are assigned to each of the plurality of optical terminal apparatuses, and bidirectional optical communication by code division multiplexing is performed between the optical line termination apparatus and the plurality of optical terminal apparatuses. Each of the optical line termination device and the plurality of optical terminal devices receives a transmission signal processing unit that encodes a transmission signal to generate and output a coded transmission signal, and a code division multiplexed signal transmitted by code division multiplexing And a reception signal processing unit for decoding the code division multiplexed signal and extracting the reception signal.

  In order to achieve the above object, the received signal processing unit of the optical access network system of the present invention comprises a decoding processing circuit for decoding a code division multiplexed signal, the decoding processing circuit comprising an analog matched filter and And a determination circuit. The analog matched filter includes an analog shift register, a plus signal adder, a minus signal adder, and an analog addition for adding output signals from the plus signal adder and the minus signal adder. And a low-pass filter.

  The transmission signal processing unit may include a code adding circuit that encodes the transmission signal, and a delay circuit that is connected to a subsequent stage of the code adding circuit and adjusts and outputs the phase of the encoded transmission signal. Is preferred.

  According to the optical access network system of the present invention, the decoding processing circuit included in the reception signal processing unit includes an analog matched filter and a determination circuit, and the analog matched filter includes an analog shift register, a plus signal, and the like. Therefore, a high-speed signal can be transmitted and received because the adder, the negative signal adder, the analog adder, and the low-pass filter are included. That is, the encoded signal is multiplexed and transmitted as the base signal, and the received signal processing unit performs decoding using an analog matched filter that does not use an A / D converter, thereby transmitting and receiving high-speed signals. It becomes possible to do.

  In addition, the transmission signal processing unit includes a delay circuit that adjusts the phase of the encoded transmission signal, so that the transmission signal is generated in an optical connector or the like for connection with an optical multiplexing / demultiplexing element provided in the optical transmission line. It is possible to prevent the problem of mixed reflection noise. For this reason, it is not necessary to use light of different wavelengths for the upstream signal and the downstream signal, and it is not necessary to increase the number of lights having different wavelengths.

  In the analog matched filter provided in the reception signal processing unit, the code division multiplexed signal is decoded. When the peak of the autocorrelation waveform obtained as a result is compared with the peak of the crosscorrelation waveform, the peak of the crosscorrelation waveform is small. Therefore, the autocorrelation waveform is generated by shifting the autocorrelation waveform generated by decoding the transmission signal and the crosscorrelation waveform generated by decoding the reflection noise component generated in the optical connector on the time axis. The peak can be easily determined by the determination circuit. This easy-to-determine state refers to a state in which the S / N ratio with respect to the peak of the autocorrelation waveform of the decoded output signal output from the analog matched filter is large.

  Shifting the autocorrelation waveform and the cross-correlation waveform described above on the time axis can be easily realized by adjusting the phase of the transmission signal using a delay circuit included in the transmission signal processing unit.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Each figure shows an example of the configuration according to the present invention, and only schematically shows the arrangement relationship of each component to the extent that the present invention can be understood, and the present invention is limited to the illustrated example. is not. In the following description, specific materials and conditions may be used. However, these materials and conditions are only one of preferred examples, and are not limited to these. Moreover, in each figure, the same component is shown with the same number, and the overlapping description may be omitted. Further, in the schematic block configuration diagram shown below, the path of an optical signal such as an optical fiber is indicated by a thick line, and the path of an electrical signal is indicated by a thin line.

<First embodiment>
The configuration and operation of the optical access network system of the first embodiment will be described with reference to FIG. FIG. 1 is a schematic block diagram of an optical access network system according to the first embodiment. The optical access network system shown in FIG. 1 assumes a case where the number of subscribers (number of users) is 4, that is, the case where there are four optical terminal devices. However, the following explanation is valid. In FIG. 1, in order to identify a plurality of optical terminal devices, the optical terminal device assigned the first channel is represented as ONU-1, and the optical terminal device assigned the fourth channel is represented as ONU-4. . All of ONU-1 to ONU-4 have the same configuration. In the following description of the optical access network system of the first embodiment, when the structure of the optical terminal device is described, it is generally described as the optical terminal device 10 and described.

  The optical access network system of the first embodiment includes an optical line termination device 100 that is a device installed on the provider side and an optical terminal device (ONU-1 to ONU-4 that is installed on the user side) The optical access network system performs bidirectional optical communication by code division multiplexing with the optical terminal device 10. The optical line termination device 100 and the optical terminal device 10 are coupled via an optical fiber transmission line 70, an optical multiplexer / demultiplexer 66, and a plurality of branched optical fiber transmission lines.

  The optical fiber transmission line 70 is provided with an optical coupler 66 at one end, and the optical line terminator 100 is coupled to the other end of the optical fiber transmission line 70. Further, the optical fiber transmission line 70 is branched into a plurality of branched optical fiber transmission lines by an optical coupler 66, and one optical terminal device is coupled to each of the branched optical fiber transmission lines. In FIG. 1, the optical fiber transmission line connecting ONU-1 is represented as a branched optical fiber transmission line 74, and the optical fiber transmission line connecting ONU-4 is represented as a branched optical fiber transmission line 76.

  Different codes are assigned to each of these optical terminal devices (ONU-1 to ONU-4), and bidirectional optical transmission using code division multiplexing is performed between the optical line termination device 100 and these optical terminal devices. Communication takes place.

  The optical terminal device 10 includes an optical processing unit 12 and an electrical processing unit 14. The light processing unit 12 is a light emitting element 20 for converting the encoded transmission signal from the electric signal form to the optical signal form, and a light receiving element for converting the code division multiplexed signal from the optical signal form to the electric signal form. Has 18.

  The electrical processing unit 14 encodes the transmission signal to generate an encoded transmission signal in the form of an electrical signal, and the code converted from the optical signal form to the electrical signal form by the light receiving element 18 And a reception signal processing unit 22 for decoding the division multiplexed signal and extracting the reception signal.

  The received signal processing unit 22 includes a decoding processing circuit 30 that performs processing for decoding the code division multiplexed signal, an automatic gain control (AGC) element 28, a clock signal reproduction circuit 34, and a frequency divider. 38, and a second delay circuit 40 (denoted as delay circuit 2 in FIG. 1) 40. The transmission signal processing unit 24 includes an encoding processing circuit 82 and a driver 60. As the driver 60, an amplifier (AMP: Amplifire) is used.

  The optical access network system according to the present invention is characterized in that the decoding processing circuit 30 includes an analog matched filter 44 and a determination circuit 46. In particular, the configuration of the analog matched filter 44 is characteristic. Although details will be described later, it is possible to increase the transmission / reception speed of the process for decoding the code division multiplexed signal by the analog matched filter 44 and the determination circuit 46.

  On the other hand, similarly to the optical terminal device 10, the optical line termination device 100 includes an optical processing unit 102 and an electric processing unit 104. Similar to the optical processing unit 12 of the optical terminal device 10, the optical processing unit 102 includes a light emitting element 122 and a light receiving element 126. The electrical processing unit 104 includes a transmission signal processing unit 106, a reception signal processing unit 108, and a clock signal generation circuit 110.

  The transmission signal processing unit 106 is an encoding processing circuit sequence 116 including in parallel an encoding processing circuit to which the same code as that assigned to each of the transmission signal processing units OUN-1 to ONU-4 is assigned. And a driver 120. The encoding processing circuits having the same configuration as each of the transmission signal processing units of OUN-1 to ONU-4 are denoted by reference numerals 1 to 4 in FIG. Signals output from each of the encoding processing circuits indicated by reference numerals 1 to 4 are combined by the electric signal combiner 118 and input to the driver 120.

  Further, the received signal processing unit 108 is a decoding processing circuit sequence including in parallel decoding processing circuits to which the same code as the code assigned to each of the received signal processing units OUN-1 to ONU-4 is assigned. 132 and an automatic gain control element 128. Decoding processing circuits to which the same codes as those assigned to the received signal processing units of OUN-1 to ONU-4 are assigned are shown as decoding 1 to decoding 4 in FIG. The signal output from the automatic gain control element 128 is branched by the electric signal branching unit 130 and input to each of the decoding processing circuits indicated as decoding 1 to decoding 4.

  A clock signal is supplied from the clock signal generation circuit 110 to the transmission signal processing unit 106 and the reception signal processing unit 108. The clock signal supplied from the clock signal generation circuit 110 is a clock signal serving as a reference for this optical access network system. In the optical terminal device 10, the clock signal recovery circuit 34 extracts this clock signal from the received code division multiplexed signal and uses it for decoding the code division multiplexed signal.

  The optical access network system having the above-described configuration shown in FIG. 1 operates as described below.

  First, the downlink signal will be described taking the first channel as an example. The transmission signal of the first channel (shown as “transmission signal input ch1” of the optical line termination device 100 in FIG. 1) is an encoding processing circuit provided in the electrical processing unit 104 of the optical line termination device 100. The signal is input to the encoding processing circuit represented by “Code 1” in the column 116, encoded, and output as an encoded transmission electrical signal. The encoded transmission electric signal is multiplexed by the electric signal multiplexer 118 and input to the driver 120 as a code division multiplexed electric signal and amplified, and the amplified code division multiplexed electric signal is provided in the optical processing unit 102. It is converted into an optical signal by the light emitting element 122 and output as a code division multiplexed optical signal. As the light emitting element 122, for example, a semiconductor laser can be used.

  The code division multiplexed optical signal is input to the optical processing unit 12 of the optical terminal device 10 through the optical coupler 124 and the optical connector 72, and through the optical fiber transmission line 70, the optical connector 68, the optical multiplexer / demultiplexer 66, and the optical connector 61. Is done. The code division multiplexed optical signal input to the optical processing unit 12 is input to the light receiving element 18 via the optical coupler 16 included in the optical processing unit 12, and is converted into a code division multiplexed electric signal. Input to the electrical processing unit 14. As the light receiving element 18, for example, a photodiode can be used.

  The code division multiplexed electric signal input to the electric processing unit 14 is branched into two by an electric signal branching unit 26, and one is input to the clock signal regeneration circuit 34 and the other is input to the automatic gain control element 28. A clock signal is extracted from the code division multiplexed electric signal input to the clock signal reproduction circuit. Further, the code division multiplex electric signal input to the automatic gain control element 28 is arranged as a code division multiplex electric signal having a constant voltage value set in the automatic gain control element 28 regardless of its strength, The data is input to the decryption processing circuit 30. This constant voltage value is equal to the input level of an analog shift register that is a constituent element of the analog matched filter 44 included in the decoding processing circuit 30.

  The code division multiplexed electric signal whose voltage value has been adjusted is first decoded by an analog matched filter 44 provided in the decoding processing circuit 30 and input to the determination circuit 46. The decision circuit 46 extracts and outputs only the autocorrelation waveform component from the signal decoded by the analog matched filter 44. That is, the received signal generated from this autocorrelation waveform component is the signal component received by ONU-1 of the first channel.

  As described above, the downlink signal, that is, the transmission signal transmitted from the optical network unit 100 to the optical terminal device 10 is transmitted as a code division multiplexed optical signal that is encoded and multiplexed. Then, in the optical terminal device 10, the code division multiplexed optical signal is converted into a code division multiplexed electric signal and decoded. That is, all the decoding processes in the optical terminal device 10 are executed in the state of electrical signals.

  The optical access network system according to the present invention is characterized by an electric processing unit that encodes a transmission signal and decodes a reception signal, and most of the following description is mainly about the operation of the electric processing unit. A signal necessary for explaining the operation of the electric processing unit is an encoded transmission electric signal or a code division multiplexed electric signal. Therefore, in the following description, it is not distinguished whether it is an optical signal or an electric signal unless particularly necessary. In other words, the code division multiplexed optical signal or the code division multiplexed electric signal is expressed as a code division multiplexed signal without clearly indicating whether it is an electric signal or an optical signal.

  Next, the uplink signal will be described taking the first channel as an example. The transmission signal of the first channel (shown as “transmission signal input” of the optical terminal device 10 in FIG. 1) is a code provided in the transmission signal processing unit 24 of the electrical processing unit 14 of the optical terminal device 10. Is input to the encoding processing circuit 82, encoded, and output as an encoded transmission signal. The encoded transmission signal is input to the driver 60 via the first delay circuit 58 (denoted as delay circuit 1 in FIG. 1) 58 and amplified. The amplified transmission signal is transmitted to the optical processing unit 12. It is converted into an optical signal by the light emitting element 20 comprising The light emitting element 20 can use a semiconductor laser.

  The encoded transmission signal is input to the optical multiplexer / demultiplexer 66 through the optical coupler 16 and the optical connector 61 to become a code division multiplexed signal, and is transmitted through the optical connector 68, the optical fiber transmission line 70, and the optical connector 72 to the optical line. Input to the optical processing unit 102 of the termination device 100. The code division multiplexed signal input to the optical processing unit 102 is input to the light receiving element 126 via the optical coupler 124 included in the optical processing unit 102 and converted into an electric signal, and the electric processing unit 104 of the optical line termination device 100 is converted into an electric signal. Is input. As the light receiving element 126, a photodiode can be used.

  The code division multiplexed signal input to the electric processing unit 104 is input to the automatic gain control element 128 included in the reception signal processing unit 108, and a constant voltage set in the automatic gain control element 128 regardless of its strength. It is arranged as an encoded received electrical signal having a value, and is input to a decoding processing circuit represented by “decoding 1” in the decoding processing circuit array 132. In this decoding processing circuit, processing similar to that of the decoding processing circuit 30 provided in the optical terminal device 10 is performed, and a signal transmitted from the ONU-1 of the first channel is generated and output.

<Encoding process>
A process of encoding a transmission signal will be described with reference to FIGS. 2A1 to 2C, taking the first channel as an example. In FIGS. 2A1 to 2C, the horizontal axis and the vertical axis are omitted, but the direction of the horizontal axis indicates the direction of the time axis, and the direction of the vertical axis indicates the signal strength. 2 (A1) and (A2) show the transmission signal and the encoded transmission signal of the first channel, respectively, and FIGS. 2 (B1) and (B2) show the transmission signal and the encoded transmission signal of the second channel, respectively. Show. FIG. 2C shows a time waveform of a code division multiplexed signal in which the encoded transmission signal of the first channel and the encoded transmission signal of the second channel are combined. In FIG. 2 (A1) to (C), the 0 level of the signal is indicated by a dashed line. The level 0 or higher is represented as “1”, and the level 0 or lower is represented as “−1”.

  The transmission signal of the first channel shown in FIG. 2 (A1) assumes the case of (1, 0, 1,...) And shows its time waveform. FIG. 2 (A2) assumes the code given by (1, 0, 0, 1) having a code length of 4, and the time of the encoded transmission signal of the first channel generated by encoding with this code The waveform is shown. Further, the transmission signal of the second channel shown in FIG. 2 (B1) assumes the case of (1, 1, 0,...) And shows its time waveform. FIG. 2 (B2) assumes the code given by (1, 0, 1, 0) having a code length of 4, and the time of the encoded transmission signal of the second channel generated by encoding with this code The waveform is shown.

  Here, the number of terms in the sequence consisting of “0” and “1” defining the code may be referred to as a code length. In this example, the number sequence that defines the code is (1, 0, 0, 1) or (1, 0, 1, 0), and since the number of terms in this number sequence is 4, the code length is 4. Become. In addition, a number sequence giving a code is called a code sequence, and each term “0” and “1” of the code sequence is sometimes called a chip. In addition, 0 and 1 themselves may be referred to as code values. The time width (also referred to as a time slot) assigned to one bit of the transmission signal is the reciprocal of the bit rate that is the transmission speed of the transmission signal. The reciprocal of the time width allocated to one chip of the code is sometimes called a chip rate.

  In encoding, 4 chips constituting a code are allocated to a time slot allocated to 1 bit of a transmission signal. That is, on the time axis, the encoded signal corresponding to the sequence (1, 0, 0, 1) or (1, 0, 1, 0) that defines the code within one bit of the transmission signal is completely contained. Are arranged on the time axis.

The meaning of encoding a transmission signal with a code having a code length of 4 is the product D of the transmission signal (hereinafter also referred to as “D”) and the encoded signal (hereinafter also referred to as “C”). This corresponds to finding xC. In the following description, when it is necessary to distinguish which channel corresponds to D or C, the number of channels is added. For example, D and C of the first channel are denoted as D ₁ and C ₁ , respectively. The same applies to the second channel and the like.

  Specifically, the sign assignment circuit for obtaining the product D × C includes EXNOR (exclusive sieve), which is a gate circuit in which an inverter is connected to the output of an exclusive OR operation EXOR (exclusive or OR) gate. Noah) circuit is used. In this case, a transmission signal, an encoded transmission signal, and the like expressed as binary signals of 1 and 0 are converted into binary signals of 1 and -1. Specifically, the bias voltage of the transmission signal and the encoded transmission signal may be adjusted to change the center of the amplitude of these signals to the 0 V level.

  Since the transmission signal of the first channel shown in FIG. 2 (A1) is (1, 0, 1,...), When this is converted into a binary signal of 1 and -1, (1, -1, 1 , ...). Since the code used to encode the transmission signal of the first channel is (1, 0, 0, 1), when this is converted into a binary signal of 1 and -1, (1, -1,- 1, 1).

  The first bit of the transmission signal of the first channel is “1”, the second bit is “0”, and the third bit is “1”. Here, if the transmission signal of the first channel is encoded with the code given by (1, -1, -1, 1), the first bit "1" is (1, -1 , -1, 1), the second bit "-1" is encoded with the code given by (1, -1, -1, 1), and the third This means that the bit “1” is encoded with the code given by (1, −1, −1, 1). Although not shown, it is the same for the fourth and subsequent bits to be encoded.

  Since encoding the transmission signal D with the code C is equivalent to obtaining the product D × C, the first bit “1” of the transmission signal is (the first bit of D ( 1)) × C (1, -1, -1, 1) = (1 × 1, 1 × (-1), 1 × (-1), 1 × 1) = (1, -1, -1, 1) is encoded. The second bit “−1” of the transmission signal is (the second bit of D (−1)) × C (1, −1, −1, 1) = ((− 1) × 1 , (-1) x (-1), (-1) x (-1), (-1) x 1) = (-1, 1, 1, -1). The same applies to the third bit. Therefore, the encoded transmission signal obtained by encoding the transmission signal of the first channel shown in FIG. 2 (A1) is ((1, -1, -1, 1), (-1 , 1, 1, -1), (1, -1, -1, 1)) = (1, -1, -1, 1, -1, 1, 1, -1, 1, -1, -1 , 1, ...) (Fig. 2 (A2)).

  In addition, the transmission signal of the second channel shown in FIG. 2 (B1) is obtained by converting the code (1, 0, 1, 0) into a binary signal of 1 and -1, (1, -1, 1, -1) The encoding is the same as in the case of the first channel. The first bit “1” of the transmission signal is (D 1st bit (1)) × C (1, −1, 1, −1) = (1 × 1, 1 × (− 1), 1 × 1, 1 × (-1) = (1, -1, 1, -1) Since the second bit of the transmission signal is also “1”, the second of D The th bit is also encoded as (1, -1, 1, -1).

  Since the third bit is “−1” (the third bit of D (−1)) × C (1, −1, 1, −1) = ((− 1) × 1, (− 1) × (-1), (-1) × 1, (-1) × (-1) = (-1, 1, -1, 1). The encoded transmission signal obtained by encoding the transmission signal of the second channel shown is ((1, -1, 1, -1), (1, -1, 1, -1) as described above. , (-1, 1, -1, 1)) = (1, -1, 1, -1, 1, -1, 1, -1, -1, 1, -1, 1, ...) (Fig. 2 (B2)).

  1st channel coded transmission signal (1, -1, -1, 1, -1, 1, 1, -1, 1, -1, -1, 1, ...) and 2nd channel coding The code division multiplexed signal given as the sum of the transmission signals (1, -1, 1, -1, 1, -1, 1, -1, -1, 1, -1, 1, ...) is ( 1 + 1, -1-1, -1 + 1, 1-1, -1 + 1, 1-1, 1 + 1, -1-1, 1-1, -1 + 1, -1-1, 1 + 1) = (+2, -2, 0, 0, 0, 0, 2, -2, 0, 0, -2, 2). Figure 2 (C) shows the time waveform of this code division multiplexed signal. Indicates.

  The code division multiplexed signal shown in FIG. 2C is converted into an optical signal and transmitted through the optical fiber transmission line. When it is received by the optical line terminal device or the optical terminal device, it is converted again into an electric signal and decoded to extract the received signal. Therefore, the absolute value of the amplitude of the time waveform of the code division multiplexed signal shown in FIG. 2 (C) has no essential meaning. Therefore, in the code division multiplexed signal shown in FIG. 2 (C), the center of the maximum value and the minimum value of the amplitude is set to 0 level, and the amplitude value is normalized to 1 (+1, -1, 0, 0, 0, 0, 1, -1, 0, 0, -1, 1) have the same meaning.

<Decryption process>
A process of decoding a code division multiplexed signal will be described with reference to FIGS. 3A to 3D, taking the first channel as an example. 3A and 3B, the horizontal axis indicates the direction of the time axis. Although the vertical axis is omitted, the direction of the vertical axis indicates the signal intensity. FIG. 3A shows a time waveform of a code division multiplexed signal input to an analog matched filter included in the decoding processing circuit. The center of the maximum value and the minimum value of the amplitude of the code division multiplexed signal shown in FIG. 2 (C) is set to 0 level, and the amplitude value is normalized to 1. FIG. 3 (B) shows a time waveform of a signal output after being decoded by an analog matched filter. As described later, the signal output from the analog matched filter includes an autocorrelation waveform component that is a reception signal component of the optical terminal device of the received channel, and a cross-correlation waveform component that is received by other than the optical terminal device of the received channel. Is the sum of That is, the cross-correlation waveform component becomes a noise component.

  FIG. 3 (C1) shows a time waveform of a signal output after the threshold value is determined by the determination circuit. FIG. 3C2 shows a time waveform of a clock signal for latching the signal shown in FIG. FIG. 3D shows a time waveform of a signal obtained by latching the signal output after the threshold determination shown in FIG. 3C1 is output with the clock signal shown in FIG. 3C2. The signal shown in FIG. 3D is a received signal. In FIG. 3 (C1), (C2) and (D), the horizontal and vertical axes are omitted, but the horizontal axis indicates the time axis and the vertical axis indicates the signal strength. . Also, the 0 level of the signal is indicated by a one-dot broken line.

  The determination circuit that performs determination processing on the signal output from the analog matched filter corresponds to the determination circuit 46 included in the decoding processing circuit 30 illustrated in FIG. Further, in FIG. 1, the signal output after the determination processing shown in FIG. 3 (C1) is performed, including a latch circuit for latching with the clock signal shown in FIG. The latch circuit itself is not shown.

  The meaning of encoding the transmission signal corresponds to obtaining the product D × C of the transmission signal D and the encoded signal C as described above. On the other hand, receiving a code division multiplexed signal that has been encoded and transmitted and decoding the code division multiplexed signal corresponds to re-encoding the code division multiplexed signal with the same code.

The code division multiplexed signal includes a first channel encoded transmission signal (D ₁ × C ₁ ), a second channel encoded transmission signal (D ₂ × C ₂ ), and a third channel encoded transmission signal (D ₃ × C ₁ ). C ₃ ), etc., which is the sum of all encoded transmission signals to be multiplexed. Therefore, the code division multiplexed signal is represented by (D ₁ × C ₁ ) + (D ₂ × C ₂ ) + (D ₃ × C ₃ ) +. Decoding this code division multiplexed signal with code C ₁ assigned to the first channel means {(D ₁ × C ₁ ) + (D ₂ × C ₂ ) + (D ₃ × C ₃ ) + ... .} × C ₁ (corresponding to encoding the code division multiplexed signal again with the same code).

That is, the time waveform of the signal decoded and output by the analog matched filter is {(D ₁ × C ₁ ) + (D ₂ × C ₂ ) + (D ₃ × C ₃ ) + ....} × C ₁ = (D ₁ × C ₁ ) × C ₁ + (D ₂ × C ₂ ) × C ₁ + (D ₃ × C ₃ ) × C ₁ + .... = D ₁ × C ₁ ² + (D ₂ x C ₂ x C ₁ ) + (D ₃ x C ₃ x C ₁ ) + .... Here, C ₁ ² = 1. This is because they are products of the same code, and all the chips constituting both codes have the same value, that is, “1” or “−1”. That is, when the calculation of C ₁ ² is seen for each chip of the code, 1 × 1 = 1 or (−1) × (−1) = 1 is always “1”. Therefore, the first term D ₁ × C ₁ ² representing the time waveform of the signal decoded and output by the above-mentioned analog matched filter becomes D ₁ , and the pulse D of each bit constituting the transmission signal of the first channel ₁ is played. That is, this component corresponds to the autocorrelation waveform component of the signal output after being decoded by the analog matched filter with respect to the transmission signal of the first channel.

On the other hand, the term following the second term representing the time waveform of the signal decoded and output by the analog matched filter is C ₁ × C _i ≠ 1 (where i = 2, 3,... Therefore, from the terms of (D ₂ × C ₂ ) × C ₁ and (D ₃ × C ₃ ) × C ₁ , the pulse D of each bit constituting the transmission signal of the second and third channels ₂ and D ₃ are not reproduced. That is, these components correspond to the cross-correlation waveform components of the signal output after being decoded by the analog matched filter with respect to the transmission signal of the first channel.

  As described above, according to the analog matched filter, it is possible to decode the code division multiplexed signal and reproduce the autocorrelation waveform component. In FIG. 3 (B), the pulse components shown on the time axis (indicated by P and Q in FIG. 3 (B)) are autocorrelation waveform components. Further, the cross-correlation waveform component is a noise component that falls between broken lines shown above and below across the time axis. In FIG. 3 (B), the shape of the cross-correlation waveform component is extremely complex, so the maximum and minimum levels are indicated by broken lines that are shown above and below the time axis, and the detailed shape is omitted. It is.

  The time waveform of the signal decoded and output by the analog matched filter shown in FIG. 3 (B) is processed by the decision circuit, and only the autocorrelation waveform component is extracted and the output signal is shown in FIG. 3 (C1). It is shown. The signal shown in FIG. 3 (C1) is latched by the clock signal shown in FIG. 3 (C2), and the received signal shown in FIG. 3 (D) is obtained.

  Next, the contents of the latch processing in the determination circuit will be described with reference to FIGS. 3 (C1), (C2), and (D). Since a known D flip-flop circuit or the like can be used as the latch circuit for performing the latch processing, description of the latch circuit itself is omitted. In this embodiment, MC100LVEL31 (manufactured by ON semiconductor) was used as the D flip-flop circuit.

  The time waveform shown in FIG. 3 (C1) is generated by processing the signal decoded and output by the analog matched filter shown in FIG. 3 (B) by a threshold processing circuit as will be described later. In other words, the threshold processing circuit plays a role of converting the analog decoded signal shown in FIG. 3 (B) into a digital decoded signal shown in FIG. 3 (C1). Therefore, the time waveform shown in FIG. 3 (C1) is characterized in that a rectangular wave (rectangular pulse) appears corresponding to the autocorrelation waveform component of the decoded and output signal shown in FIG. 3 (B). . The magnitude of the amplitude of the rectangular pulse is defined by the threshold processing circuit, and the magnitude of the amplitude of all the rectangular pulses appearing in FIG. 3 (C1) is constant. In FIG. 3 (C1), an example of this rectangular pulse is shown sandwiched between two downward arrows a and b respectively. As the threshold processing circuit, a suitable one from known comparators can be appropriately selected and used. In this example, MAX9600 (manufactured by MAXIM Integrated Products) was used.

  When the digital decoded signal shown in FIG. 3 (C1) and the clock signal shown in FIG. 3 (C2) are input to the D flip-flop circuit functioning as a latch circuit, the following processing is performed, The received signal shown in 3 (D) is obtained.

  The rising edge of the clock signal shown in FIG. 3 (C2) (for example, the moment indicated by X in FIG. 3 (C2)) corresponds to the peak of the autocorrelation waveform of the digital decoded signal (for example, FIG. 3 (C1) is sandwiched between two downward arrows with a and b attached to each other.) If there is an intensity corresponding to “1” from the output terminal of the D flip-flop circuit The signal begins to be output. Then, until the next rising edge of the clock signal (the moment indicated by Y in FIG. 3 (C2)), a signal having an intensity corresponding to “1” continues to be output from the output terminal of the D flip-flop circuit. At the moment, the signal changes from the output terminal of the D flip-flop circuit to a signal having the intensity equivalent to “-1”.

  Similarly, the next time the signal having the intensity corresponding to “1” starts to be output from the output terminal of the D flip-flop circuit is the moment when the clock signal indicated by Z in FIG. 3 (C2) rises. The output signal from the output terminal of the D flip-flop circuit changes to a signal having a strength corresponding to “-1” at the moment when the clock signal rises again (this moment deviates from FIG. 3 (C2)). ing.).

  As described above, when the rising signal of the clock signal is input to the D flip-flop circuit within the existence time of the rectangular pulse corresponding to the peak of the autocorrelation waveform of the digital decoded signal, it is shown in FIG. A rectangular pulse having an intensity corresponding to “1” of the received signal is generated. On the other hand, if the rising edge of the clock signal is input to the D flip-flop circuit outside the existence time of the rectangular pulse corresponding to the peak of the autocorrelation waveform of the digital decoded signal, the output terminal of the D flip-flop circuit The signal corresponding to “-1” is still output.

  As described above, the output terminal of the D flip-flop circuit is set to “1” in accordance with whether or not there is a rectangular pulse corresponding to the peak of the autocorrelation waveform of the digital decoded signal at the rising edge of the clock signal. A corresponding signal is output, or a signal corresponding to “−1” is output. As a result, the received signal is reproduced. The received signal shown in FIG. 3 (D) is a part of the transmission signal (1, -1, 1, ...) shown in FIG. 2 (A1). The part has been reproduced. In order to clearly indicate the portion corresponding to (1, -1, 1,...) In FIG. 3 (D), the signal values “1” and “−1” are shown in parentheses.

  As is clear from the above description, if there is no rectangular pulse corresponding to the peak of the autocorrelation waveform of the digital decoded signal at the moment of the rising edge of the clock signal, the reception signal shown in FIG. 3 (D) is generated. I can't. Therefore, it is necessary to adjust the relative positional relationship on the time axis between the digital decoded signal shown in FIG. 3 (C1) and the clock signal shown in FIG. 3 (C2). Adjustment of the relative positional relationship between the two will be described with reference to FIG.

  The code division multiplexed signal output from the light receiving element 18 is branched by the electric signal branching unit 26, and one of the branched signals is input to the clock signal recovery circuit 34, and the clock signal of the transmission rate frequency is recovered and output. . The clock signal having the transmission rate frequency is branched by the electric signal branching unit 36, and one of the branched signals is input to the frequency divider 38, converted into a clock signal having the base rate frequency, and output. Here, the transmission rate frequency refers to the frequency corresponding to the bit rate of the code division multiplexed signal, and the base rate frequency refers to the frequency corresponding to the bit rate of the transmission signal of each channel. That is, the frequency obtained by dividing the transmission rate frequency by the number of channels is the base rate frequency.

  The clock signal output from the frequency divider 38 is input to the second delay circuit 40, and its phase is adjusted and output. The clock signal output from the second delay circuit 40 is shown in FIG. 3 (C2). That is, the second delay circuit 40 can adjust the position of the clock signal shown in FIG. 3 (C2) on the time axis. This adjustment may be performed manually, but can also be performed automatically. One means for automating this adjustment is disclosed in an open patent publication (Japanese Patent Laid-Open No. 2005-33544).

  Here, the noise component included in the time waveform of the signal decoded and output by the analog matched filter shown in FIG. 3B will be described. In the optical terminal device 10 of the optical access network system shown in FIG. 1, a transmission signal is output from the transmission signal processing unit 24, while a reception signal is input to the reception signal processing unit 22. Here, a code for encoding and a code for decoding are assigned to each channel. These codes are the same. Therefore, there arises a problem that reflection noise generated in an optical connector or the like for connection with an optical multiplexing / demultiplexing element provided in the optical transmission line is mixed into a reception signal input to the reception signal processing unit.

  The mechanism of mixing the reflected noise into the received signal will be described with reference to FIG. FIG. 4 is a diagram for explaining how reflected light from the optical connector is mixed into the reception signal processing unit. In FIG. 4, only the portions necessary for explaining the mechanism of the mixing of reflected noise into the received signal are extracted from FIG. The transmission signal is output from the light emitting element 20 and input from the port 3 of the optical coupler 16, output from the port 1, and input to the optical connector 61. A part of the transmission signal is reflected from the optical connector 61 and input to the port 1 of the optical coupler 16. The reflected transmission signal is output from the port 2 of the optical coupler 16 and input to the light receiving element 18.

  Therefore, both the reception signal a input from the port 1 of the optical coupler 16 and output from the port 2 and a part b of the transmission signal reflected from the optical connector 61 are input to the light receiving element 18. A part b of this transmission signal is mainly input from port 3 of optical coupler 16 and output from port 1 is reflected from optical connector 61, input to port 1 again, and output from port 2 It has been done.

  With reference to FIGS. 5A and 5B, description will be made regarding a case where a signal in which a reception signal and a reflected transmission signal are mixed is decoded. FIGS. 5A and 5B are diagrams showing the relationship between the peak positions of the autocorrelation waveform when a signal in which a reception signal and a reflected transmission signal are mixed is decoded. The horizontal axis indicates the time axis and the vertical axis is omitted, but the signal intensity is indicated in the direction of the vertical axis.

  Since the transmission signal and the reception signal are signals encoded with the same code, the peak positions of both autocorrelation waveforms may coincide with each other. 5A and 5B, the peak indicated by c indicates the autocorrelation waveform of the received signal, and the peak indicated by r indicates the autocorrelation waveform of the reflected transmission signal. Fig. 5 (A) shows the case where the peak positions of the autocorrelation waveform of the received signal and the reflected transmission signal match, and Fig. 5 (B) shows the autocorrelation waveform of the received signal and the reflected transmission signal. This shows a case where the peak positions do not match.

  5 (A) and 5 (B), the cross-correlation waveform component of the received signal is a noise component that falls between the thick broken lines shown above and below across the time axis, and the cross-correlation waveform component of the transmission signal is the time axis. Is a noise component that falls between thin broken lines shown above and below. Since the shape of the cross-correlation waveform component is extremely complicated, the levels of the maximum value and the minimum value are indicated by broken lines that are shown above and below the time axis, and the detailed shape is omitted.

When the peak position of the autocorrelation waveform of the received signal and the reflected signal of the reflected transmission signal shown in Fig. 5 (A) match, the difference between the peak of the autocorrelation waveform of the received signal and the peak of the autocorrelation waveform of the transmission signal Is a net signal component, which is indicated by S ₁ in FIG. 5 (A). The value of N giving the S / N ratio in this case is the peak intensity of the autocorrelation waveform of the transmission signal, and is indicated by N ₁ in FIG. 5 (A).

On the other hand, if the peak positions of both autocorrelation waveforms shown in FIG. 5 (B) do not match, the difference between the peak of the autocorrelation waveform and the peak of the cross-correlation waveform component of the received signal is the net signal component, It is indicated by S ₂ in FIG. 5 (B). The value of N giving the S / N ratio in this case is the peak intensity of the cross-correlation waveform component of the received signal, and is indicated by N ₂ in FIG. 5 (B).

As shown in FIGS. 5 (A) and 5 (B), when S ₁ <S ₂ and N ₁ > N ₂ , the peak positions of both autocorrelation waveforms shown in FIG. 5 (B) do not match The S / N ratio S ₂ / N ₂ is larger than the S / N ratio S ₁ / N ₁ when the peak positions of both autocorrelation waveforms shown in FIG. That is, (S ₂ / N ₂ )> (S ₁ / N ₁ ). Therefore, since the S / N ratio can be increased by shifting the peak position of the autocorrelation waveform of the received signal and the peak position of the reflected signal autocorrelation waveform, the both can be increased in this way. It can be said that it is preferable to shift the peak positions of the signals.

  The peak position of the autocorrelation waveform of the reception signal and the reflected transmission signal is adjusted by adjusting the delay amount of the first delay circuit 58 shown in FIG. The case of the first channel will be described as an example. The encoded transmission signal output from the code adding circuit 56 is input to the first delay circuit 58 and the phase thereof is adjusted. Since the delay amount of the encoded transmission signal is adjusted in the first delay circuit 58, the peak position of the autocorrelation waveform of the transmission signal reflected from the optical connector 61 and the encoding output from the first delay circuit 58 The positional relationship on the time axis with the peak position of the autocorrelation waveform of the transmission signal can be adjusted. The interval between the peak positions of both autocorrelation waveforms changes in accordance with the delay amount given in the first delay circuit 58. That is, as shown in FIG. 5 (B), the peak positions of the autocorrelation waveforms of both do not match. The interval between the peak positions of the autocorrelation waveform of the received signal and the reflected transmission signal corresponding to the delay amount given in the first delay circuit 58 is shown in FIG. 5 (B) on the time axis with arrows at both ends. Shown with parallel line segments.

<Analog matched filter>
One of the features of the optical access network system of the present invention is that a code division multiplexed signal is decoded by an analog matched filter. Therefore, the configuration and operation of the analog matched filter will be described with reference to FIGS.

  6A and 6B are schematic block configuration diagrams of the analog matched filter. The analog matched filter includes an analog shift register 140, a plus signal adder 142, a minus signal adder 144, and output signals output from the plus signal adder 142 and the minus signal adder 144, respectively. An analog adder 146 for adding and a low-pass filter 148 are provided. The plus signal adder 142 and the minus signal adder 144 include an amplifier 150 and an inverting amplifier 152, respectively. The amplifier 150 and the inverting amplifier 152 are shown with their peripheral circuits omitted.

  A code division multiplexed signal output from the automatic gain control element 28 is input to an input terminal indicated as data input. A clock signal having a transmission rate frequency branched by the electric signal branching device 36 is input to an input terminal indicated as clock input.

  The analog matched filter shown in FIG. 6 (A) is designed on the assumption that decoding is performed using a code given by a sequence (1, 0, 0, 1). That is, it is assumed that decoding is performed using the code assigned to the first channel of the first embodiment. The code given by the sequence (1, 0, 0, 1) can be said to be the code given by the sequence (1, -1, -1, 1) when the binary representation of "1" and "-1" is displayed. .

  Here, for simplicity, first, only the component of the first channel in the code division multiplexed signal will be taken up and described. The code division multiplexed signal also contains encoded transmission signals of channels other than the first channel, but these are encoded with a code different from the code assigned to the first channel. Does not play.

  The encoded transmission signal of the first channel shown in FIG. 2 (A2) has the same time waveform as the transmission signal of the first channel having the time waveform shown in FIG. 2 (A1) by the analog matched filter. The reproduction as a received signal will be described.

  The analog shift register 140 is a shift register (hereinafter referred to as “CCD shift register”) formed by a charge coupled device CCD (Charge Coupled Device) having four stages (shown in order from the input side as 1, 2, 3, 4). Register ")). That is, the analog shift register 140 is a 4-bit CCD shift register. In the first embodiment, since it is assumed that encoding is performed with a code having 4 chips (a code having a code length of 4), a 4-stage CCD shift register is used. Actually, since a code with a long code length such as a code with 16 or 32 chips is used, a CCD shift register with a large number of stages such as a 16 or 32 stage CCD shift register is used, but the principle described below is It is the same.

  When each channel bit rate is 125 Mbit / s and 16 channels are encoded with an orthogonal code with a code length of 16 or multiplexed, or each channel bit rate is 62.5 Mbit / s and 32 channels are code length 32 In the case of encoding with an orthogonal code and multiplexing, the coding chip rate is 2 Gbit / s. That is, the charge between each stage of the CCD shift register may be shifted at 2 Gb / s. On the other hand, in the current CCD shift register, the speed of the charge shift between each stage is secured at about 10 Gbit / s. Therefore, according to the analog matched filter using the CCD shift register, the chip rate is Encoding that is 2 Gbit / s can be easily realized. That is, in PON, an optical access network system is easily realized for a carrier and a subscriber to perform 100 Mbit / s class communication using a code division multiplexing system.

A clock signal having a transmission rate frequency is input to the clock input terminal of the CCD shift register 140. A code division multiplexed signal (the encoded transmission signal shown in FIG. 2 (A2)) is input to the data input terminal of the CCD shift register 140. The input terminal of the first stage of the CCD shift register 140 shown in FIGS. 6 (A) and 6 (B) is indicated as D ₁ , and the output terminal is indicated as Q ₁ . In addition, the second, third, and fourth stage input terminals are denoted as D ₂ , D ₃ , and D ₄ , respectively, and the output terminals are denoted as Q ₂ , Q ₃ , and Q ₄ , respectively. Data input terminal of the CCD shift register 140 is connected to the input terminal D ₁ of the first stage.

  With reference to FIG. 6 (A), the principle by which the code division multiplexed signal of the first channel encoded with the code (1, -1, -1, 1) is decoded will be described.

First, the data input terminal D ₁ of the first stage of the CCD shift register, the code division multiplex signal, i.e., here, "1" (Fig first channel of encoded transmission signals shown in FIG. 2 (A2) When 2 CS1 and indicated time slot (A2) is set to 1.) is input, in synchronization with the clock signal, the output "1" from the output terminal to Q ₁ first stage . Then, "-1" in the first channel of encoded transmission signal to the data input terminal D ₁ of the first stage (time slot indicated as CS2 in FIG. 2 (A2) is -1.) Of When input, “−1” is output from the first stage output terminal Q ₁ and “1” is output from the second stage output terminal Q ₂ in synchronization with the clock signal. Thus successively CS3 and indicated time slot, when a signal CS4 and the indicated time slot is inputted to the data input terminal D ₁ of the first stage, in synchronization with a clock signal, first from the first stage From the four-stage output terminals, the previously output signals are shifted one by one and output.

At the stage where all the chips of the encoded transmission signal existing in the time slot from CS1 to CS4 are all input from the data input terminal of the analog shift register 140, the output terminals of the first to fourth stages, Q ₁ , Q ₂ , Q _3, and Q ₄ output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are (1, -1, -1, 1). That is, the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the first stage to the fourth stage are the voltage values at the positions indicated by F, G, H, I in the analog shift register 140. appear.

  The voltage value at position F and the voltage value at position I are input to the plus signal adder 142, combined by the electrical signal combiner 154, and input to the amplifier 150. The voltage value at position F and the position I Is output as a signal corresponding to the sum of the voltage values of On the other hand, the voltage value at position G and the voltage value at position H are input to the negative signal adder 144, combined by the electrical signal combiner 156, and input to the inverting amplifier 152, and the voltage value of the position G And a voltage value corresponding to the sum of the voltage value at position H (a negative value) is converted into a positive voltage value and output.

  The output signal from the amplifier 150 and the output signal from the inverting amplifier 152 are combined by the analog adder 146 and input to the low-pass filter 148.

  The low-pass filter 148 filters the base rate frequency signal out of the signal output from the analog adder 146 and serves to block high frequency noise components.

The encoded transmission signal, just steps chips that are time slots from CS1 to CS4 is all inputted from the data input terminal of the analog shift register 140 Q _1, Q _2, Q from ₃ and the output terminal of Q ₄ Since the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are (1, -1, -1, 1), the electric signal multiplexer 154 has a potential that is the potential at the positions F and I. 1 and the potential 1 are input, and the potential 2 is input to the amplifier 150. Further, the electric signal multiplexer 156 receives the electric potentials −1 and −1 which are the electric potentials at the G and H positions, and inputs the electric potential −2 to the inverting amplifier 152.

  Therefore, the amplifier 150 outputs a signal having a potential proportional to the potential 2 (here, the amplification factor is 1 for simplicity), and the inverting amplifier 152 inverts the potential −2 (here, the simple Therefore, the amplified signal of potential 2 is output, and both signals are combined by the analog adder 146 and passed through the low-pass filter 148 as the signal of potential 4, and the CCD shift register 140 Output from the data output terminal.

The next time the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 becomes (1, -1, -1, 1) is the chip that exists in the time slots from CS9 to CS12 Are all input from the data input terminal of the analog shift register 140. At this time as well, a signal having a potential of 4 is output from the data output terminal of the CCD shift register 140.

When the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is different from (1, -1, -1, 1), the data output of the CCD shift register 140 A signal having a potential of 4 or higher is never output from the terminal, and the potential is always less than 4. This is because the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is different from (1, -1, -1, 1), for example, (-1, -1, 1, 1 ) Etc., it is clear if the same explanation as above is considered.

  Next, with reference to FIG. 6 (B), the principle of decoding the code division multiplexed signal of the second channel encoded with the code (1, -1, 1, -1) will be described. The difference between the analog matched filter shown in FIG. 6 (A) and the analog matched filter shown in FIG. 6 (B) is that the signal input to the amplifier 150 and the inverting amplifier 152 is in any position of F, G, H, and I. The difference between taking out from. In the analog matched filter shown in FIG. 6A, the input signal to the amplifier 150 is taken out from the positions F and I, and the input signal to the inverting amplifier 152 is taken out from the positions G and H. On the other hand, in the analog matched filter shown in FIG. 6B, the input signal to the amplifier 150 is taken out from the G and I positions, and the input signal to the inverting amplifier 152 is taken out from the F and H positions. . As described above, an arbitrary code having a code length of 4 can be set depending on whether the signal input to the amplifier 150 and the inverting amplifier 152 is extracted from F, G, H, or I.

  Code-division multiplexed signals also contain encoded transmission signals of channels other than the second channel, but these are encoded with a code different from the code assigned to the second channel. Does not play.

  The encoded transmission signal of the second channel shown in FIG. 2 (B2) has the same time waveform as the transmission signal of the second channel having the time waveform shown in FIG. 2 (B1) by the analog matched filter. The reproduction as a received signal will be described. Also in the analog matched filter shown in FIG. 6 (B), the decoding operation is basically the same as that of the analog matched filter shown in FIG. 6 (A).

First, the data input terminal D ₁ of the first stage of the CCD shift register, the code division multiplex signal, i.e., here, "1" (FIG encoded transmission signal of the second channel shown in FIG. 4 (B2) When 2 CS1 and indicated time slot (B2) is set to 1.) is input, in synchronization with the clock signal, the output "1" from the output terminal to Q ₁ first stage . Then, "-1" of the second channel of the encoded transmission signal to the data input terminal D ₁ of the first stage (CS2 and indicated time slot of FIG. 2 (B2) is set to -1.) Of When input, “−1” is output from the first stage output terminal Q ₁ and “1” is output from the second stage output terminal Q ₂ in synchronization with the clock signal. Thus successively CS3 and indicated time slot, when a signal CS4 and the indicated time slot is inputted to the data input terminal D ₁ of the first stage, in synchronization with a clock signal, first from the first stage From the four-stage output terminals, the previously output signals are shifted one by one and output.

At the stage where all the chips of the encoded transmission signal existing in the time slot from CS1 to CS4 are all input from the data input terminal of the analog shift register 140, the output terminals of the first to fourth stages, Q ₁ , Q ₂ , Q ₃ and Q ₄ output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are (−1, 1, −1, 1). That is, the output locations (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the first to fourth stages are as voltage values at positions indicated by F, G, H, and I in the analog shift register 140. appear.

  The voltage value at position G and the voltage value at position I are input to the plus signal adder 142, combined by the electrical signal combiner 154, and input to the amplifier 150. Is output as a signal corresponding to the sum of the voltage values of On the other hand, the voltage value at position F and the voltage value at position H are input to the negative signal adder 144, combined by the electrical signal combiner 156, and input to the inverting amplifier 152, and the voltage value of the position F And a voltage value corresponding to the sum of the voltage value at position H (a negative value) is converted into a positive voltage value and output.

  The output signal from the amplifier 150 and the output signal from the inverting amplifier 152 are combined by the analog adder 146 and input to the low-pass filter 148.

The encoded transmission signal, just steps chips that are time slots from CS1 to CS4 is all inputted from the data input terminal of the analog shift register 140 Q _1, Q _2, Q from ₃ and the output terminal of Q ₄ Since the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are (-1, 1, -1, 1), the electric signal multiplexer 154 has a potential that is a potential at the positions of G and I. 1 and the potential 1 are input, and the potential 2 is input to the amplifier 150. In addition, the electric signal multiplexer 156 receives the electric potentials −1 and −1 which are the electric potentials at the positions F and H, and inputs the electric potential −2 to the inverting amplifier 152.

  Therefore, a signal having a potential proportional to the potential 2 is output from the amplifier 150, and a signal having a potential 2 in which the potential -2 is inverted is output from the inverting amplifier 152. Both signals are combined by the analog adder 146. The signal having the potential 4 is output from the data output terminal of the CCD shift register 140 through the low-pass filter 148.

The next value of the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is (-1, 1, -1, 1) is the chip in the time slot from CS5 to CS8 Are all input from the data input terminal of the analog shift register 140. At this time as well, a signal having a potential of 4 is output from the data output terminal of the CCD shift register 140.

When the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is different from (-1, 1, -1, 1), the data output from the CCD shift register 140 A signal having a potential of 4 or higher is never output from the terminal, and the potential is always less than 4.

As described above, only when the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 matches the set sign, the potential 4 from the data output terminal of the CCD shift register 140 Is output. This is a signal corresponding to the autocorrelation waveform. For example, in the time waveform of the signal obtained by decoding the encoded transmission signal of the first channel shown in FIG. 3 (B), the peaks indicated as P and Q are the data of the CCD shift register 140. This is a peak that appears at the moment when a signal having a potential of 4 is output from the output terminal.

<Determination circuit>
The configuration and operation of the determination circuit will be described with reference to FIGS. FIG. 7A is a schematic block configuration diagram of the determination circuit, and FIG. 7B shows a time waveform of the decoded signal output from the analog matched filter. FIG. 7C shows a time waveform of a signal output after threshold determination.

  The time waveform shown in FIG. 7 (B) corresponds to the time waveform of the signal decoded and output by the analog matched filter shown in FIG. 3 (B). Although FIG. 7 (B) and FIG. 3 (B) are apparently different, each figure is abstracted for convenience of explanation, and the time waveform of the actual signal is shown in FIG. 7 (B). close.

  The determination circuit includes a comparator 42 and a D flip-flop circuit 52. The decoded signal output from the analog matched filter shown in FIG. 7B is input from the analog data input terminal of the determination circuit to the input terminal (IN) of the comparator 42. On the other hand, a signal having a potential set as a threshold value is input from the threshold level input terminal (REF). This potential corresponds to the potential described as the threshold value in FIG.

  A signal having a potential corresponding to 1 is output from the output terminal (OUT) of the comparator 42 when the level of the signal input from the input terminal (IN) exceeds the threshold value. On the other hand, when the level of the signal input from the input terminal (IN) is below the threshold, a signal having a potential corresponding to 0 is output. Therefore, the time waveform of the signal output from the output terminal (OUT) of the comparator 42 is the time waveform shown in FIG. The time waveform shown in FIG. 7C corresponds to the time waveform shown in FIG. 3C1 described above.

  A signal having a time waveform shown in FIG. 7C is input to the input terminal (D) of the D flip-flop circuit 52. On the other hand, a clock signal is input to the clock signal input terminal (CLK) of the D flip-flop circuit 52. The clock signal input to the clock signal input terminal (CLK) is the clock signal shown in FIG. 3 (C2). That is, a threshold value input to the input terminal (D) is determined by this clock signal, and the output signal is latched. Since the principle of the latch operation has already been described, it will not be repeated here.

In FIG. 3 (C1), the widths of the rectangular pulses are shown to be equal, but actually the widths of the rectangular pulses are not equal as in the time waveform shown in FIG. 7 (C). However, since it is sufficient that the rising edge of the clock signal is included in the range of the width of the rectangular pulse, the widths of the rectangular pulses are not necessarily equal. However, the second delay is set so that the rising edge of the clock signal input to the clock signal input terminal (CLK) falls within the rectangular pulse width (W ₁ and W ₂ ) shown in FIG. 7C. It is necessary to adjust the position of the clock signal on the time axis by a circuit.

<Second embodiment>
The configuration and operation of the optical access network system according to the second embodiment will be described with reference to FIG. FIG. 8 is a schematic block diagram of an optical access network system according to the second embodiment. In the second embodiment, it is assumed that the number of subscribers is 16. The difference from the optical access network system of the first embodiment is that, in the optical access network system of the first embodiment, only one type of signal wavelength is used for communication, whereas the optical access network system of the second embodiment The access network system is a so-called WDM system that uses four types of wavelengths as signal wavelengths.

Therefore, the configuration of the portion where communication is performed with the signal wavelength λ ₁ is the same as that of the optical access network system of the first embodiment. By using four types of wavelengths from λ ₁ to λ ₄ as signal wavelengths, the number of users has been expanded to 4 times the system (ONU-1 to ONU-16). That is, by utilizing the wavelength lambda ₁ in ONU-4 from ONU-1, using a wavelength lambda ₂ in ONU-8 from ONU-5, using the wavelength lambda ₃ in ONU-12 from ONU-9, ONU-13 to use the wavelength λ ₄ in the ONU-16 from. The codes assigned to ONU-1, 5, 9 and 13 can be made common. Similarly, codes assigned to ONU-2, 6, 10 and 14, codes assigned to ONU-3, 7, 11 and 15, and codes assigned to ONU-4, 8, 12 and 16 can be made common. . Further, the first channel (ch1) to the 16th channel (ch16) are associated with ONU-1 to ONU-16, respectively. Of course, the above-described code assignment and channel assignment to the ONU are merely examples, and are not limited thereto.

By increasing the number of wavelengths used as signal wavelengths from λ ₁ to λ ₄ , optical multiplexers 66-1 and 66-4 corresponding to the optical multiplexer 66 in the optical access network system of the first embodiment Between the optical couplers 124-1 and 124-4 corresponding to the optical coupler 124, wavelength selective multiplexers / demultiplexers 50 and 54 having wavelength selectivity are required.

  As the wavelength selective multiplexer / demultiplexer having wavelength selectivity, for example, a WDM multiplexer / demultiplexer can be used. Further, it is also possible to use an apparatus in which an optical filter having a different transmission wavelength is installed in each port for outputting the optical coupler / branch having no wavelength selectivity and the branched light of the optical coupler / branch.

Also in the optical access network system of the second embodiment, the configuration of each part in which communication is performed with a signal wavelength of λ ₁ to λ ₄ is the same as that of the optical access network system of the first embodiment. Obviously, it is possible to obtain the effect of transmitting / receiving a high-speed signal and not having to increase the number of wavelengths used as compared with the conventional optical system of the same type.

1 is a schematic block diagram of an optical access network system according to a first embodiment. It is a figure where it uses for description of the process in which a transmission signal is encoded. It is a figure where it uses for description of the process in which a received signal is decoded. It is a figure where it uses for description of a mode that the reflected light from an optical connector mixes in a received signal processing part. It is a figure which shows about the relationship of the peak position of an autocorrelation waveform at the time of decoding the signal in which the received signal and the reflected transmission signal were mixed. It is a schematic block diagram of an analog matched filter. It is a figure used for description of the schematic block block diagram of a determination circuit, and its operation principle. FIG. 6 is a schematic block configuration diagram of an optical access network system according to a second embodiment.

Explanation of symbols

10: Optical terminal unit (ONU)
12, 102: Light processing section
14, 104: Electric processing section
16, 124, 124-1, 124-4: Optical coupler
18, 126: Light receiving element
20, 122: Light emitting element
22, 108: Received signal processor
24, 106: Transmission signal processor
26, 36, 130: Electric signal splitter
28, 128: Automatic gain control element
30: Decryption processing circuit
34: Clock signal recovery circuit
38: Divider
40: Second delay circuit
42: Comparator
44: Analog matched filter
46: Judgment circuit
50, 54: Wavelength selective multiplexer / demultiplexer
52: D flip-flop circuit
56: Sign assignment circuit
58: First delay circuit
60, 120: Driver (Amplifier)
61, 64, 68, 72: Optical connector
66, 66-1, 66-4: Optical coupler
70: Optical fiber transmission line
74, 76: Branch optical fiber transmission line
82: Encoding processing circuit
100: Optical line terminator (OLT)
110: Clock signal generation circuit
116: Encoding circuit sequence
118, 154, 156: Electric signal multiplexer
132: Decoding processing circuit array
140: Analog shift register
142: Adder for positive signal
144: Adder for negative signal
146: Analog adder
148: Low-pass filter
150: Amplifier
152: Inverting amplifier

Claims (2)

An optical coupler is provided at one end of the optical fiber transmission line.
Between an optical line terminating device coupled to the other end of the optical fiber transmission line and a plurality of optical terminal devices coupled to each of a plurality of branched optical fiber transmission lines formed by branching by the optical coupler. An optical access network system for performing bidirectional optical communication by code division multiplexing by assigning different codes to each of the plurality of optical terminal devices,
Each of the plurality of optical terminal devices and the optical line terminating device includes a transmission signal processing unit that encodes a transmission signal to generate and outputs an encoded transmission signal, and a code division multiplexed signal transmitted by code division multiplexing And a reception signal processing unit that decodes the code division multiplexed signal and extracts the reception signal,
The received signal processing unit includes a decoding processing circuit that decodes the code division multiplexed signal, and the decoding processing circuit includes an analog matched filter and a determination circuit,
The analog matched filter includes an analog shift register, a plus signal adder, a minus signal adder, an analog adder that adds output signals from the plus signal adder and the minus signal adder, respectively. An optical access network system comprising a low-pass filter.   The transmission signal processing unit includes a code adding circuit that encodes the transmission signal, and a delay circuit that is connected to a subsequent stage of the code adding circuit and adjusts and outputs the phase of the encoded transmission signal. The optical access network system according to claim 1.