JPH04103021U - optical receiver circuit - Google Patents
optical receiver circuitInfo
- Publication number
- JPH04103021U JPH04103021U JP1991004900U JP490091U JPH04103021U JP H04103021 U JPH04103021 U JP H04103021U JP 1991004900 U JP1991004900 U JP 1991004900U JP 490091 U JP490091 U JP 490091U JP H04103021 U JPH04103021 U JP H04103021U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- optical
- amplifier
- electrical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 18
- 238000000605 extraction Methods 0.000 claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 6
- 230000006866 deterioration Effects 0.000 claims abstract description 5
- 230000005540 biological transmission Effects 0.000 claims 1
- 230000008929 regeneration Effects 0.000 abstract description 6
- 238000011069 regeneration method Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- 230000004069 differentiation Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 1
- 238000005315 distribution function Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Abstract
(57)【要約】
【構成】光入力信号を電気信号に変換する光−電気変換
素子1と、該電気信号と等化増幅する増幅器2,3,4
と、前記光−電気変換素子の増倍率および前記増幅器の
利得を制御する利得制御回路5と、前記増幅器の出力信
号を識別再生のための信号とタイミング抽出のための信
号とに2分配する信号分配器6と、クロック信号を抽出
するタイミング抽出回路7と、該クロック信号により識
別再生する識別再生回路8とを有する光受信回路におい
て、前記信号分配器6は、前記識別再生回路8への入力
信号を実質的に無損失で波形劣化なく分配し、かつ前記
増幅器出力信号の微分信号を発生し電気タイミング抽出
回路7へ分配する伝達特性をもつ分布定数線路型方向性
結合器てあることを特徴とする。
【効果】増幅出力信号の識別再生用およびクロック抽出
用ヘの2分配を、ギガビット領域において、波形劣化無
しに行え、かつ分配および微分の両機能を信号分配器に
あわせ持たせることができる。
(57) [Summary] [Structure] Optical-to-electrical conversion element 1 that converts an optical input signal into an electrical signal, and amplifiers 2, 3, and 4 that equalize and amplify the electrical signal.
, a gain control circuit 5 that controls the multiplication factor of the opto-electric conversion element and the gain of the amplifier, and a signal that divides the output signal of the amplifier into a signal for identification and reproduction and a signal for timing extraction. In an optical receiving circuit including a distributor 6, a timing extraction circuit 7 for extracting a clock signal, and an identification/regeneration circuit 8 for identification/regeneration based on the clock signal, the signal distributor 6 is configured to provide input to the identification/regeneration circuit 8. It is characterized by a distributed constant line type directional coupler having a transfer characteristic that distributes signals substantially without loss and without waveform deterioration, and generates a differential signal of the amplifier output signal and distributes it to the electrical timing extraction circuit 7. shall be. [Effect] The amplified output signal can be divided into two parts, one for identification and reproduction and one for clock extraction, in the gigabit region without waveform deterioration, and the signal distributor can have both distribution and differentiation functions.
Description
【0001】0001
本考案は光受信回路に関し、特にギガビット領域を超えるような大容量の光通 信システムに使用され光受信回路に関する。 This invention relates to optical receiver circuits, especially for large-capacity optical communications exceeding the gigabit range. It relates to optical receiving circuits used in communication systems.
【0002】0002
従来の光受信回路では、図2に示すように光入力信号を電気信号に変換するア バランシェフォトダイオード(以下APDと記す)1、その電気信号を増幅する 前置増幅器2、可変利得増幅器3、主増幅器4で構成される増幅器により光受信 信号を電気信号に変換して等化増幅し、主増幅器4の出力レベルに応じて利得制 御回路5によりADP1の増倍率Mと可変利得増幅器3の利得とを制御して、光 受信レベルの変化に対し主増幅器4の出力レベルを一定化する。一方、主増幅器 4の出力信号は、エミッタホロワあるいは抵抗分配器等により構成される信号分 配器10により2分配され、一方は微分回路11、クロック抽出回路7によりク ロック信号を抽出され、識別再生回路8にてもう一方の信号分配器の10の出力 信号をクロック信号のタイミングで識別再生する。 In conventional optical receiving circuits, as shown in Figure 2, there is an adapter that converts an optical input signal into an electrical signal. Balanche photodiode (hereinafter referred to as APD) 1, amplifies the electrical signal Optical reception is performed by an amplifier consisting of a preamplifier 2, a variable gain amplifier 3, and a main amplifier 4. The signal is converted into an electrical signal, equalized and amplified, and the gain is controlled according to the output level of the main amplifier 4. The control circuit 5 controls the multiplication factor M of the ADP 1 and the gain of the variable gain amplifier 3. The output level of the main amplifier 4 is made constant against changes in the reception level. On the other hand, the main amplifier The output signal of 4 is a signal component composed of an emitter follower or a resistor divider, etc. The clock is divided into two by the distributor 10, and one is clocked by the differentiating circuit 11 and the clock extracting circuit 7. The lock signal is extracted, and the identification and regeneration circuit 8 outputs the other signal distributor 10. A signal is identified and reproduced at the timing of a clock signal.
【0003】0003
この従来の光受信回路では、主増幅回路4の出力信号を2分配する際、エミッ タホロワもしくは抵抗分配器の信号分配器10によっているが、エミッタホロワ ではギガビット領域での高速動作を実現し波形劣化でなく分配することが困難で あり、また抵抗分配器では分配損失が大きいという問題点がある。 In this conventional optical receiving circuit, when dividing the output signal of the main amplifier circuit 4 into two, the emitter Emitter follower or resistor divider signal divider 10 is used. It is difficult to realize high-speed operation in the gigabit region and distribute without waveform deterioration. There is also the problem that the resistance divider has a large distribution loss.
【0004】0004
本考案の回路は、光入力信号を電気信号に変換する光−電気変換素子と、該電 気信号と等化増幅する増幅器と、前記光−電気変換素子の増倍率および前記増幅 器の利得を制御する利得制御回路と、前記増幅器の出力信号を識別再生のための 信号とタイミング抽出のための信号とに2分配する信号分配器と、クロック信号 を抽出するタイミング抽出回路と、該クロック信号により識別再生する識別再生 回路とを有する光受信回路において、 前記信号分配器は、前記識別再生回路への入力信号を実質的に無損失で波形劣化 なく分配し、かつ前記増幅器出力信号の微分信号を発生し電気タイミング抽出回 路へ分配する伝達特性をもつ分布定数線路型方向性結合器てあることを特徴とす る。 The circuit of the present invention includes an optical-to-electrical conversion element that converts an optical input signal into an electrical signal, and the electrical signal. an amplifier that equalizes and amplifies the optical signal, a multiplication factor of the optical-to-electrical conversion element, and the amplification a gain control circuit for controlling the gain of the amplifier; and a gain control circuit for identifying and reproducing the output signal of the amplifier. A signal divider that divides the signal into two, a signal and a signal for timing extraction, and a clock signal A timing extraction circuit that extracts the clock signal, and an identification reproduction circuit that performs identification reproduction based on the clock signal. In an optical receiving circuit having a circuit, The signal distributor reduces the waveform of the input signal to the identification and regeneration circuit with substantially no loss. The electrical timing extraction circuit generates a differential signal of the amplifier output signal. It is characterized by a distributed constant line type directional coupler having a transfer characteristic that distributes the distribution to the Ru.
【0005】[0005]
次に本考案について図面を参照して説明する。図1は本考案の一実施例のブロ ック図である。 Next, the present invention will be explained with reference to the drawings. Figure 1 shows a block diagram of one embodiment of the present invention. This is a diagram.
【0006】 APD1によって変換された電気信号は、前置増幅器2,可変利得増幅器3, 主増幅器4により等化増幅され、その等化出力信号はカプラー6の入力ポートP ORT1に入力される。カプラー6は、分布定数線路型の方向性結合器であり、 出力ポートPORT4を特性インピーダンスZ0 の終端器9で終端した時のカプ ラー6の入力ポートPORT1から出力ポートPORT2,PORT3への伝達 特性は図3に示すとおりである。入力ポートPORT1から入力された等化出力 信号は、出力ポートPORT2では微分信号となり、また出力ポートPORT3 では無損失の等価信号として分配される。The electrical signal converted by the APD 1 is equalized and amplified by a preamplifier 2 , a variable gain amplifier 3 , and a main amplifier 4 , and the equalized output signal is input to an input port PORT 1 of a coupler 6 . The coupler 6 is a distributed constant line type directional coupler, and the transfer characteristics from the input port PORT1 of the coupler 6 to the output ports PORT2 and PORT3 when the output port PORT4 is terminated with a terminator 9 having a characteristic impedance Z 0 are as follows. As shown in FIG. The equalized output signal input from the input port PORT1 becomes a differential signal at the output port PORT2, and is distributed as a lossless equivalent signal at the output port PORT3.
【0007】 カプラー6の出力ポートPORT2で得る微分信号は、クロック抽出回路7に 入力されてクロック信号を抽出され、このクロック信号を識別回路8に入力して カプラー6の出力ポートPORT3で得られる等化信号の識別再生を行う。[0007] The differential signal obtained at the output port PORT2 of the coupler 6 is sent to the clock extraction circuit 7. The input clock signal is extracted, and this clock signal is input to the identification circuit 8. The equalized signal obtained at the output port PORT3 of the coupler 6 is identified and reproduced.
【0008】[0008]
以上説明したように本考案は、等化出力信号を識別再生用およびクロック抽出 用に2分配する信号分配器として分布定数線路型方向性結合器を用いることによ り、ギガビット領域において波形劣化のない分配が可能となり、また分配機能と 微分機能とをあわせ持たせることができるという効果を有する。 As explained above, the present invention uses the equalized output signal for identification and reproduction and clock extraction. By using a distributed constant line type directional coupler as a signal splitter that divides the signal into two, This enables distribution without waveform deterioration in the gigabit domain, and also enables distribution functions and It has the effect of being able to have a differential function as well.
【図1】本考案の一実施例のブロック図[Figure 1] Block diagram of one embodiment of the present invention
【図2】従来の光受信回路のブロック図[Figure 2] Block diagram of a conventional optical receiver circuit
【図3】本考案の実施例におけるカプラー6の伝達特性
を例示する特性図FIG. 3 is a characteristic diagram illustrating the transfer characteristics of the coupler 6 in the embodiment of the present invention.
1 アバランシェフォトダイオード(APD) 2 前置増幅器 3 可変利得増幅器 4 主増幅器 5 利得制御回路 6 カプラー 7 クロック抽出回路 8 識別再生回路 9 終端器 10 信号分配器 11 微分回路 1 Avalanche photodiode (APD) 2 Preamplifier 3 Variable gain amplifier 4 Main amplifier 5 Gain control circuit 6 Coupler 7 Clock extraction circuit 8 Identification and regeneration circuit 9 Terminal 10 Signal splitter 11 Differential circuit
Claims (1)
気変換素子と、該電気信号と等化増幅する増幅器と、前
記光−電気変換素子の増倍率および前記増幅器の利得を
制御する利得制御回路と、前記増幅器の出力信号を識別
再生のための信号とタイミング抽出のための信号とに2
分配する信号分配器と、クロック信号を抽出するタイミ
ング抽出回路と、該クロック信号により識別再生する識
別再生回路とを有する光受信回路において、前記信号分
配器は、前記識別再生回路への入力信号を実質的に無損
失で波形劣化なく分配し、かつ前記増幅器出力信号の微
分信号を発生し電気タイミング抽出回路へ分配する伝達
特性をもつ分布定数線路型方向性結合器てあることを特
徴とする光受信回路。1. An optical-electrical conversion element that converts an optical input signal into an electrical signal, an amplifier that equalizes and amplifies the electrical signal, and a gain that controls the multiplication factor of the optical-electrical conversion element and the gain of the amplifier. a control circuit, a signal for identifying and reproducing the output signal of the amplifier, and a signal for timing extraction;
In the optical receiving circuit, the signal distributor includes a signal distributor for distributing a signal, a timing extraction circuit for extracting a clock signal, and an identification reproducing circuit for discriminating and reproducing based on the clock signal. An optical optical system characterized by having a distributed constant line type directional coupler having a transmission characteristic that distributes the signal substantially without loss and without waveform deterioration, generates a differential signal of the amplifier output signal, and distributes it to an electrical timing extraction circuit. receiving circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1991004900U JP2580472Y2 (en) | 1991-02-08 | 1991-02-08 | Optical receiving circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1991004900U JP2580472Y2 (en) | 1991-02-08 | 1991-02-08 | Optical receiving circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04103021U true JPH04103021U (en) | 1992-09-04 |
JP2580472Y2 JP2580472Y2 (en) | 1998-09-10 |
Family
ID=31735044
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1991004900U Expired - Lifetime JP2580472Y2 (en) | 1991-02-08 | 1991-02-08 | Optical receiving circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2580472Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08274721A (en) * | 1995-03-31 | 1996-10-18 | Nec Corp | Method and device for optical transmission |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6247230A (en) * | 1985-08-27 | 1987-02-28 | Nec Corp | Optical receiving circuit |
JPS62105541A (en) * | 1985-11-01 | 1987-05-16 | Fujitsu Ltd | Optical receiving circuit |
JPH036132A (en) * | 1989-06-02 | 1991-01-11 | Nippon Hoso Kyokai <Nhk> | Shf band same frequency repeating system |
-
1991
- 1991-02-08 JP JP1991004900U patent/JP2580472Y2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6247230A (en) * | 1985-08-27 | 1987-02-28 | Nec Corp | Optical receiving circuit |
JPS62105541A (en) * | 1985-11-01 | 1987-05-16 | Fujitsu Ltd | Optical receiving circuit |
JPH036132A (en) * | 1989-06-02 | 1991-01-11 | Nippon Hoso Kyokai <Nhk> | Shf band same frequency repeating system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08274721A (en) * | 1995-03-31 | 1996-10-18 | Nec Corp | Method and device for optical transmission |
Also Published As
Publication number | Publication date |
---|---|
JP2580472Y2 (en) | 1998-09-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980526 |