JPS6196556U - - Google Patents

Info

Publication number
JPS6196556U
JPS6196556U JP18175184U JP18175184U JPS6196556U JP S6196556 U JPS6196556 U JP S6196556U JP 18175184 U JP18175184 U JP 18175184U JP 18175184 U JP18175184 U JP 18175184U JP S6196556 U JPS6196556 U JP S6196556U
Authority
JP
Japan
Prior art keywords
disc
integrated circuit
lead frame
shaped
rounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18175184U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18175184U priority Critical patent/JPS6196556U/ja
Publication of JPS6196556U publication Critical patent/JPS6196556U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第1図aとbは本考案実施例の平面図と正面図
、第2図aとbは従来例の平面図と断面図である
。 図中、11はプラスチツク・パツケージIC、
12はチツプ、13はステージ、14はリード、
15は電極、16はワイヤ、をそれぞれ示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. 集積回路を形成した円板状シリコンウエハをリ
    ードフレームの円板状ステージに接着し、該集積
    回路の電極を該リードフレームのリードにワイヤ
    で接続した組立体を丸みをもたせて樹脂封止して
    なることを特徴とする半導体装置。
JP18175184U 1984-11-30 1984-11-30 Pending JPS6196556U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18175184U JPS6196556U (ja) 1984-11-30 1984-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18175184U JPS6196556U (ja) 1984-11-30 1984-11-30

Publications (1)

Publication Number Publication Date
JPS6196556U true JPS6196556U (ja) 1986-06-21

Family

ID=30739292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18175184U Pending JPS6196556U (ja) 1984-11-30 1984-11-30

Country Status (1)

Country Link
JP (1) JPS6196556U (ja)

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