JPH0317629U - - Google Patents

Info

Publication number
JPH0317629U
JPH0317629U JP7748989U JP7748989U JPH0317629U JP H0317629 U JPH0317629 U JP H0317629U JP 7748989 U JP7748989 U JP 7748989U JP 7748989 U JP7748989 U JP 7748989U JP H0317629 U JPH0317629 U JP H0317629U
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor chip
resin
tabs
molding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7748989U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7748989U priority Critical patent/JPH0317629U/ja
Publication of JPH0317629U publication Critical patent/JPH0317629U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例を組立て工程順に示
し、aは樹脂封止前の状態を示す縦断面図、bは
樹脂封止後の状態を示す縦断面図、第2図は従来
の樹脂封止型半導体装置の一例を示す縦断面図で
ある。 1…半導体チツプ、2…タブ、3…ボンデイン
グワイヤ、4…封止樹脂部、5…リードフレーム
、6…電極。

Claims (1)

    【実用新案登録請求の範囲】
  1. 電極群を有する半導体チツプと、タブを有しな
    いリードフレームと、該リードフレームとこれに
    対応する前記各電極とを電気的に接続するボンデ
    イングワイヤと、上記各部品をモールドする封止
    樹脂部とを備え、前記半導体チツプは前記リード
    フレームと遊離した位置に設けられていることを
    特徴とする樹脂封止型半導体装置。
JP7748989U 1989-06-30 1989-06-30 Pending JPH0317629U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7748989U JPH0317629U (ja) 1989-06-30 1989-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7748989U JPH0317629U (ja) 1989-06-30 1989-06-30

Publications (1)

Publication Number Publication Date
JPH0317629U true JPH0317629U (ja) 1991-02-21

Family

ID=31619923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7748989U Pending JPH0317629U (ja) 1989-06-30 1989-06-30

Country Status (1)

Country Link
JP (1) JPH0317629U (ja)

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